if_mec.c revision 1.11
1 /* $NetBSD: if_mec.c,v 1.11 2007/07/09 20:52:26 ad Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Izumi Tsutsui. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Copyright (c) 2003 Christopher SEKIYA 32 * All rights reserved. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. All advertising materials mentioning features or use of this software 43 * must display the following acknowledgement: 44 * This product includes software developed for the 45 * NetBSD Project. See http://www.NetBSD.org/ for 46 * information about NetBSD. 47 * 4. The name of the author may not be used to endorse or promote products 48 * derived from this software without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 51 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 52 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 53 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 54 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 55 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 56 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 57 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 58 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 59 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 */ 61 62 /* 63 * MACE MAC-110 ethernet driver 64 */ 65 66 #include <sys/cdefs.h> 67 __KERNEL_RCSID(0, "$NetBSD: if_mec.c,v 1.11 2007/07/09 20:52:26 ad Exp $"); 68 69 #include "opt_ddb.h" 70 #include "bpfilter.h" 71 #include "rnd.h" 72 73 #include <sys/param.h> 74 #include <sys/systm.h> 75 #include <sys/device.h> 76 #include <sys/callout.h> 77 #include <sys/mbuf.h> 78 #include <sys/malloc.h> 79 #include <sys/kernel.h> 80 #include <sys/socket.h> 81 #include <sys/ioctl.h> 82 #include <sys/errno.h> 83 84 #if NRND > 0 85 #include <sys/rnd.h> 86 #endif 87 88 #include <net/if.h> 89 #include <net/if_dl.h> 90 #include <net/if_media.h> 91 #include <net/if_ether.h> 92 93 #if NBPFILTER > 0 94 #include <net/bpf.h> 95 #endif 96 97 #include <machine/bus.h> 98 #include <machine/intr.h> 99 #include <machine/machtype.h> 100 101 #include <dev/mii/mii.h> 102 #include <dev/mii/miivar.h> 103 104 #include <sgimips/mace/macevar.h> 105 #include <sgimips/mace/if_mecreg.h> 106 107 #include <dev/arcbios/arcbios.h> 108 #include <dev/arcbios/arcbiosvar.h> 109 110 /* #define MEC_DEBUG */ 111 112 #ifdef MEC_DEBUG 113 #define MEC_DEBUG_RESET 0x01 114 #define MEC_DEBUG_START 0x02 115 #define MEC_DEBUG_STOP 0x04 116 #define MEC_DEBUG_INTR 0x08 117 #define MEC_DEBUG_RXINTR 0x10 118 #define MEC_DEBUG_TXINTR 0x20 119 uint32_t mec_debug = 0; 120 #define DPRINTF(x, y) if (mec_debug & (x)) printf y 121 #else 122 #define DPRINTF(x, y) /* nothing */ 123 #endif 124 125 /* 126 * Transmit descriptor list size 127 */ 128 #define MEC_NTXDESC 64 129 #define MEC_NTXDESC_MASK (MEC_NTXDESC - 1) 130 #define MEC_NEXTTX(x) (((x) + 1) & MEC_NTXDESC_MASK) 131 132 /* 133 * software state for TX 134 */ 135 struct mec_txsoft { 136 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 137 bus_dmamap_t txs_dmamap; /* our DMA map */ 138 uint32_t txs_flags; 139 #define MEC_TXS_BUFLEN_MASK 0x0000007f /* data len in txd_buf */ 140 #define MEC_TXS_TXDBUF 0x00000080 /* txd_buf is used */ 141 #define MEC_TXS_TXDPTR1 0x00000100 /* txd_ptr[0] is used */ 142 }; 143 144 /* 145 * Transmit buffer descriptor 146 */ 147 #define MEC_TXDESCSIZE 128 148 #define MEC_NTXPTR 3 149 #define MEC_TXD_BUFOFFSET \ 150 (sizeof(uint64_t) + MEC_NTXPTR * sizeof(uint64_t)) 151 #define MEC_TXD_BUFSIZE (MEC_TXDESCSIZE - MEC_TXD_BUFOFFSET) 152 #define MEC_TXD_BUFSTART(len) (MEC_TXD_BUFSIZE - (len)) 153 #define MEC_TXD_ALIGN 8 154 #define MEC_TXD_ROUNDUP(addr) \ 155 (((addr) + (MEC_TXD_ALIGN - 1)) & ~((uint64_t)MEC_TXD_ALIGN - 1)) 156 157 struct mec_txdesc { 158 volatile uint64_t txd_cmd; 159 #define MEC_TXCMD_DATALEN 0x000000000000ffff /* data length */ 160 #define MEC_TXCMD_BUFSTART 0x00000000007f0000 /* start byte offset */ 161 #define TXCMD_BUFSTART(x) ((x) << 16) 162 #define MEC_TXCMD_TERMDMA 0x0000000000800000 /* stop DMA on abort */ 163 #define MEC_TXCMD_TXINT 0x0000000001000000 /* INT after TX done */ 164 #define MEC_TXCMD_PTR1 0x0000000002000000 /* valid 1st txd_ptr */ 165 #define MEC_TXCMD_PTR2 0x0000000004000000 /* valid 2nd txd_ptr */ 166 #define MEC_TXCMD_PTR3 0x0000000008000000 /* valid 3rd txd_ptr */ 167 #define MEC_TXCMD_UNUSED 0xfffffffff0000000ULL /* should be zero */ 168 169 #define txd_stat txd_cmd 170 #define MEC_TXSTAT_LEN 0x000000000000ffff /* TX length */ 171 #define MEC_TXSTAT_COLCNT 0x00000000000f0000 /* collision count */ 172 #define MEC_TXSTAT_COLCNT_SHIFT 16 173 #define MEC_TXSTAT_LATE_COL 0x0000000000100000 /* late collision */ 174 #define MEC_TXSTAT_CRCERROR 0x0000000000200000 /* */ 175 #define MEC_TXSTAT_DEFERRED 0x0000000000400000 /* */ 176 #define MEC_TXSTAT_SUCCESS 0x0000000000800000 /* TX complete */ 177 #define MEC_TXSTAT_TOOBIG 0x0000000001000000 /* */ 178 #define MEC_TXSTAT_UNDERRUN 0x0000000002000000 /* */ 179 #define MEC_TXSTAT_COLLISIONS 0x0000000004000000 /* */ 180 #define MEC_TXSTAT_EXDEFERRAL 0x0000000008000000 /* */ 181 #define MEC_TXSTAT_COLLIDED 0x0000000010000000 /* */ 182 #define MEC_TXSTAT_UNUSED 0x7fffffffe0000000ULL /* should be zero */ 183 #define MEC_TXSTAT_SENT 0x8000000000000000ULL /* packet sent */ 184 185 uint64_t txd_ptr[MEC_NTXPTR]; 186 #define MEC_TXPTR_UNUSED2 0x0000000000000007 /* should be zero */ 187 #define MEC_TXPTR_DMAADDR 0x00000000fffffff8 /* TX DMA address */ 188 #define MEC_TXPTR_LEN 0x0000ffff00000000ULL /* buffer length */ 189 #define TXPTR_LEN(x) ((uint64_t)(x) << 32) 190 #define MEC_TXPTR_UNUSED1 0xffff000000000000ULL /* should be zero */ 191 192 uint8_t txd_buf[MEC_TXD_BUFSIZE]; 193 }; 194 195 /* 196 * Receive buffer size 197 */ 198 #define MEC_NRXDESC 16 199 #define MEC_NRXDESC_MASK (MEC_NRXDESC - 1) 200 #define MEC_NEXTRX(x) (((x) + 1) & MEC_NRXDESC_MASK) 201 202 /* 203 * Receive buffer description 204 */ 205 #define MEC_RXDESCSIZE 4096 /* umm, should be 4kbyte aligned */ 206 #define MEC_RXD_NRXPAD 3 207 #define MEC_RXD_DMAOFFSET (1 + MEC_RXD_NRXPAD) 208 #define MEC_RXD_BUFOFFSET (MEC_RXD_DMAOFFSET * sizeof(uint64_t)) 209 #define MEC_RXD_BUFSIZE (MEC_RXDESCSIZE - MEC_RXD_BUFOFFSET) 210 211 struct mec_rxdesc { 212 volatile uint64_t rxd_stat; 213 #define MEC_RXSTAT_LEN 0x000000000000ffff /* data length */ 214 #define MEC_RXSTAT_VIOLATION 0x0000000000010000 /* code violation (?) */ 215 #define MEC_RXSTAT_UNUSED2 0x0000000000020000 /* unknown (?) */ 216 #define MEC_RXSTAT_CRCERROR 0x0000000000040000 /* CRC error */ 217 #define MEC_RXSTAT_MULTICAST 0x0000000000080000 /* multicast packet */ 218 #define MEC_RXSTAT_BROADCAST 0x0000000000100000 /* broadcast packet */ 219 #define MEC_RXSTAT_INVALID 0x0000000000200000 /* invalid preamble */ 220 #define MEC_RXSTAT_LONGEVENT 0x0000000000400000 /* long packet */ 221 #define MEC_RXSTAT_BADPACKET 0x0000000000800000 /* bad packet */ 222 #define MEC_RXSTAT_CAREVENT 0x0000000001000000 /* carrier event */ 223 #define MEC_RXSTAT_MATCHMCAST 0x0000000002000000 /* match multicast */ 224 #define MEC_RXSTAT_MATCHMAC 0x0000000004000000 /* match MAC */ 225 #define MEC_RXSTAT_SEQNUM 0x00000000f8000000 /* sequence number */ 226 #define MEC_RXSTAT_CKSUM 0x0000ffff00000000ULL /* IP checksum */ 227 #define MEC_RXSTAT_UNUSED1 0x7fff000000000000ULL /* should be zero */ 228 #define MEC_RXSTAT_RECEIVED 0x8000000000000000ULL /* set to 1 on RX */ 229 uint64_t rxd_pad1[MEC_RXD_NRXPAD]; 230 uint8_t rxd_buf[MEC_RXD_BUFSIZE]; 231 }; 232 233 /* 234 * control structures for DMA ops 235 */ 236 struct mec_control_data { 237 /* 238 * TX descriptors and buffers 239 */ 240 struct mec_txdesc mcd_txdesc[MEC_NTXDESC]; 241 242 /* 243 * RX descriptors and buffers 244 */ 245 struct mec_rxdesc mcd_rxdesc[MEC_NRXDESC]; 246 }; 247 248 /* 249 * It _seems_ there are some restrictions on descriptor address: 250 * 251 * - Base address of txdescs should be 8kbyte aligned 252 * - Each txdesc should be 128byte aligned 253 * - Each rxdesc should be 4kbyte aligned 254 * 255 * So we should specify 8k align to allocalte txdescs. 256 * In this case, sizeof(struct mec_txdesc) * MEC_NTXDESC is 8192 257 * so rxdescs are also allocated at 4kbyte aligned. 258 */ 259 #define MEC_CONTROL_DATA_ALIGN (8 * 1024) 260 261 #define MEC_CDOFF(x) offsetof(struct mec_control_data, x) 262 #define MEC_CDTXOFF(x) MEC_CDOFF(mcd_txdesc[(x)]) 263 #define MEC_CDRXOFF(x) MEC_CDOFF(mcd_rxdesc[(x)]) 264 265 /* 266 * software state per device 267 */ 268 struct mec_softc { 269 struct device sc_dev; /* generic device structures */ 270 271 bus_space_tag_t sc_st; /* bus_space tag */ 272 bus_space_handle_t sc_sh; /* bus_space handle */ 273 bus_dma_tag_t sc_dmat; /* bus_dma tag */ 274 void *sc_sdhook; /* shoutdown hook */ 275 276 struct ethercom sc_ethercom; /* Ethernet common part */ 277 278 struct mii_data sc_mii; /* MII/media information */ 279 int sc_phyaddr; /* MII address */ 280 struct callout sc_tick_ch; /* tick callout */ 281 282 uint8_t sc_enaddr[ETHER_ADDR_LEN]; /* MAC address */ 283 284 bus_dmamap_t sc_cddmamap; /* bus_dma map for control data */ 285 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 286 287 /* pointer to allocalted control data */ 288 struct mec_control_data *sc_control_data; 289 #define sc_txdesc sc_control_data->mcd_txdesc 290 #define sc_rxdesc sc_control_data->mcd_rxdesc 291 292 /* software state for TX descs */ 293 struct mec_txsoft sc_txsoft[MEC_NTXDESC]; 294 295 int sc_txpending; /* number of TX requests pending */ 296 int sc_txdirty; /* first dirty TX descriptor */ 297 int sc_txlast; /* last used TX descriptor */ 298 299 int sc_rxptr; /* next ready RX buffer */ 300 301 #if NRND > 0 302 rndsource_element_t sc_rnd_source; /* random source */ 303 #endif 304 }; 305 306 #define MEC_CDTXADDR(sc, x) ((sc)->sc_cddma + MEC_CDTXOFF(x)) 307 #define MEC_CDRXADDR(sc, x) ((sc)->sc_cddma + MEC_CDRXOFF(x)) 308 309 #define MEC_TXDESCSYNC(sc, x, ops) \ 310 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 311 MEC_CDTXOFF(x), MEC_TXDESCSIZE, (ops)) 312 #define MEC_TXCMDSYNC(sc, x, ops) \ 313 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 314 MEC_CDTXOFF(x), sizeof(uint64_t), (ops)) 315 316 #define MEC_RXSTATSYNC(sc, x, ops) \ 317 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 318 MEC_CDRXOFF(x), sizeof(uint64_t), (ops)) 319 #define MEC_RXBUFSYNC(sc, x, len, ops) \ 320 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 321 MEC_CDRXOFF(x) + MEC_RXD_BUFOFFSET, \ 322 MEC_ETHER_ALIGN + (len), (ops)) 323 324 /* XXX these values should be moved to <net/if_ether.h> ? */ 325 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 326 #define MEC_ETHER_ALIGN 2 327 328 #ifdef DDB 329 #define STATIC 330 #else 331 #define STATIC static 332 #endif 333 334 STATIC int mec_match(struct device *, struct cfdata *, void *); 335 STATIC void mec_attach(struct device *, struct device *, void *); 336 337 STATIC int mec_mii_readreg(struct device *, int, int); 338 STATIC void mec_mii_writereg(struct device *, int, int, int); 339 STATIC int mec_mii_wait(struct mec_softc *); 340 STATIC void mec_statchg(struct device *); 341 STATIC void mec_mediastatus(struct ifnet *, struct ifmediareq *); 342 STATIC int mec_mediachange(struct ifnet *); 343 344 static void enaddr_aton(const char *, uint8_t *); 345 346 STATIC int mec_init(struct ifnet * ifp); 347 STATIC void mec_start(struct ifnet *); 348 STATIC void mec_watchdog(struct ifnet *); 349 STATIC void mec_tick(void *); 350 STATIC int mec_ioctl(struct ifnet *, u_long, void *); 351 STATIC void mec_reset(struct mec_softc *); 352 STATIC void mec_setfilter(struct mec_softc *); 353 STATIC int mec_intr(void *arg); 354 STATIC void mec_stop(struct ifnet *, int); 355 STATIC void mec_rxintr(struct mec_softc *); 356 STATIC void mec_txintr(struct mec_softc *); 357 STATIC void mec_shutdown(void *); 358 359 CFATTACH_DECL(mec, sizeof(struct mec_softc), 360 mec_match, mec_attach, NULL, NULL); 361 362 static int mec_matched = 0; 363 364 STATIC int 365 mec_match(struct device *parent, struct cfdata *match, void *aux) 366 { 367 368 /* allow only one device */ 369 if (mec_matched) 370 return 0; 371 372 mec_matched = 1; 373 return 1; 374 } 375 376 STATIC void 377 mec_attach(struct device *parent, struct device *self, void *aux) 378 { 379 struct mec_softc *sc = (void *)self; 380 struct mace_attach_args *maa = aux; 381 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 382 uint32_t command; 383 const char *macaddr; 384 struct mii_softc *child; 385 bus_dma_segment_t seg; 386 int i, err, rseg; 387 388 sc->sc_st = maa->maa_st; 389 if (bus_space_subregion(sc->sc_st, maa->maa_sh, 390 maa->maa_offset, 0, &sc->sc_sh) != 0) { 391 printf(": can't map i/o space\n"); 392 return; 393 } 394 395 /* set up DMA structures */ 396 sc->sc_dmat = maa->maa_dmat; 397 398 /* 399 * Allocate the control data structures, and create and load the 400 * DMA map for it. 401 */ 402 if ((err = bus_dmamem_alloc(sc->sc_dmat, 403 sizeof(struct mec_control_data), MEC_CONTROL_DATA_ALIGN, 0, 404 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 405 printf(": unable to allocate control data, error = %d\n", err); 406 goto fail_0; 407 } 408 /* 409 * XXX needs re-think... 410 * control data structures contain whole RX data buffer, so 411 * BUS_DMA_COHERENT (which disables cache) may cause some performance 412 * issue on copying data from the RX buffer to mbuf on normal memory, 413 * though we have to make sure all bus_dmamap_sync(9) ops are called 414 * proprely in that case. 415 */ 416 if ((err = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 417 sizeof(struct mec_control_data), 418 (void **)&sc->sc_control_data, /*BUS_DMA_COHERENT*/ 0)) != 0) { 419 printf(": unable to map control data, error = %d\n", err); 420 goto fail_1; 421 } 422 memset(sc->sc_control_data, 0, sizeof(struct mec_control_data)); 423 424 if ((err = bus_dmamap_create(sc->sc_dmat, 425 sizeof(struct mec_control_data), 1, 426 sizeof(struct mec_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 427 printf(": unable to create control data DMA map, error = %d\n", 428 err); 429 goto fail_2; 430 } 431 if ((err = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 432 sc->sc_control_data, sizeof(struct mec_control_data), NULL, 433 BUS_DMA_NOWAIT)) != 0) { 434 printf(": unable to load control data DMA map, error = %d\n", 435 err); 436 goto fail_3; 437 } 438 439 /* create TX buffer DMA maps */ 440 for (i = 0; i < MEC_NTXDESC; i++) { 441 if ((err = bus_dmamap_create(sc->sc_dmat, 442 MCLBYTES, 1, MCLBYTES, 0, 0, 443 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 444 printf(": unable to create tx DMA map %d, error = %d\n", 445 i, err); 446 goto fail_4; 447 } 448 } 449 450 callout_init(&sc->sc_tick_ch, 0); 451 452 /* get ethernet address from ARCBIOS */ 453 if ((macaddr = ARCBIOS->GetEnvironmentVariable("eaddr")) == NULL) { 454 printf(": unable to get MAC address!\n"); 455 goto fail_4; 456 } 457 enaddr_aton(macaddr, sc->sc_enaddr); 458 459 /* reset device */ 460 mec_reset(sc); 461 462 command = bus_space_read_8(sc->sc_st, sc->sc_sh, MEC_MAC_CONTROL); 463 464 printf(": MAC-110 Ethernet, rev %d\n", 465 (command & MEC_MAC_REVISION) >> MEC_MAC_REVISION_SHIFT); 466 467 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 468 ether_sprintf(sc->sc_enaddr)); 469 470 /* Done, now attach everything */ 471 472 sc->sc_mii.mii_ifp = ifp; 473 sc->sc_mii.mii_readreg = mec_mii_readreg; 474 sc->sc_mii.mii_writereg = mec_mii_writereg; 475 sc->sc_mii.mii_statchg = mec_statchg; 476 477 /* Set up PHY properties */ 478 ifmedia_init(&sc->sc_mii.mii_media, 0, mec_mediachange, 479 mec_mediastatus); 480 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 481 MII_OFFSET_ANY, 0); 482 483 child = LIST_FIRST(&sc->sc_mii.mii_phys); 484 if (child == NULL) { 485 /* No PHY attached */ 486 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL, 487 0, NULL); 488 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL); 489 } else { 490 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 491 sc->sc_phyaddr = child->mii_phy; 492 } 493 494 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 495 ifp->if_softc = sc; 496 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 497 ifp->if_ioctl = mec_ioctl; 498 ifp->if_start = mec_start; 499 ifp->if_watchdog = mec_watchdog; 500 ifp->if_init = mec_init; 501 ifp->if_stop = mec_stop; 502 ifp->if_mtu = ETHERMTU; 503 IFQ_SET_READY(&ifp->if_snd); 504 505 if_attach(ifp); 506 ether_ifattach(ifp, sc->sc_enaddr); 507 508 /* establish interrupt */ 509 cpu_intr_establish(maa->maa_intr, maa->maa_intrmask, mec_intr, sc); 510 511 #if NRND > 0 512 rnd_attach_source(&sc->sc_rnd_source, sc->sc_dev.dv_xname, 513 RND_TYPE_NET, 0); 514 #endif 515 516 /* set shutdown hook to reset interface on powerdown */ 517 sc->sc_sdhook = shutdownhook_establish(mec_shutdown, sc); 518 519 return; 520 521 /* 522 * Free any resources we've allocated during the failed attach 523 * attempt. Do this in reverse order and fall though. 524 */ 525 fail_4: 526 for (i = 0; i < MEC_NTXDESC; i++) { 527 if (sc->sc_txsoft[i].txs_dmamap != NULL) 528 bus_dmamap_destroy(sc->sc_dmat, 529 sc->sc_txsoft[i].txs_dmamap); 530 } 531 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 532 fail_3: 533 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 534 fail_2: 535 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 536 sizeof(struct mec_control_data)); 537 fail_1: 538 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 539 fail_0: 540 return; 541 } 542 543 STATIC int 544 mec_mii_readreg(struct device *self, int phy, int reg) 545 { 546 struct mec_softc *sc = (void *)self; 547 bus_space_tag_t st = sc->sc_st; 548 bus_space_handle_t sh = sc->sc_sh; 549 uint64_t val; 550 int i; 551 552 if (mec_mii_wait(sc) != 0) 553 return 0; 554 555 bus_space_write_8(st, sh, MEC_PHY_ADDRESS, 556 (phy << MEC_PHY_ADDR_DEVSHIFT) | (reg & MEC_PHY_ADDR_REGISTER)); 557 bus_space_write_8(st, sh, MEC_PHY_READ_INITIATE, 1); 558 delay(25); 559 560 for (i = 0; i < 20; i++) { 561 delay(30); 562 563 val = bus_space_read_8(st, sh, MEC_PHY_DATA); 564 565 if ((val & MEC_PHY_DATA_BUSY) == 0) 566 return val & MEC_PHY_DATA_VALUE; 567 } 568 return 0; 569 } 570 571 STATIC void 572 mec_mii_writereg(struct device *self, int phy, int reg, int val) 573 { 574 struct mec_softc *sc = (void *)self; 575 bus_space_tag_t st = sc->sc_st; 576 bus_space_handle_t sh = sc->sc_sh; 577 578 if (mec_mii_wait(sc) != 0) { 579 printf("timed out writing %x: %x\n", reg, val); 580 return; 581 } 582 583 bus_space_write_8(st, sh, MEC_PHY_ADDRESS, 584 (phy << MEC_PHY_ADDR_DEVSHIFT) | (reg & MEC_PHY_ADDR_REGISTER)); 585 586 delay(60); 587 588 bus_space_write_8(st, sh, MEC_PHY_DATA, val & MEC_PHY_DATA_VALUE); 589 590 delay(60); 591 592 mec_mii_wait(sc); 593 } 594 595 STATIC int 596 mec_mii_wait(struct mec_softc *sc) 597 { 598 uint32_t busy; 599 int i, s; 600 601 for (i = 0; i < 100; i++) { 602 delay(30); 603 604 s = splhigh(); 605 busy = bus_space_read_8(sc->sc_st, sc->sc_sh, MEC_PHY_DATA); 606 splx(s); 607 608 if ((busy & MEC_PHY_DATA_BUSY) == 0) 609 return 0; 610 if (busy == 0xffff) /* XXX ? */ 611 return 0; 612 } 613 614 printf("%s: MII timed out\n", sc->sc_dev.dv_xname); 615 return 1; 616 } 617 618 STATIC void 619 mec_statchg(struct device *self) 620 { 621 struct mec_softc *sc = (void *)self; 622 bus_space_tag_t st = sc->sc_st; 623 bus_space_handle_t sh = sc->sc_sh; 624 uint32_t control; 625 626 control = bus_space_read_8(st, sh, MEC_MAC_CONTROL); 627 control &= ~(MEC_MAC_IPGT | MEC_MAC_IPGR1 | MEC_MAC_IPGR2 | 628 MEC_MAC_FULL_DUPLEX | MEC_MAC_SPEED_SELECT); 629 630 /* must also set IPG here for duplex stuff ... */ 631 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) { 632 control |= MEC_MAC_FULL_DUPLEX; 633 } else { 634 /* set IPG */ 635 control |= MEC_MAC_IPG_DEFAULT; 636 } 637 638 bus_space_write_8(st, sh, MEC_MAC_CONTROL, control); 639 } 640 641 STATIC void 642 mec_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 643 { 644 struct mec_softc *sc = ifp->if_softc; 645 646 if ((ifp->if_flags & IFF_UP) == 0) 647 return; 648 649 mii_pollstat(&sc->sc_mii); 650 ifmr->ifm_status = sc->sc_mii.mii_media_status; 651 ifmr->ifm_active = sc->sc_mii.mii_media_active; 652 } 653 654 STATIC int 655 mec_mediachange(struct ifnet *ifp) 656 { 657 struct mec_softc *sc = ifp->if_softc; 658 659 if ((ifp->if_flags & IFF_UP) == 0) 660 return 0; 661 662 return mii_mediachg(&sc->sc_mii); 663 } 664 665 /* 666 * XXX 667 * maybe this function should be moved to common part 668 * (sgimips/machdep.c or elsewhere) for all on-board network devices. 669 */ 670 static void 671 enaddr_aton(const char *str, uint8_t *eaddr) 672 { 673 int i; 674 char c; 675 676 for (i = 0; i < ETHER_ADDR_LEN; i++) { 677 if (*str == ':') 678 str++; 679 680 c = *str++; 681 if (isdigit(c)) { 682 eaddr[i] = (c - '0'); 683 } else if (isxdigit(c)) { 684 eaddr[i] = (toupper(c) + 10 - 'A'); 685 } 686 c = *str++; 687 if (isdigit(c)) { 688 eaddr[i] = (eaddr[i] << 4) | (c - '0'); 689 } else if (isxdigit(c)) { 690 eaddr[i] = (eaddr[i] << 4) | (toupper(c) + 10 - 'A'); 691 } 692 } 693 } 694 695 STATIC int 696 mec_init(struct ifnet *ifp) 697 { 698 struct mec_softc *sc = ifp->if_softc; 699 bus_space_tag_t st = sc->sc_st; 700 bus_space_handle_t sh = sc->sc_sh; 701 struct mec_rxdesc *rxd; 702 int i; 703 704 /* cancel any pending I/O */ 705 mec_stop(ifp, 0); 706 707 /* reset device */ 708 mec_reset(sc); 709 710 /* setup filter for multicast or promisc mode */ 711 mec_setfilter(sc); 712 713 /* set the TX ring pointer to the base address */ 714 bus_space_write_8(st, sh, MEC_TX_RING_BASE, MEC_CDTXADDR(sc, 0)); 715 716 sc->sc_txpending = 0; 717 sc->sc_txdirty = 0; 718 sc->sc_txlast = MEC_NTXDESC - 1; 719 720 /* put RX buffers into FIFO */ 721 for (i = 0; i < MEC_NRXDESC; i++) { 722 rxd = &sc->sc_rxdesc[i]; 723 rxd->rxd_stat = 0; 724 MEC_RXSTATSYNC(sc, i, BUS_DMASYNC_PREREAD); 725 MEC_RXBUFSYNC(sc, i, ETHER_MAX_LEN, BUS_DMASYNC_PREREAD); 726 bus_space_write_8(st, sh, MEC_MCL_RX_FIFO, MEC_CDRXADDR(sc, i)); 727 } 728 sc->sc_rxptr = 0; 729 730 #if 0 /* XXX no info */ 731 bus_space_write_8(st, sh, MEC_TIMER, 0); 732 #endif 733 734 /* 735 * MEC_DMA_TX_INT_ENABLE will be set later otherwise it causes 736 * spurious interrupts when TX buffers are empty 737 */ 738 bus_space_write_8(st, sh, MEC_DMA_CONTROL, 739 (MEC_RXD_DMAOFFSET << MEC_DMA_RX_DMA_OFFSET_SHIFT) | 740 (MEC_NRXDESC << MEC_DMA_RX_INT_THRESH_SHIFT) | 741 MEC_DMA_TX_DMA_ENABLE | /* MEC_DMA_TX_INT_ENABLE | */ 742 MEC_DMA_RX_DMA_ENABLE | MEC_DMA_RX_INT_ENABLE); 743 744 callout_reset(&sc->sc_tick_ch, hz, mec_tick, sc); 745 746 ifp->if_flags |= IFF_RUNNING; 747 ifp->if_flags &= ~IFF_OACTIVE; 748 mec_start(ifp); 749 750 mii_mediachg(&sc->sc_mii); 751 752 return 0; 753 } 754 755 STATIC void 756 mec_reset(struct mec_softc *sc) 757 { 758 bus_space_tag_t st = sc->sc_st; 759 bus_space_handle_t sh = sc->sc_sh; 760 uint64_t address, control; 761 int i; 762 763 /* reset chip */ 764 bus_space_write_8(st, sh, MEC_MAC_CONTROL, MEC_MAC_CORE_RESET); 765 delay(1000); 766 bus_space_write_8(st, sh, MEC_MAC_CONTROL, 0); 767 delay(1000); 768 769 /* set ethernet address */ 770 address = 0; 771 for (i = 0; i < ETHER_ADDR_LEN; i++) { 772 address = address << 8; 773 address += sc->sc_enaddr[i]; 774 } 775 bus_space_write_8(st, sh, MEC_STATION, address); 776 777 /* Default to 100/half and let autonegotiation work its magic */ 778 control = MEC_MAC_SPEED_SELECT | MEC_MAC_FILTER_MATCHMULTI | 779 MEC_MAC_IPG_DEFAULT; 780 781 bus_space_write_8(st, sh, MEC_MAC_CONTROL, control); 782 bus_space_write_8(st, sh, MEC_DMA_CONTROL, 0); 783 784 DPRINTF(MEC_DEBUG_RESET, ("mec: control now %llx\n", 785 bus_space_read_8(st, sh, MEC_MAC_CONTROL))); 786 } 787 788 STATIC void 789 mec_start(struct ifnet *ifp) 790 { 791 struct mec_softc *sc = ifp->if_softc; 792 struct mbuf *m0, *m; 793 struct mec_txdesc *txd; 794 struct mec_txsoft *txs; 795 bus_dmamap_t dmamap; 796 bus_space_tag_t st = sc->sc_st; 797 bus_space_handle_t sh = sc->sc_sh; 798 uint64_t txdaddr; 799 int error, firsttx, nexttx, opending; 800 int len, bufoff, buflen, unaligned, txdlen; 801 802 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 803 return; 804 805 /* 806 * Remember the previous txpending and the first transmit descriptor. 807 */ 808 opending = sc->sc_txpending; 809 firsttx = MEC_NEXTTX(sc->sc_txlast); 810 811 DPRINTF(MEC_DEBUG_START, 812 ("mec_start: opending = %d, firsttx = %d\n", opending, firsttx)); 813 814 for (;;) { 815 /* Grab a packet off the queue. */ 816 IFQ_POLL(&ifp->if_snd, m0); 817 if (m0 == NULL) 818 break; 819 m = NULL; 820 821 if (sc->sc_txpending == MEC_NTXDESC) { 822 break; 823 } 824 825 /* 826 * Get the next available transmit descriptor. 827 */ 828 nexttx = MEC_NEXTTX(sc->sc_txlast); 829 txd = &sc->sc_txdesc[nexttx]; 830 txs = &sc->sc_txsoft[nexttx]; 831 832 buflen = 0; 833 bufoff = 0; 834 txdaddr = 0; /* XXX gcc */ 835 txdlen = 0; /* XXX gcc */ 836 837 len = m0->m_pkthdr.len; 838 839 DPRINTF(MEC_DEBUG_START, 840 ("mec_start: len = %d, nexttx = %d\n", len, nexttx)); 841 842 if (len < ETHER_PAD_LEN) { 843 /* 844 * I don't know if MEC chip does auto padding, 845 * so if the packet is small enough, 846 * just copy it to the buffer in txdesc. 847 * Maybe this is the simple way. 848 */ 849 DPRINTF(MEC_DEBUG_START, ("mec_start: short packet\n")); 850 851 IFQ_DEQUEUE(&ifp->if_snd, m0); 852 bufoff = MEC_TXD_BUFSTART(ETHER_PAD_LEN); 853 m_copydata(m0, 0, m0->m_pkthdr.len, 854 txd->txd_buf + bufoff); 855 memset(txd->txd_buf + bufoff + len, 0, 856 ETHER_PAD_LEN - len); 857 len = buflen = ETHER_PAD_LEN; 858 859 txs->txs_flags = MEC_TXS_TXDBUF | buflen; 860 } else { 861 /* 862 * If the packet won't fit the buffer in txdesc, 863 * we have to use concatinate pointer to handle it. 864 * While MEC can handle up to three segments to 865 * concatinate, MEC requires that both the second and 866 * third segments have to be 8 byte aligned. 867 * Since it's unlikely for mbuf clusters, we use 868 * only the first concatinate pointer. If the packet 869 * doesn't fit in one DMA segment, allocate new mbuf 870 * and copy the packet to it. 871 * 872 * Besides, if the start address of the first segments 873 * is not 8 byte aligned, such part have to be copied 874 * to the txdesc buffer. (XXX see below comments) 875 */ 876 DPRINTF(MEC_DEBUG_START, ("mec_start: long packet\n")); 877 878 dmamap = txs->txs_dmamap; 879 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 880 BUS_DMA_WRITE | BUS_DMA_NOWAIT) != 0) { 881 DPRINTF(MEC_DEBUG_START, 882 ("mec_start: re-allocating mbuf\n")); 883 MGETHDR(m, M_DONTWAIT, MT_DATA); 884 if (m == NULL) { 885 printf("%s: unable to allocate " 886 "TX mbuf\n", sc->sc_dev.dv_xname); 887 break; 888 } 889 if (len > (MHLEN - MEC_ETHER_ALIGN)) { 890 MCLGET(m, M_DONTWAIT); 891 if ((m->m_flags & M_EXT) == 0) { 892 printf("%s: unable to allocate " 893 "TX cluster\n", 894 sc->sc_dev.dv_xname); 895 m_freem(m); 896 break; 897 } 898 } 899 /* 900 * Each packet has the Ethernet header, so 901 * in many case the header isn't 4-byte aligned 902 * and data after the header is 4-byte aligned. 903 * Thus adding 2-byte offset before copying to 904 * new mbuf avoids unaligned copy and this may 905 * improve some performance. 906 * As noted above, unaligned part has to be 907 * copied to txdesc buffer so this may cause 908 * extra copy ops, but for now MEC always 909 * requires some data in txdesc buffer, 910 * so we always have to copy some data anyway. 911 */ 912 m->m_data += MEC_ETHER_ALIGN; 913 m_copydata(m0, 0, len, mtod(m, void *)); 914 m->m_pkthdr.len = m->m_len = len; 915 error = bus_dmamap_load_mbuf(sc->sc_dmat, 916 dmamap, m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 917 if (error) { 918 printf("%s: unable to load TX buffer, " 919 "error = %d\n", 920 sc->sc_dev.dv_xname, error); 921 break; 922 } 923 } 924 IFQ_DEQUEUE(&ifp->if_snd, m0); 925 if (m != NULL) { 926 m_freem(m0); 927 m0 = m; 928 } 929 930 /* handle unaligned part */ 931 txdaddr = MEC_TXD_ROUNDUP(dmamap->dm_segs[0].ds_addr); 932 txs->txs_flags = MEC_TXS_TXDPTR1; 933 unaligned = 934 dmamap->dm_segs[0].ds_addr & (MEC_TXD_ALIGN - 1); 935 DPRINTF(MEC_DEBUG_START, 936 ("mec_start: ds_addr = 0x%08x, unaligned = %d\n", 937 (u_int)dmamap->dm_segs[0].ds_addr, unaligned)); 938 if (unaligned != 0) { 939 buflen = MEC_TXD_ALIGN - unaligned; 940 bufoff = MEC_TXD_BUFSTART(buflen); 941 DPRINTF(MEC_DEBUG_START, 942 ("mec_start: unaligned, " 943 "buflen = %d, bufoff = %d\n", 944 buflen, bufoff)); 945 memcpy(txd->txd_buf + bufoff, 946 mtod(m0, void *), buflen); 947 txs->txs_flags |= MEC_TXS_TXDBUF | buflen; 948 } 949 #if 1 950 else { 951 /* 952 * XXX needs hardware info XXX 953 * It seems MEC always requires some data 954 * in txd_buf[] even if buffer is 955 * 8-byte aligned otherwise DMA abort error 956 * occurs later... 957 */ 958 buflen = MEC_TXD_ALIGN; 959 bufoff = MEC_TXD_BUFSTART(buflen); 960 memcpy(txd->txd_buf + bufoff, 961 mtod(m0, void *), buflen); 962 DPRINTF(MEC_DEBUG_START, 963 ("mec_start: aligned, " 964 "buflen = %d, bufoff = %d\n", 965 buflen, bufoff)); 966 txs->txs_flags |= MEC_TXS_TXDBUF | buflen; 967 txdaddr += MEC_TXD_ALIGN; 968 } 969 #endif 970 txdlen = len - buflen; 971 DPRINTF(MEC_DEBUG_START, 972 ("mec_start: txdaddr = 0x%08llx, txdlen = %d\n", 973 txdaddr, txdlen)); 974 975 /* 976 * sync the DMA map for TX mbuf 977 * 978 * XXX unaligned part doesn't have to be sync'ed, 979 * but it's harmless... 980 */ 981 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, 982 dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 983 } 984 985 #if NBPFILTER > 0 986 /* 987 * Pass packet to bpf if there is a listener. 988 */ 989 if (ifp->if_bpf) 990 bpf_mtap(ifp->if_bpf, m0); 991 #endif 992 993 /* 994 * setup the transmit descriptor. 995 */ 996 997 /* TXINT bit will be set later on the last packet */ 998 txd->txd_cmd = (len - 1); 999 /* but also set TXINT bit on a half of TXDESC */ 1000 if (sc->sc_txpending == (MEC_NTXDESC / 2)) 1001 txd->txd_cmd |= MEC_TXCMD_TXINT; 1002 1003 if (txs->txs_flags & MEC_TXS_TXDBUF) 1004 txd->txd_cmd |= TXCMD_BUFSTART(MEC_TXDESCSIZE - buflen); 1005 if (txs->txs_flags & MEC_TXS_TXDPTR1) { 1006 txd->txd_cmd |= MEC_TXCMD_PTR1; 1007 txd->txd_ptr[0] = TXPTR_LEN(txdlen - 1) | txdaddr; 1008 /* 1009 * Store a pointer to the packet so we can 1010 * free it later. 1011 */ 1012 txs->txs_mbuf = m0; 1013 } else { 1014 txd->txd_ptr[0] = 0; 1015 /* 1016 * In this case all data are copied to buffer in txdesc, 1017 * we can free TX mbuf here. 1018 */ 1019 m_freem(m0); 1020 } 1021 1022 DPRINTF(MEC_DEBUG_START, 1023 ("mec_start: txd_cmd = 0x%016llx, txd_ptr = 0x%016llx\n", 1024 txd->txd_cmd, txd->txd_ptr[0])); 1025 DPRINTF(MEC_DEBUG_START, 1026 ("mec_start: len = %d (0x%04x), buflen = %d (0x%02x)\n", 1027 len, len, buflen, buflen)); 1028 1029 /* sync TX descriptor */ 1030 MEC_TXDESCSYNC(sc, nexttx, 1031 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1032 1033 /* advance the TX pointer. */ 1034 sc->sc_txpending++; 1035 sc->sc_txlast = nexttx; 1036 } 1037 1038 if (sc->sc_txpending == MEC_NTXDESC) { 1039 /* No more slots; notify upper layer. */ 1040 ifp->if_flags |= IFF_OACTIVE; 1041 } 1042 1043 if (sc->sc_txpending != opending) { 1044 /* 1045 * Cause a TX interrupt to happen on the last packet 1046 * we enqueued. 1047 */ 1048 sc->sc_txdesc[sc->sc_txlast].txd_cmd |= MEC_TXCMD_TXINT; 1049 MEC_TXCMDSYNC(sc, sc->sc_txlast, 1050 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1051 1052 /* start TX */ 1053 bus_space_write_8(st, sh, MEC_TX_RING_PTR, 1054 MEC_NEXTTX(sc->sc_txlast)); 1055 1056 /* 1057 * If the transmitter was idle, 1058 * reset the txdirty pointer and reenable TX interrupt. 1059 */ 1060 if (opending == 0) { 1061 sc->sc_txdirty = firsttx; 1062 bus_space_write_8(st, sh, MEC_TX_ALIAS, 1063 MEC_TX_ALIAS_INT_ENABLE); 1064 } 1065 1066 /* Set a watchdog timer in case the chip flakes out. */ 1067 ifp->if_timer = 5; 1068 } 1069 } 1070 1071 STATIC void 1072 mec_stop(struct ifnet *ifp, int disable) 1073 { 1074 struct mec_softc *sc = ifp->if_softc; 1075 struct mec_txsoft *txs; 1076 int i; 1077 1078 DPRINTF(MEC_DEBUG_STOP, ("mec_stop\n")); 1079 1080 ifp->if_timer = 0; 1081 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1082 1083 callout_stop(&sc->sc_tick_ch); 1084 mii_down(&sc->sc_mii); 1085 1086 /* release any TX buffers */ 1087 for (i = 0; i < MEC_NTXDESC; i++) { 1088 txs = &sc->sc_txsoft[i]; 1089 if ((txs->txs_flags & MEC_TXS_TXDPTR1) != 0) { 1090 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1091 m_freem(txs->txs_mbuf); 1092 txs->txs_mbuf = NULL; 1093 } 1094 } 1095 } 1096 1097 STATIC int 1098 mec_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1099 { 1100 struct mec_softc *sc = ifp->if_softc; 1101 struct ifreq *ifr = (void *)data; 1102 int s, error; 1103 1104 s = splnet(); 1105 1106 switch (cmd) { 1107 case SIOCSIFMEDIA: 1108 case SIOCGIFMEDIA: 1109 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1110 break; 1111 1112 default: 1113 error = ether_ioctl(ifp, cmd, data); 1114 if (error == ENETRESET) { 1115 /* 1116 * Multicast list has changed; set the hardware filter 1117 * accordingly. 1118 */ 1119 if (ifp->if_flags & IFF_RUNNING) 1120 error = mec_init(ifp); 1121 else 1122 error = 0; 1123 } 1124 break; 1125 } 1126 1127 /* Try to get more packets going. */ 1128 mec_start(ifp); 1129 1130 splx(s); 1131 return error; 1132 } 1133 1134 STATIC void 1135 mec_watchdog(struct ifnet *ifp) 1136 { 1137 struct mec_softc *sc = ifp->if_softc; 1138 1139 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1140 ifp->if_oerrors++; 1141 1142 mec_init(ifp); 1143 } 1144 1145 STATIC void 1146 mec_tick(void *arg) 1147 { 1148 struct mec_softc *sc = arg; 1149 int s; 1150 1151 s = splnet(); 1152 mii_tick(&sc->sc_mii); 1153 splx(s); 1154 1155 callout_reset(&sc->sc_tick_ch, hz, mec_tick, sc); 1156 } 1157 1158 STATIC void 1159 mec_setfilter(struct mec_softc *sc) 1160 { 1161 struct ethercom *ec = &sc->sc_ethercom; 1162 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1163 struct ether_multi *enm; 1164 struct ether_multistep step; 1165 bus_space_tag_t st = sc->sc_st; 1166 bus_space_handle_t sh = sc->sc_sh; 1167 uint64_t mchash; 1168 uint32_t control, hash; 1169 int mcnt; 1170 1171 control = bus_space_read_8(st, sh, MEC_MAC_CONTROL); 1172 control &= ~MEC_MAC_FILTER_MASK; 1173 1174 if (ifp->if_flags & IFF_PROMISC) { 1175 control |= MEC_MAC_FILTER_PROMISC; 1176 bus_space_write_8(st, sh, MEC_MULTICAST, 0xffffffffffffffffULL); 1177 bus_space_write_8(st, sh, MEC_MAC_CONTROL, control); 1178 return; 1179 } 1180 1181 mcnt = 0; 1182 mchash = 0; 1183 ETHER_FIRST_MULTI(step, ec, enm); 1184 while (enm != NULL) { 1185 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1186 /* set allmulti for a range of multicast addresses */ 1187 control |= MEC_MAC_FILTER_ALLMULTI; 1188 bus_space_write_8(st, sh, MEC_MULTICAST, 1189 0xffffffffffffffffULL); 1190 bus_space_write_8(st, sh, MEC_MAC_CONTROL, control); 1191 return; 1192 } 1193 1194 #define mec_calchash(addr) (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26) 1195 1196 hash = mec_calchash(enm->enm_addrlo); 1197 mchash |= 1 << hash; 1198 mcnt++; 1199 ETHER_NEXT_MULTI(step, enm); 1200 } 1201 1202 ifp->if_flags &= ~IFF_ALLMULTI; 1203 1204 if (mcnt > 0) 1205 control |= MEC_MAC_FILTER_MATCHMULTI; 1206 1207 bus_space_write_8(st, sh, MEC_MULTICAST, mchash); 1208 bus_space_write_8(st, sh, MEC_MAC_CONTROL, control); 1209 } 1210 1211 STATIC int 1212 mec_intr(void *arg) 1213 { 1214 struct mec_softc *sc = arg; 1215 bus_space_tag_t st = sc->sc_st; 1216 bus_space_handle_t sh = sc->sc_sh; 1217 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1218 uint32_t statreg, statack, dmac; 1219 int handled, sent; 1220 1221 DPRINTF(MEC_DEBUG_INTR, ("mec_intr: called\n")); 1222 1223 handled = sent = 0; 1224 1225 for (;;) { 1226 statreg = bus_space_read_8(st, sh, MEC_INT_STATUS); 1227 1228 DPRINTF(MEC_DEBUG_INTR, 1229 ("mec_intr: INT_STAT = 0x%08x\n", statreg)); 1230 1231 statack = statreg & MEC_INT_STATUS_MASK; 1232 if (statack == 0) 1233 break; 1234 bus_space_write_8(st, sh, MEC_INT_STATUS, statack); 1235 1236 handled = 1; 1237 1238 if (statack & 1239 (MEC_INT_RX_THRESHOLD | 1240 MEC_INT_RX_FIFO_UNDERFLOW)) { 1241 mec_rxintr(sc); 1242 } 1243 1244 dmac = bus_space_read_8(st, sh, MEC_DMA_CONTROL); 1245 DPRINTF(MEC_DEBUG_INTR, 1246 ("mec_intr: DMA_CONT = 0x%08x\n", dmac)); 1247 1248 if (statack & 1249 (MEC_INT_TX_EMPTY | 1250 MEC_INT_TX_PACKET_SENT | 1251 MEC_INT_TX_ABORT)) { 1252 mec_txintr(sc); 1253 sent = 1; 1254 if ((statack & MEC_INT_TX_EMPTY) != 0 && 1255 (dmac & MEC_DMA_TX_INT_ENABLE) != 0) { 1256 /* 1257 * disable TX interrupt to stop 1258 * TX empty interrupt 1259 */ 1260 bus_space_write_8(st, sh, MEC_TX_ALIAS, 0); 1261 DPRINTF(MEC_DEBUG_INTR, 1262 ("mec_intr: disable TX_INT\n")); 1263 } 1264 } 1265 1266 if (statack & 1267 (MEC_INT_TX_LINK_FAIL | 1268 MEC_INT_TX_MEM_ERROR | 1269 MEC_INT_TX_ABORT | 1270 MEC_INT_RX_FIFO_UNDERFLOW | 1271 MEC_INT_RX_DMA_UNDERFLOW)) { 1272 printf("%s: mec_intr: interrupt status = 0x%08x\n", 1273 sc->sc_dev.dv_xname, statreg); 1274 } 1275 } 1276 1277 if (sent) { 1278 /* try to get more packets going */ 1279 mec_start(ifp); 1280 } 1281 1282 #if NRND > 0 1283 if (handled) 1284 rnd_add_uint32(&sc->sc_rnd_source, statreg); 1285 #endif 1286 1287 return handled; 1288 } 1289 1290 STATIC void 1291 mec_rxintr(struct mec_softc *sc) 1292 { 1293 bus_space_tag_t st = sc->sc_st; 1294 bus_space_handle_t sh = sc->sc_sh; 1295 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1296 struct mbuf *m; 1297 struct mec_rxdesc *rxd; 1298 uint64_t rxstat; 1299 u_int len; 1300 int i; 1301 1302 DPRINTF(MEC_DEBUG_RXINTR, ("mec_rxintr: called\n")); 1303 1304 for (i = sc->sc_rxptr;; i = MEC_NEXTRX(i)) { 1305 rxd = &sc->sc_rxdesc[i]; 1306 1307 MEC_RXSTATSYNC(sc, i, BUS_DMASYNC_POSTREAD); 1308 rxstat = rxd->rxd_stat; 1309 1310 DPRINTF(MEC_DEBUG_RXINTR, 1311 ("mec_rxintr: rxstat = 0x%016llx, rxptr = %d\n", 1312 rxstat, i)); 1313 DPRINTF(MEC_DEBUG_RXINTR, ("mec_rxintr: rxfifo = 0x%08x\n", 1314 (u_int)bus_space_read_8(st, sh, MEC_RX_FIFO))); 1315 1316 if ((rxstat & MEC_RXSTAT_RECEIVED) == 0) { 1317 MEC_RXSTATSYNC(sc, i, BUS_DMASYNC_PREREAD); 1318 break; 1319 } 1320 1321 len = rxstat & MEC_RXSTAT_LEN; 1322 1323 if (len < ETHER_MIN_LEN || 1324 len > (MCLBYTES - MEC_ETHER_ALIGN)) { 1325 /* invalid length packet; drop it. */ 1326 DPRINTF(MEC_DEBUG_RXINTR, 1327 ("mec_rxintr: wrong packet\n")); 1328 dropit: 1329 ifp->if_ierrors++; 1330 rxd->rxd_stat = 0; 1331 MEC_RXSTATSYNC(sc, i, BUS_DMASYNC_PREREAD); 1332 bus_space_write_8(st, sh, MEC_MCL_RX_FIFO, 1333 MEC_CDRXADDR(sc, i)); 1334 continue; 1335 } 1336 1337 if (rxstat & 1338 (MEC_RXSTAT_BADPACKET | 1339 MEC_RXSTAT_LONGEVENT | 1340 MEC_RXSTAT_INVALID | 1341 MEC_RXSTAT_CRCERROR | 1342 MEC_RXSTAT_VIOLATION)) { 1343 printf("%s: mec_rxintr: status = 0x%016llx\n", 1344 sc->sc_dev.dv_xname, rxstat); 1345 goto dropit; 1346 } 1347 1348 /* 1349 * The MEC includes the CRC with every packet. Trim 1350 * it off here. 1351 */ 1352 len -= ETHER_CRC_LEN; 1353 1354 /* 1355 * now allocate an mbuf (and possibly a cluster) to hold 1356 * the received packet. 1357 */ 1358 MGETHDR(m, M_DONTWAIT, MT_DATA); 1359 if (m == NULL) { 1360 printf("%s: unable to allocate RX mbuf\n", 1361 sc->sc_dev.dv_xname); 1362 goto dropit; 1363 } 1364 if (len > (MHLEN - MEC_ETHER_ALIGN)) { 1365 MCLGET(m, M_DONTWAIT); 1366 if ((m->m_flags & M_EXT) == 0) { 1367 printf("%s: unable to allocate RX cluster\n", 1368 sc->sc_dev.dv_xname); 1369 m_freem(m); 1370 m = NULL; 1371 goto dropit; 1372 } 1373 } 1374 1375 /* 1376 * Note MEC chip seems to insert 2 byte padding at the top of 1377 * RX buffer, but we copy whole buffer to avoid unaligned copy. 1378 */ 1379 MEC_RXBUFSYNC(sc, i, len, BUS_DMASYNC_POSTREAD); 1380 memcpy(mtod(m, void *), rxd->rxd_buf, MEC_ETHER_ALIGN + len); 1381 MEC_RXBUFSYNC(sc, i, ETHER_MAX_LEN, BUS_DMASYNC_PREREAD); 1382 m->m_data += MEC_ETHER_ALIGN; 1383 1384 /* put RX buffer into FIFO again */ 1385 rxd->rxd_stat = 0; 1386 MEC_RXSTATSYNC(sc, i, BUS_DMASYNC_PREREAD); 1387 bus_space_write_8(st, sh, MEC_MCL_RX_FIFO, MEC_CDRXADDR(sc, i)); 1388 1389 m->m_pkthdr.rcvif = ifp; 1390 m->m_pkthdr.len = m->m_len = len; 1391 1392 ifp->if_ipackets++; 1393 1394 #if NBPFILTER > 0 1395 /* 1396 * Pass this up to any BPF listeners, but only 1397 * pass it up the stack it its for us. 1398 */ 1399 if (ifp->if_bpf) 1400 bpf_mtap(ifp->if_bpf, m); 1401 #endif 1402 1403 /* Pass it on. */ 1404 (*ifp->if_input)(ifp, m); 1405 } 1406 1407 /* update RX pointer */ 1408 sc->sc_rxptr = i; 1409 } 1410 1411 STATIC void 1412 mec_txintr(struct mec_softc *sc) 1413 { 1414 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1415 struct mec_txdesc *txd; 1416 struct mec_txsoft *txs; 1417 bus_dmamap_t dmamap; 1418 uint64_t txstat; 1419 int i; 1420 u_int col; 1421 1422 ifp->if_flags &= ~IFF_OACTIVE; 1423 1424 DPRINTF(MEC_DEBUG_TXINTR, ("mec_txintr: called\n")); 1425 1426 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1427 i = MEC_NEXTTX(i), sc->sc_txpending--) { 1428 txd = &sc->sc_txdesc[i]; 1429 1430 MEC_TXDESCSYNC(sc, i, 1431 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1432 1433 txstat = txd->txd_stat; 1434 DPRINTF(MEC_DEBUG_TXINTR, 1435 ("mec_txintr: dirty = %d, txstat = 0x%016llx\n", 1436 i, txstat)); 1437 if ((txstat & MEC_TXSTAT_SENT) == 0) { 1438 MEC_TXCMDSYNC(sc, i, BUS_DMASYNC_PREREAD); 1439 break; 1440 } 1441 1442 if ((txstat & MEC_TXSTAT_SUCCESS) == 0) { 1443 printf("%s: TX error: txstat = 0x%016llx\n", 1444 sc->sc_dev.dv_xname, txstat); 1445 ifp->if_oerrors++; 1446 continue; 1447 } 1448 1449 txs = &sc->sc_txsoft[i]; 1450 if ((txs->txs_flags & MEC_TXS_TXDPTR1) != 0) { 1451 dmamap = txs->txs_dmamap; 1452 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, 1453 dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1454 bus_dmamap_unload(sc->sc_dmat, dmamap); 1455 m_freem(txs->txs_mbuf); 1456 txs->txs_mbuf = NULL; 1457 } 1458 1459 col = (txstat & MEC_TXSTAT_COLCNT) >> MEC_TXSTAT_COLCNT_SHIFT; 1460 ifp->if_collisions += col; 1461 ifp->if_opackets++; 1462 } 1463 1464 /* update the dirty TX buffer pointer */ 1465 sc->sc_txdirty = i; 1466 DPRINTF(MEC_DEBUG_INTR, 1467 ("mec_txintr: sc_txdirty = %2d, sc_txpending = %2d\n", 1468 sc->sc_txdirty, sc->sc_txpending)); 1469 1470 /* cancel the watchdog timer if there are no pending TX packets */ 1471 if (sc->sc_txpending == 0) 1472 ifp->if_timer = 0; 1473 } 1474 1475 STATIC void 1476 mec_shutdown(void *arg) 1477 { 1478 struct mec_softc *sc = arg; 1479 1480 mec_stop(&sc->sc_ethercom.ec_if, 1); 1481 } 1482
Indexes created Sun Sep 28 16:09:52 GMT 2025