if_mec.c revision 1.31
1 /* $NetBSD: if_mec.c,v 1.31 2008/08/23 15:09:10 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 2004, 2008 Izumi Tsutsui. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /* 28 * Copyright (c) 2003 Christopher SEKIYA 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 1. Redistributions of source code must retain the above copyright 35 * notice, this list of conditions and the following disclaimer. 36 * 2. Redistributions in binary form must reproduce the above copyright 37 * notice, this list of conditions and the following disclaimer in the 38 * documentation and/or other materials provided with the distribution. 39 * 3. All advertising materials mentioning features or use of this software 40 * must display the following acknowledgement: 41 * This product includes software developed for the 42 * NetBSD Project. See http://www.NetBSD.org/ for 43 * information about NetBSD. 44 * 4. The name of the author may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 /* 60 * MACE MAC-110 Ethernet driver 61 */ 62 63 #include <sys/cdefs.h> 64 __KERNEL_RCSID(0, "$NetBSD: if_mec.c,v 1.31 2008/08/23 15:09:10 tsutsui Exp $"); 65 66 #include "opt_ddb.h" 67 #include "bpfilter.h" 68 #include "rnd.h" 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/device.h> 73 #include <sys/callout.h> 74 #include <sys/mbuf.h> 75 #include <sys/malloc.h> 76 #include <sys/kernel.h> 77 #include <sys/socket.h> 78 #include <sys/ioctl.h> 79 #include <sys/errno.h> 80 81 #if NRND > 0 82 #include <sys/rnd.h> 83 #endif 84 85 #include <net/if.h> 86 #include <net/if_dl.h> 87 #include <net/if_media.h> 88 #include <net/if_ether.h> 89 90 #if NBPFILTER > 0 91 #include <net/bpf.h> 92 #endif 93 94 #include <machine/bus.h> 95 #include <machine/intr.h> 96 #include <machine/machtype.h> 97 98 #include <dev/mii/mii.h> 99 #include <dev/mii/miivar.h> 100 101 #include <sgimips/mace/macevar.h> 102 #include <sgimips/mace/if_mecreg.h> 103 104 #include <dev/arcbios/arcbios.h> 105 #include <dev/arcbios/arcbiosvar.h> 106 107 /* #define MEC_DEBUG */ 108 109 #ifdef MEC_DEBUG 110 #define MEC_DEBUG_RESET 0x01 111 #define MEC_DEBUG_START 0x02 112 #define MEC_DEBUG_STOP 0x04 113 #define MEC_DEBUG_INTR 0x08 114 #define MEC_DEBUG_RXINTR 0x10 115 #define MEC_DEBUG_TXINTR 0x20 116 #define MEC_DEBUG_TXSEGS 0x40 117 uint32_t mec_debug = 0; 118 #define DPRINTF(x, y) if (mec_debug & (x)) printf y 119 #else 120 #define DPRINTF(x, y) /* nothing */ 121 #endif 122 123 /* #define MEC_EVENT_COUNTERS */ 124 125 #ifdef MEC_EVENT_COUNTERS 126 #define MEC_EVCNT_INCR(ev) (ev)->ev_count++ 127 #else 128 #define MEC_EVCNT_INCR(ev) do {} while (/* CONSTCOND */ 0) 129 #endif 130 131 /* 132 * Transmit descriptor list size 133 */ 134 #define MEC_NTXDESC 64 135 #define MEC_NTXDESC_MASK (MEC_NTXDESC - 1) 136 #define MEC_NEXTTX(x) (((x) + 1) & MEC_NTXDESC_MASK) 137 #define MEC_NTXDESC_RSVD 4 138 #define MEC_NTXDESC_INTR 8 139 140 /* 141 * software state for TX 142 */ 143 struct mec_txsoft { 144 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 145 bus_dmamap_t txs_dmamap; /* our DMA map */ 146 uint32_t txs_flags; 147 #define MEC_TXS_BUFLEN_MASK 0x0000007f /* data len in txd_buf */ 148 #define MEC_TXS_TXDPTR 0x00000080 /* concat txd_ptr is used */ 149 }; 150 151 /* 152 * Transmit buffer descriptor 153 */ 154 #define MEC_TXDESCSIZE 128 155 #define MEC_NTXPTR 3 156 #define MEC_TXD_BUFOFFSET sizeof(uint64_t) 157 #define MEC_TXD_BUFOFFSET1 \ 158 (sizeof(uint64_t) + sizeof(uint64_t) * MEC_NTXPTR) 159 #define MEC_TXD_BUFSIZE (MEC_TXDESCSIZE - MEC_TXD_BUFOFFSET) 160 #define MEC_TXD_BUFSIZE1 (MEC_TXDESCSIZE - MEC_TXD_BUFOFFSET1) 161 #define MEC_TXD_BUFSTART(len) (MEC_TXD_BUFSIZE - (len)) 162 #define MEC_TXD_ALIGN 8 163 #define MEC_TXD_ALIGNMASK (MEC_TXD_ALIGN - 1) 164 #define MEC_TXD_ROUNDUP(addr) \ 165 (((addr) + MEC_TXD_ALIGNMASK) & ~(uint64_t)MEC_TXD_ALIGNMASK) 166 #define MEC_NTXSEG 16 167 168 struct mec_txdesc { 169 volatile uint64_t txd_cmd; 170 #define MEC_TXCMD_DATALEN 0x000000000000ffff /* data length */ 171 #define MEC_TXCMD_BUFSTART 0x00000000007f0000 /* start byte offset */ 172 #define TXCMD_BUFSTART(x) ((x) << 16) 173 #define MEC_TXCMD_TERMDMA 0x0000000000800000 /* stop DMA on abort */ 174 #define MEC_TXCMD_TXINT 0x0000000001000000 /* INT after TX done */ 175 #define MEC_TXCMD_PTR1 0x0000000002000000 /* valid 1st txd_ptr */ 176 #define MEC_TXCMD_PTR2 0x0000000004000000 /* valid 2nd txd_ptr */ 177 #define MEC_TXCMD_PTR3 0x0000000008000000 /* valid 3rd txd_ptr */ 178 #define MEC_TXCMD_UNUSED 0xfffffffff0000000ULL /* should be zero */ 179 180 #define txd_stat txd_cmd 181 #define MEC_TXSTAT_LEN 0x000000000000ffff /* TX length */ 182 #define MEC_TXSTAT_COLCNT 0x00000000000f0000 /* collision count */ 183 #define MEC_TXSTAT_COLCNT_SHIFT 16 184 #define MEC_TXSTAT_LATE_COL 0x0000000000100000 /* late collision */ 185 #define MEC_TXSTAT_CRCERROR 0x0000000000200000 /* */ 186 #define MEC_TXSTAT_DEFERRED 0x0000000000400000 /* */ 187 #define MEC_TXSTAT_SUCCESS 0x0000000000800000 /* TX complete */ 188 #define MEC_TXSTAT_TOOBIG 0x0000000001000000 /* */ 189 #define MEC_TXSTAT_UNDERRUN 0x0000000002000000 /* */ 190 #define MEC_TXSTAT_COLLISIONS 0x0000000004000000 /* */ 191 #define MEC_TXSTAT_EXDEFERRAL 0x0000000008000000 /* */ 192 #define MEC_TXSTAT_COLLIDED 0x0000000010000000 /* */ 193 #define MEC_TXSTAT_UNUSED 0x7fffffffe0000000ULL /* should be zero */ 194 #define MEC_TXSTAT_SENT 0x8000000000000000ULL /* packet sent */ 195 196 union { 197 uint64_t txptr[MEC_NTXPTR]; 198 #define MEC_TXPTR_UNUSED2 0x0000000000000007 /* should be zero */ 199 #define MEC_TXPTR_DMAADDR 0x00000000fffffff8 /* TX DMA address */ 200 #define MEC_TXPTR_LEN 0x0000ffff00000000ULL /* buffer length */ 201 #define TXPTR_LEN(x) ((uint64_t)(x) << 32) 202 #define MEC_TXPTR_UNUSED1 0xffff000000000000ULL /* should be zero */ 203 204 uint8_t txbuf[MEC_TXD_BUFSIZE]; 205 } txd_data; 206 #define txd_ptr txd_data.txptr 207 #define txd_buf txd_data.txbuf 208 }; 209 210 /* 211 * Receive buffer size 212 */ 213 #define MEC_NRXDESC 16 214 #define MEC_NRXDESC_MASK (MEC_NRXDESC - 1) 215 #define MEC_NEXTRX(x) (((x) + 1) & MEC_NRXDESC_MASK) 216 217 /* 218 * Receive buffer description 219 */ 220 #define MEC_RXDESCSIZE 4096 /* umm, should be 4kbyte aligned */ 221 #define MEC_RXD_NRXPAD 3 222 #define MEC_RXD_DMAOFFSET (1 + MEC_RXD_NRXPAD) 223 #define MEC_RXD_BUFOFFSET (MEC_RXD_DMAOFFSET * sizeof(uint64_t)) 224 #define MEC_RXD_BUFSIZE (MEC_RXDESCSIZE - MEC_RXD_BUFOFFSET) 225 226 struct mec_rxdesc { 227 volatile uint64_t rxd_stat; 228 #define MEC_RXSTAT_LEN 0x000000000000ffff /* data length */ 229 #define MEC_RXSTAT_VIOLATION 0x0000000000010000 /* code violation (?) */ 230 #define MEC_RXSTAT_UNUSED2 0x0000000000020000 /* unknown (?) */ 231 #define MEC_RXSTAT_CRCERROR 0x0000000000040000 /* CRC error */ 232 #define MEC_RXSTAT_MULTICAST 0x0000000000080000 /* multicast packet */ 233 #define MEC_RXSTAT_BROADCAST 0x0000000000100000 /* broadcast packet */ 234 #define MEC_RXSTAT_INVALID 0x0000000000200000 /* invalid preamble */ 235 #define MEC_RXSTAT_LONGEVENT 0x0000000000400000 /* long packet */ 236 #define MEC_RXSTAT_BADPACKET 0x0000000000800000 /* bad packet */ 237 #define MEC_RXSTAT_CAREVENT 0x0000000001000000 /* carrier event */ 238 #define MEC_RXSTAT_MATCHMCAST 0x0000000002000000 /* match multicast */ 239 #define MEC_RXSTAT_MATCHMAC 0x0000000004000000 /* match MAC */ 240 #define MEC_RXSTAT_SEQNUM 0x00000000f8000000 /* sequence number */ 241 #define MEC_RXSTAT_CKSUM 0x0000ffff00000000ULL /* IP checksum */ 242 #define MEC_RXSTAT_UNUSED1 0x7fff000000000000ULL /* should be zero */ 243 #define MEC_RXSTAT_RECEIVED 0x8000000000000000ULL /* set to 1 on RX */ 244 uint64_t rxd_pad1[MEC_RXD_NRXPAD]; 245 uint8_t rxd_buf[MEC_RXD_BUFSIZE]; 246 }; 247 248 /* 249 * control structures for DMA ops 250 */ 251 struct mec_control_data { 252 /* 253 * TX descriptors and buffers 254 */ 255 struct mec_txdesc mcd_txdesc[MEC_NTXDESC]; 256 257 /* 258 * RX descriptors and buffers 259 */ 260 struct mec_rxdesc mcd_rxdesc[MEC_NRXDESC]; 261 }; 262 263 /* 264 * It _seems_ there are some restrictions on descriptor address: 265 * 266 * - Base address of txdescs should be 8kbyte aligned 267 * - Each txdesc should be 128byte aligned 268 * - Each rxdesc should be 4kbyte aligned 269 * 270 * So we should specify 8k align to allocalte txdescs. 271 * In this case, sizeof(struct mec_txdesc) * MEC_NTXDESC is 8192 272 * so rxdescs are also allocated at 4kbyte aligned. 273 */ 274 #define MEC_CONTROL_DATA_ALIGN (8 * 1024) 275 276 #define MEC_CDOFF(x) offsetof(struct mec_control_data, x) 277 #define MEC_CDTXOFF(x) MEC_CDOFF(mcd_txdesc[(x)]) 278 #define MEC_CDRXOFF(x) MEC_CDOFF(mcd_rxdesc[(x)]) 279 280 /* 281 * software state per device 282 */ 283 struct mec_softc { 284 device_t sc_dev; /* generic device structures */ 285 286 bus_space_tag_t sc_st; /* bus_space tag */ 287 bus_space_handle_t sc_sh; /* bus_space handle */ 288 bus_dma_tag_t sc_dmat; /* bus_dma tag */ 289 void *sc_sdhook; /* shutdown hook */ 290 291 struct ethercom sc_ethercom; /* Ethernet common part */ 292 293 struct mii_data sc_mii; /* MII/media information */ 294 int sc_phyaddr; /* MII address */ 295 struct callout sc_tick_ch; /* tick callout */ 296 297 uint8_t sc_enaddr[ETHER_ADDR_LEN]; /* MAC address */ 298 299 bus_dmamap_t sc_cddmamap; /* bus_dma map for control data */ 300 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 301 302 /* pointer to allocated control data */ 303 struct mec_control_data *sc_control_data; 304 #define sc_txdesc sc_control_data->mcd_txdesc 305 #define sc_rxdesc sc_control_data->mcd_rxdesc 306 307 /* software state for TX descs */ 308 struct mec_txsoft sc_txsoft[MEC_NTXDESC]; 309 310 int sc_txpending; /* number of TX requests pending */ 311 int sc_txdirty; /* first dirty TX descriptor */ 312 int sc_txlast; /* last used TX descriptor */ 313 314 int sc_rxptr; /* next ready RX buffer */ 315 316 #if NRND > 0 317 rndsource_element_t sc_rnd_source; /* random source */ 318 #endif 319 #ifdef MEC_EVENT_COUNTERS 320 struct evcnt sc_ev_txpkts; /* TX packets queued total */ 321 struct evcnt sc_ev_txdpad; /* TX packets padded in txdesc buf */ 322 struct evcnt sc_ev_txdbuf; /* TX packets copied to txdesc buf */ 323 struct evcnt sc_ev_txptr1; /* TX packets using concat ptr1 */ 324 struct evcnt sc_ev_txptr1a; /* TX packets w/ptr1 ~160bytes */ 325 struct evcnt sc_ev_txptr1b; /* TX packets w/ptr1 ~256bytes */ 326 struct evcnt sc_ev_txptr1c; /* TX packets w/ptr1 ~512bytes */ 327 struct evcnt sc_ev_txptr1d; /* TX packets w/ptr1 ~1024bytes */ 328 struct evcnt sc_ev_txptr1e; /* TX packets w/ptr1 >1024bytes */ 329 struct evcnt sc_ev_txptr2; /* TX packets using concat ptr1,2 */ 330 struct evcnt sc_ev_txptr2a; /* TX packets w/ptr2 ~160bytes */ 331 struct evcnt sc_ev_txptr2b; /* TX packets w/ptr2 ~256bytes */ 332 struct evcnt sc_ev_txptr2c; /* TX packets w/ptr2 ~512bytes */ 333 struct evcnt sc_ev_txptr2d; /* TX packets w/ptr2 ~1024bytes */ 334 struct evcnt sc_ev_txptr2e; /* TX packets w/ptr2 >1024bytes */ 335 struct evcnt sc_ev_txptr3; /* TX packets using concat ptr1,2,3 */ 336 struct evcnt sc_ev_txptr3a; /* TX packets w/ptr3 ~160bytes */ 337 struct evcnt sc_ev_txptr3b; /* TX packets w/ptr3 ~256bytes */ 338 struct evcnt sc_ev_txptr3c; /* TX packets w/ptr3 ~512bytes */ 339 struct evcnt sc_ev_txptr3d; /* TX packets w/ptr3 ~1024bytes */ 340 struct evcnt sc_ev_txptr3e; /* TX packets w/ptr3 >1024bytes */ 341 struct evcnt sc_ev_txmbuf; /* TX packets copied to new mbufs */ 342 struct evcnt sc_ev_txmbufa; /* TX packets w/mbuf ~160bytes */ 343 struct evcnt sc_ev_txmbufb; /* TX packets w/mbuf ~256bytes */ 344 struct evcnt sc_ev_txmbufc; /* TX packets w/mbuf ~512bytes */ 345 struct evcnt sc_ev_txmbufd; /* TX packets w/mbuf ~1024bytes */ 346 struct evcnt sc_ev_txmbufe; /* TX packets w/mbuf >1024bytes */ 347 struct evcnt sc_ev_txptrs; /* TX packets using ptrs total */ 348 struct evcnt sc_ev_txptrc0; /* TX packets w/ptrs no hdr chain */ 349 struct evcnt sc_ev_txptrc1; /* TX packets w/ptrs 1 hdr chain */ 350 struct evcnt sc_ev_txptrc2; /* TX packets w/ptrs 2 hdr chains */ 351 struct evcnt sc_ev_txptrc3; /* TX packets w/ptrs 3 hdr chains */ 352 struct evcnt sc_ev_txptrc4; /* TX packets w/ptrs 4 hdr chains */ 353 struct evcnt sc_ev_txptrc5; /* TX packets w/ptrs 5 hdr chains */ 354 struct evcnt sc_ev_txptrc6; /* TX packets w/ptrs >5 hdr chains */ 355 struct evcnt sc_ev_txptrh0; /* TX packets w/ptrs ~8bytes hdr */ 356 struct evcnt sc_ev_txptrh1; /* TX packets w/ptrs ~16bytes hdr */ 357 struct evcnt sc_ev_txptrh2; /* TX packets w/ptrs ~32bytes hdr */ 358 struct evcnt sc_ev_txptrh3; /* TX packets w/ptrs ~64bytes hdr */ 359 struct evcnt sc_ev_txptrh4; /* TX packets w/ptrs ~80bytes hdr */ 360 struct evcnt sc_ev_txptrh5; /* TX packets w/ptrs ~96bytes hdr */ 361 struct evcnt sc_ev_txdstall; /* TX stalled due to no txdesc */ 362 struct evcnt sc_ev_txempty; /* TX empty interrupts */ 363 struct evcnt sc_ev_txsent; /* TX sent interrupts */ 364 #endif 365 }; 366 367 #define MEC_CDTXADDR(sc, x) ((sc)->sc_cddma + MEC_CDTXOFF(x)) 368 #define MEC_CDRXADDR(sc, x) ((sc)->sc_cddma + MEC_CDRXOFF(x)) 369 370 #define MEC_TXDESCSYNC(sc, x, ops) \ 371 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 372 MEC_CDTXOFF(x), MEC_TXDESCSIZE, (ops)) 373 #define MEC_TXCMDSYNC(sc, x, ops) \ 374 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 375 MEC_CDTXOFF(x), sizeof(uint64_t), (ops)) 376 377 #define MEC_RXSTATSYNC(sc, x, ops) \ 378 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 379 MEC_CDRXOFF(x), sizeof(uint64_t), (ops)) 380 #define MEC_RXBUFSYNC(sc, x, len, ops) \ 381 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 382 MEC_CDRXOFF(x) + MEC_RXD_BUFOFFSET, \ 383 MEC_ETHER_ALIGN + (len), (ops)) 384 385 /* XXX these values should be moved to <net/if_ether.h> ? */ 386 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 387 #define MEC_ETHER_ALIGN 2 388 389 static int mec_match(device_t, cfdata_t, void *); 390 static void mec_attach(device_t, device_t, void *); 391 392 static int mec_mii_readreg(device_t, int, int); 393 static void mec_mii_writereg(device_t, int, int, int); 394 static int mec_mii_wait(struct mec_softc *); 395 static void mec_statchg(device_t); 396 397 static void enaddr_aton(const char *, uint8_t *); 398 399 static int mec_init(struct ifnet * ifp); 400 static void mec_start(struct ifnet *); 401 static void mec_watchdog(struct ifnet *); 402 static void mec_tick(void *); 403 static int mec_ioctl(struct ifnet *, u_long, void *); 404 static void mec_reset(struct mec_softc *); 405 static void mec_setfilter(struct mec_softc *); 406 static int mec_intr(void *arg); 407 static void mec_stop(struct ifnet *, int); 408 static void mec_rxintr(struct mec_softc *); 409 static void mec_txintr(struct mec_softc *, uint32_t); 410 static void mec_shutdown(void *); 411 412 CFATTACH_DECL_NEW(mec, sizeof(struct mec_softc), 413 mec_match, mec_attach, NULL, NULL); 414 415 static int mec_matched = 0; 416 417 static int 418 mec_match(device_t parent, cfdata_t cf, void *aux) 419 { 420 421 /* allow only one device */ 422 if (mec_matched) 423 return 0; 424 425 mec_matched = 1; 426 return 1; 427 } 428 429 static void 430 mec_attach(device_t parent, device_t self, void *aux) 431 { 432 struct mec_softc *sc = device_private(self); 433 struct mace_attach_args *maa = aux; 434 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 435 uint64_t address, command; 436 const char *macaddr; 437 struct mii_softc *child; 438 bus_dma_segment_t seg; 439 int i, err, rseg; 440 bool mac_is_fake; 441 442 sc->sc_dev = self; 443 sc->sc_st = maa->maa_st; 444 if (bus_space_subregion(sc->sc_st, maa->maa_sh, 445 maa->maa_offset, 0, &sc->sc_sh) != 0) { 446 aprint_error(": can't map i/o space\n"); 447 return; 448 } 449 450 /* set up DMA structures */ 451 sc->sc_dmat = maa->maa_dmat; 452 453 /* 454 * Allocate the control data structures, and create and load the 455 * DMA map for it. 456 */ 457 if ((err = bus_dmamem_alloc(sc->sc_dmat, 458 sizeof(struct mec_control_data), MEC_CONTROL_DATA_ALIGN, 0, 459 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 460 aprint_error(": unable to allocate control data, error = %d\n", 461 err); 462 goto fail_0; 463 } 464 /* 465 * XXX needs re-think... 466 * control data structures contain whole RX data buffer, so 467 * BUS_DMA_COHERENT (which disables cache) may cause some performance 468 * issue on copying data from the RX buffer to mbuf on normal memory, 469 * though we have to make sure all bus_dmamap_sync(9) ops are called 470 * properly in that case. 471 */ 472 if ((err = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 473 sizeof(struct mec_control_data), 474 (void **)&sc->sc_control_data, /*BUS_DMA_COHERENT*/ 0)) != 0) { 475 aprint_error(": unable to map control data, error = %d\n", err); 476 goto fail_1; 477 } 478 memset(sc->sc_control_data, 0, sizeof(struct mec_control_data)); 479 480 if ((err = bus_dmamap_create(sc->sc_dmat, 481 sizeof(struct mec_control_data), 1, 482 sizeof(struct mec_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 483 aprint_error(": unable to create control data DMA map," 484 " error = %d\n", err); 485 goto fail_2; 486 } 487 if ((err = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 488 sc->sc_control_data, sizeof(struct mec_control_data), NULL, 489 BUS_DMA_NOWAIT)) != 0) { 490 aprint_error(": unable to load control data DMA map," 491 " error = %d\n", err); 492 goto fail_3; 493 } 494 495 /* create TX buffer DMA maps */ 496 for (i = 0; i < MEC_NTXDESC; i++) { 497 if ((err = bus_dmamap_create(sc->sc_dmat, 498 MCLBYTES, MEC_NTXSEG, MCLBYTES, PAGE_SIZE, 0, 499 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 500 aprint_error(": unable to create tx DMA map %d," 501 " error = %d\n", i, err); 502 goto fail_4; 503 } 504 } 505 506 callout_init(&sc->sc_tick_ch, 0); 507 508 /* get Ethernet address from ARCBIOS */ 509 if ((macaddr = ARCBIOS->GetEnvironmentVariable("eaddr")) == NULL) { 510 aprint_error(": unable to get MAC address!\n"); 511 goto fail_4; 512 } 513 /* 514 * On some machines the DS2502 chip storing the serial number/ 515 * mac address is on the pci riser board - if this board is 516 * missing, ARCBIOS will not know a good ethernet address (but 517 * otherwise the machine will work fine). 518 */ 519 mac_is_fake = false; 520 if (strcmp(macaddr, "ff:ff:ff:ff:ff:ff") == 0) { 521 uint32_t ui = 0; 522 const char * netaddr = 523 ARCBIOS->GetEnvironmentVariable("netaddr"); 524 525 /* 526 * Create a MAC address by abusing the "netaddr" env var 527 */ 528 sc->sc_enaddr[0] = 0xf2; 529 sc->sc_enaddr[1] = 0x0b; 530 sc->sc_enaddr[2] = 0xa4; 531 if (netaddr) { 532 mac_is_fake = true; 533 while (*netaddr) { 534 int v = 0; 535 while (*netaddr && *netaddr != '.') { 536 if (*netaddr >= '0' && *netaddr <= '9') 537 v = v*10 + (*netaddr - '0'); 538 netaddr++; 539 } 540 ui <<= 8; 541 ui |= v; 542 if (*netaddr == '.') 543 netaddr++; 544 } 545 } 546 memcpy(sc->sc_enaddr+3, ((uint8_t *)&ui)+1, 3); 547 } 548 if (!mac_is_fake) 549 enaddr_aton(macaddr, sc->sc_enaddr); 550 551 /* set the Ethernet address */ 552 address = 0; 553 for (i = 0; i < ETHER_ADDR_LEN; i++) { 554 address = address << 8; 555 address |= sc->sc_enaddr[i]; 556 } 557 bus_space_write_8(sc->sc_st, sc->sc_sh, MEC_STATION, address); 558 559 /* reset device */ 560 mec_reset(sc); 561 562 command = bus_space_read_8(sc->sc_st, sc->sc_sh, MEC_MAC_CONTROL); 563 564 aprint_normal(": MAC-110 Ethernet, rev %u\n", 565 (u_int)((command & MEC_MAC_REVISION) >> MEC_MAC_REVISION_SHIFT)); 566 567 if (mac_is_fake) 568 aprint_normal_dev(self, 569 "could not get ethernet address from firmware" 570 " - generated one from the \"netaddr\" environment" 571 " variable\n"); 572 aprint_normal_dev(self, "Ethernet address %s\n", 573 ether_sprintf(sc->sc_enaddr)); 574 575 /* Done, now attach everything */ 576 577 sc->sc_mii.mii_ifp = ifp; 578 sc->sc_mii.mii_readreg = mec_mii_readreg; 579 sc->sc_mii.mii_writereg = mec_mii_writereg; 580 sc->sc_mii.mii_statchg = mec_statchg; 581 582 /* Set up PHY properties */ 583 sc->sc_ethercom.ec_mii = &sc->sc_mii; 584 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 585 ether_mediastatus); 586 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 587 MII_OFFSET_ANY, 0); 588 589 child = LIST_FIRST(&sc->sc_mii.mii_phys); 590 if (child == NULL) { 591 /* No PHY attached */ 592 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL, 593 0, NULL); 594 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL); 595 } else { 596 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 597 sc->sc_phyaddr = child->mii_phy; 598 } 599 600 strcpy(ifp->if_xname, device_xname(self)); 601 ifp->if_softc = sc; 602 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 603 ifp->if_ioctl = mec_ioctl; 604 ifp->if_start = mec_start; 605 ifp->if_watchdog = mec_watchdog; 606 ifp->if_init = mec_init; 607 ifp->if_stop = mec_stop; 608 ifp->if_mtu = ETHERMTU; 609 IFQ_SET_READY(&ifp->if_snd); 610 611 if_attach(ifp); 612 ether_ifattach(ifp, sc->sc_enaddr); 613 614 /* establish interrupt */ 615 cpu_intr_establish(maa->maa_intr, maa->maa_intrmask, mec_intr, sc); 616 617 #if NRND > 0 618 rnd_attach_source(&sc->sc_rnd_source, device_xname(self), 619 RND_TYPE_NET, 0); 620 #endif 621 622 #ifdef MEC_EVENT_COUNTERS 623 evcnt_attach_dynamic(&sc->sc_ev_txpkts , EVCNT_TYPE_MISC, 624 NULL, device_xname(self), "TX pkts queued total"); 625 evcnt_attach_dynamic(&sc->sc_ev_txdpad , EVCNT_TYPE_MISC, 626 NULL, device_xname(self), "TX pkts padded in txdesc buf"); 627 evcnt_attach_dynamic(&sc->sc_ev_txdbuf , EVCNT_TYPE_MISC, 628 NULL, device_xname(self), "TX pkts copied to txdesc buf"); 629 evcnt_attach_dynamic(&sc->sc_ev_txptr1 , EVCNT_TYPE_MISC, 630 NULL, device_xname(self), "TX pkts using concat ptr1"); 631 evcnt_attach_dynamic(&sc->sc_ev_txptr1a , EVCNT_TYPE_MISC, 632 NULL, device_xname(self), "TX pkts w/ptr1 ~160bytes"); 633 evcnt_attach_dynamic(&sc->sc_ev_txptr1b , EVCNT_TYPE_MISC, 634 NULL, device_xname(self), "TX pkts w/ptr1 ~256bytes"); 635 evcnt_attach_dynamic(&sc->sc_ev_txptr1c , EVCNT_TYPE_MISC, 636 NULL, device_xname(self), "TX pkts w/ptr1 ~512bytes"); 637 evcnt_attach_dynamic(&sc->sc_ev_txptr1d , EVCNT_TYPE_MISC, 638 NULL, device_xname(self), "TX pkts w/ptr1 ~1024bytes"); 639 evcnt_attach_dynamic(&sc->sc_ev_txptr1e , EVCNT_TYPE_MISC, 640 NULL, device_xname(self), "TX pkts w/ptr1 >1024bytes"); 641 evcnt_attach_dynamic(&sc->sc_ev_txptr2 , EVCNT_TYPE_MISC, 642 NULL, device_xname(self), "TX pkts using concat ptr1,2"); 643 evcnt_attach_dynamic(&sc->sc_ev_txptr2a , EVCNT_TYPE_MISC, 644 NULL, device_xname(self), "TX pkts w/ptr2 ~160bytes"); 645 evcnt_attach_dynamic(&sc->sc_ev_txptr2b , EVCNT_TYPE_MISC, 646 NULL, device_xname(self), "TX pkts w/ptr2 ~256bytes"); 647 evcnt_attach_dynamic(&sc->sc_ev_txptr2c , EVCNT_TYPE_MISC, 648 NULL, device_xname(self), "TX pkts w/ptr2 ~512bytes"); 649 evcnt_attach_dynamic(&sc->sc_ev_txptr2d , EVCNT_TYPE_MISC, 650 NULL, device_xname(self), "TX pkts w/ptr2 ~1024bytes"); 651 evcnt_attach_dynamic(&sc->sc_ev_txptr2e , EVCNT_TYPE_MISC, 652 NULL, device_xname(self), "TX pkts w/ptr2 >1024bytes"); 653 evcnt_attach_dynamic(&sc->sc_ev_txptr3 , EVCNT_TYPE_MISC, 654 NULL, device_xname(self), "TX pkts using concat ptr1,2,3"); 655 evcnt_attach_dynamic(&sc->sc_ev_txptr3a , EVCNT_TYPE_MISC, 656 NULL, device_xname(self), "TX pkts w/ptr3 ~160bytes"); 657 evcnt_attach_dynamic(&sc->sc_ev_txptr3b , EVCNT_TYPE_MISC, 658 NULL, device_xname(self), "TX pkts w/ptr3 ~256bytes"); 659 evcnt_attach_dynamic(&sc->sc_ev_txptr3c , EVCNT_TYPE_MISC, 660 NULL, device_xname(self), "TX pkts w/ptr3 ~512bytes"); 661 evcnt_attach_dynamic(&sc->sc_ev_txptr3d , EVCNT_TYPE_MISC, 662 NULL, device_xname(self), "TX pkts w/ptr3 ~1024bytes"); 663 evcnt_attach_dynamic(&sc->sc_ev_txptr3e , EVCNT_TYPE_MISC, 664 NULL, device_xname(self), "TX pkts w/ptr3 >1024bytes"); 665 evcnt_attach_dynamic(&sc->sc_ev_txmbuf , EVCNT_TYPE_MISC, 666 NULL, device_xname(self), "TX pkts copied to new mbufs"); 667 evcnt_attach_dynamic(&sc->sc_ev_txmbufa , EVCNT_TYPE_MISC, 668 NULL, device_xname(self), "TX pkts w/mbuf ~160bytes"); 669 evcnt_attach_dynamic(&sc->sc_ev_txmbufb , EVCNT_TYPE_MISC, 670 NULL, device_xname(self), "TX pkts w/mbuf ~256bytes"); 671 evcnt_attach_dynamic(&sc->sc_ev_txmbufc , EVCNT_TYPE_MISC, 672 NULL, device_xname(self), "TX pkts w/mbuf ~512bytes"); 673 evcnt_attach_dynamic(&sc->sc_ev_txmbufd , EVCNT_TYPE_MISC, 674 NULL, device_xname(self), "TX pkts w/mbuf ~1024bytes"); 675 evcnt_attach_dynamic(&sc->sc_ev_txmbufe , EVCNT_TYPE_MISC, 676 NULL, device_xname(self), "TX pkts w/mbuf >1024bytes"); 677 evcnt_attach_dynamic(&sc->sc_ev_txptrs , EVCNT_TYPE_MISC, 678 NULL, device_xname(self), "TX pkts using ptrs total"); 679 evcnt_attach_dynamic(&sc->sc_ev_txptrc0 , EVCNT_TYPE_MISC, 680 NULL, device_xname(self), "TX pkts w/ptrs no hdr chain"); 681 evcnt_attach_dynamic(&sc->sc_ev_txptrc1 , EVCNT_TYPE_MISC, 682 NULL, device_xname(self), "TX pkts w/ptrs 1 hdr chain"); 683 evcnt_attach_dynamic(&sc->sc_ev_txptrc2 , EVCNT_TYPE_MISC, 684 NULL, device_xname(self), "TX pkts w/ptrs 2 hdr chains"); 685 evcnt_attach_dynamic(&sc->sc_ev_txptrc3 , EVCNT_TYPE_MISC, 686 NULL, device_xname(self), "TX pkts w/ptrs 3 hdr chains"); 687 evcnt_attach_dynamic(&sc->sc_ev_txptrc4 , EVCNT_TYPE_MISC, 688 NULL, device_xname(self), "TX pkts w/ptrs 4 hdr chains"); 689 evcnt_attach_dynamic(&sc->sc_ev_txptrc5 , EVCNT_TYPE_MISC, 690 NULL, device_xname(self), "TX pkts w/ptrs 5 hdr chains"); 691 evcnt_attach_dynamic(&sc->sc_ev_txptrc6 , EVCNT_TYPE_MISC, 692 NULL, device_xname(self), "TX pkts w/ptrs >5 hdr chains"); 693 evcnt_attach_dynamic(&sc->sc_ev_txptrh0 , EVCNT_TYPE_MISC, 694 NULL, device_xname(self), "TX pkts w/ptrs ~8bytes hdr"); 695 evcnt_attach_dynamic(&sc->sc_ev_txptrh1 , EVCNT_TYPE_MISC, 696 NULL, device_xname(self), "TX pkts w/ptrs ~16bytes hdr"); 697 evcnt_attach_dynamic(&sc->sc_ev_txptrh2 , EVCNT_TYPE_MISC, 698 NULL, device_xname(self), "TX pkts w/ptrs ~32bytes hdr"); 699 evcnt_attach_dynamic(&sc->sc_ev_txptrh3 , EVCNT_TYPE_MISC, 700 NULL, device_xname(self), "TX pkts w/ptrs ~64bytes hdr"); 701 evcnt_attach_dynamic(&sc->sc_ev_txptrh4 , EVCNT_TYPE_MISC, 702 NULL, device_xname(self), "TX pkts w/ptrs ~80bytes hdr"); 703 evcnt_attach_dynamic(&sc->sc_ev_txptrh5 , EVCNT_TYPE_MISC, 704 NULL, device_xname(self), "TX pkts w/ptrs ~96bytes hdr"); 705 evcnt_attach_dynamic(&sc->sc_ev_txdstall , EVCNT_TYPE_MISC, 706 NULL, device_xname(self), "TX stalled due to no txdesc"); 707 evcnt_attach_dynamic(&sc->sc_ev_txempty , EVCNT_TYPE_MISC, 708 NULL, device_xname(self), "TX empty interrupts"); 709 evcnt_attach_dynamic(&sc->sc_ev_txsent , EVCNT_TYPE_MISC, 710 NULL, device_xname(self), "TX sent interrupts"); 711 #endif 712 713 /* set shutdown hook to reset interface on powerdown */ 714 sc->sc_sdhook = shutdownhook_establish(mec_shutdown, sc); 715 716 return; 717 718 /* 719 * Free any resources we've allocated during the failed attach 720 * attempt. Do this in reverse order and fall though. 721 */ 722 fail_4: 723 for (i = 0; i < MEC_NTXDESC; i++) { 724 if (sc->sc_txsoft[i].txs_dmamap != NULL) 725 bus_dmamap_destroy(sc->sc_dmat, 726 sc->sc_txsoft[i].txs_dmamap); 727 } 728 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 729 fail_3: 730 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 731 fail_2: 732 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 733 sizeof(struct mec_control_data)); 734 fail_1: 735 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 736 fail_0: 737 return; 738 } 739 740 static int 741 mec_mii_readreg(device_t self, int phy, int reg) 742 { 743 struct mec_softc *sc = device_private(self); 744 bus_space_tag_t st = sc->sc_st; 745 bus_space_handle_t sh = sc->sc_sh; 746 uint64_t val; 747 int i; 748 749 if (mec_mii_wait(sc) != 0) 750 return 0; 751 752 bus_space_write_8(st, sh, MEC_PHY_ADDRESS, 753 (phy << MEC_PHY_ADDR_DEVSHIFT) | (reg & MEC_PHY_ADDR_REGISTER)); 754 delay(25); 755 bus_space_write_8(st, sh, MEC_PHY_READ_INITIATE, 1); 756 delay(25); 757 mec_mii_wait(sc); 758 759 for (i = 0; i < 20; i++) { 760 delay(30); 761 762 val = bus_space_read_8(st, sh, MEC_PHY_DATA); 763 764 if ((val & MEC_PHY_DATA_BUSY) == 0) 765 return val & MEC_PHY_DATA_VALUE; 766 } 767 return 0; 768 } 769 770 static void 771 mec_mii_writereg(device_t self, int phy, int reg, int val) 772 { 773 struct mec_softc *sc = device_private(self); 774 bus_space_tag_t st = sc->sc_st; 775 bus_space_handle_t sh = sc->sc_sh; 776 777 if (mec_mii_wait(sc) != 0) { 778 printf("timed out writing %x: %x\n", reg, val); 779 return; 780 } 781 782 bus_space_write_8(st, sh, MEC_PHY_ADDRESS, 783 (phy << MEC_PHY_ADDR_DEVSHIFT) | (reg & MEC_PHY_ADDR_REGISTER)); 784 785 delay(60); 786 787 bus_space_write_8(st, sh, MEC_PHY_DATA, val & MEC_PHY_DATA_VALUE); 788 789 delay(60); 790 791 mec_mii_wait(sc); 792 } 793 794 static int 795 mec_mii_wait(struct mec_softc *sc) 796 { 797 uint32_t busy; 798 int i, s; 799 800 for (i = 0; i < 100; i++) { 801 delay(30); 802 803 s = splhigh(); 804 busy = bus_space_read_8(sc->sc_st, sc->sc_sh, MEC_PHY_DATA); 805 splx(s); 806 807 if ((busy & MEC_PHY_DATA_BUSY) == 0) 808 return 0; 809 #if 0 810 if (busy == 0xffff) /* XXX ? */ 811 return 0; 812 #endif 813 } 814 815 printf("%s: MII timed out\n", device_xname(sc->sc_dev)); 816 return 1; 817 } 818 819 static void 820 mec_statchg(device_t self) 821 { 822 struct mec_softc *sc = device_private(self); 823 bus_space_tag_t st = sc->sc_st; 824 bus_space_handle_t sh = sc->sc_sh; 825 uint32_t control; 826 827 control = bus_space_read_8(st, sh, MEC_MAC_CONTROL); 828 control &= ~(MEC_MAC_IPGT | MEC_MAC_IPGR1 | MEC_MAC_IPGR2 | 829 MEC_MAC_FULL_DUPLEX | MEC_MAC_SPEED_SELECT); 830 831 /* must also set IPG here for duplex stuff ... */ 832 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) { 833 control |= MEC_MAC_FULL_DUPLEX; 834 } else { 835 /* set IPG */ 836 control |= MEC_MAC_IPG_DEFAULT; 837 } 838 839 bus_space_write_8(st, sh, MEC_MAC_CONTROL, control); 840 } 841 842 /* 843 * XXX 844 * maybe this function should be moved to common part 845 * (sgimips/machdep.c or elsewhere) for all on-board network devices. 846 */ 847 static void 848 enaddr_aton(const char *str, uint8_t *eaddr) 849 { 850 int i; 851 char c; 852 853 for (i = 0; i < ETHER_ADDR_LEN; i++) { 854 if (*str == ':') 855 str++; 856 857 c = *str++; 858 if (isdigit(c)) { 859 eaddr[i] = (c - '0'); 860 } else if (isxdigit(c)) { 861 eaddr[i] = (toupper(c) + 10 - 'A'); 862 } 863 c = *str++; 864 if (isdigit(c)) { 865 eaddr[i] = (eaddr[i] << 4) | (c - '0'); 866 } else if (isxdigit(c)) { 867 eaddr[i] = (eaddr[i] << 4) | (toupper(c) + 10 - 'A'); 868 } 869 } 870 } 871 872 static int 873 mec_init(struct ifnet *ifp) 874 { 875 struct mec_softc *sc = ifp->if_softc; 876 bus_space_tag_t st = sc->sc_st; 877 bus_space_handle_t sh = sc->sc_sh; 878 struct mec_rxdesc *rxd; 879 int i, rc; 880 881 /* cancel any pending I/O */ 882 mec_stop(ifp, 0); 883 884 /* reset device */ 885 mec_reset(sc); 886 887 /* setup filter for multicast or promisc mode */ 888 mec_setfilter(sc); 889 890 /* set the TX ring pointer to the base address */ 891 bus_space_write_8(st, sh, MEC_TX_RING_BASE, MEC_CDTXADDR(sc, 0)); 892 893 sc->sc_txpending = 0; 894 sc->sc_txdirty = 0; 895 sc->sc_txlast = MEC_NTXDESC - 1; 896 897 /* put RX buffers into FIFO */ 898 for (i = 0; i < MEC_NRXDESC; i++) { 899 rxd = &sc->sc_rxdesc[i]; 900 rxd->rxd_stat = 0; 901 MEC_RXSTATSYNC(sc, i, BUS_DMASYNC_PREREAD); 902 MEC_RXBUFSYNC(sc, i, ETHER_MAX_LEN, BUS_DMASYNC_PREREAD); 903 bus_space_write_8(st, sh, MEC_MCL_RX_FIFO, MEC_CDRXADDR(sc, i)); 904 } 905 sc->sc_rxptr = 0; 906 907 #if 0 /* XXX no info */ 908 bus_space_write_8(st, sh, MEC_TIMER, 0); 909 #endif 910 911 /* 912 * MEC_DMA_TX_INT_ENABLE will be set later otherwise it causes 913 * spurious interrupts when TX buffers are empty 914 */ 915 bus_space_write_8(st, sh, MEC_DMA_CONTROL, 916 (MEC_RXD_DMAOFFSET << MEC_DMA_RX_DMA_OFFSET_SHIFT) | 917 (MEC_NRXDESC << MEC_DMA_RX_INT_THRESH_SHIFT) | 918 MEC_DMA_TX_DMA_ENABLE | /* MEC_DMA_TX_INT_ENABLE | */ 919 MEC_DMA_RX_DMA_ENABLE | MEC_DMA_RX_INT_ENABLE); 920 921 callout_reset(&sc->sc_tick_ch, hz, mec_tick, sc); 922 923 if ((rc = ether_mediachange(ifp)) != 0) 924 return rc; 925 926 ifp->if_flags |= IFF_RUNNING; 927 ifp->if_flags &= ~IFF_OACTIVE; 928 mec_start(ifp); 929 930 return 0; 931 } 932 933 static void 934 mec_reset(struct mec_softc *sc) 935 { 936 bus_space_tag_t st = sc->sc_st; 937 bus_space_handle_t sh = sc->sc_sh; 938 uint64_t control; 939 940 /* stop DMA first */ 941 bus_space_write_8(st, sh, MEC_DMA_CONTROL, 0); 942 943 /* reset chip */ 944 bus_space_write_8(st, sh, MEC_MAC_CONTROL, MEC_MAC_CORE_RESET); 945 delay(1000); 946 bus_space_write_8(st, sh, MEC_MAC_CONTROL, 0); 947 delay(1000); 948 949 /* Default to 100/half and let auto-negotiation work its magic */ 950 control = MEC_MAC_SPEED_SELECT | MEC_MAC_FILTER_MATCHMULTI | 951 MEC_MAC_IPG_DEFAULT; 952 953 bus_space_write_8(st, sh, MEC_MAC_CONTROL, control); 954 /* stop DMA again for sanity */ 955 bus_space_write_8(st, sh, MEC_DMA_CONTROL, 0); 956 957 DPRINTF(MEC_DEBUG_RESET, ("mec: control now %llx\n", 958 bus_space_read_8(st, sh, MEC_MAC_CONTROL))); 959 } 960 961 static void 962 mec_start(struct ifnet *ifp) 963 { 964 struct mec_softc *sc = ifp->if_softc; 965 struct mbuf *m0, *m; 966 struct mec_txdesc *txd; 967 struct mec_txsoft *txs; 968 bus_dmamap_t dmamap; 969 bus_space_tag_t st = sc->sc_st; 970 bus_space_handle_t sh = sc->sc_sh; 971 int error, firsttx, nexttx, opending; 972 int len, bufoff, buflen, nsegs, align, resid, pseg, nptr, slen, i; 973 uint32_t txdcmd; 974 975 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 976 return; 977 978 /* 979 * Remember the previous txpending and the first transmit descriptor. 980 */ 981 opending = sc->sc_txpending; 982 firsttx = MEC_NEXTTX(sc->sc_txlast); 983 984 DPRINTF(MEC_DEBUG_START, 985 ("mec_start: opending = %d, firsttx = %d\n", opending, firsttx)); 986 987 while (sc->sc_txpending < MEC_NTXDESC - 1) { 988 /* Grab a packet off the queue. */ 989 IFQ_POLL(&ifp->if_snd, m0); 990 if (m0 == NULL) 991 break; 992 m = NULL; 993 994 /* 995 * Get the next available transmit descriptor. 996 */ 997 nexttx = MEC_NEXTTX(sc->sc_txlast); 998 txd = &sc->sc_txdesc[nexttx]; 999 txs = &sc->sc_txsoft[nexttx]; 1000 dmamap = txs->txs_dmamap; 1001 txs->txs_flags = 0; 1002 1003 buflen = 0; 1004 bufoff = 0; 1005 resid = 0; 1006 nptr = 0; /* XXX gcc */ 1007 pseg = 0; /* XXX gcc */ 1008 1009 len = m0->m_pkthdr.len; 1010 1011 DPRINTF(MEC_DEBUG_START, 1012 ("mec_start: len = %d, nexttx = %d, txpending = %d\n", 1013 len, nexttx, sc->sc_txpending)); 1014 1015 if (len <= MEC_TXD_BUFSIZE) { 1016 /* 1017 * If a TX packet will fit into small txdesc buffer, 1018 * just copy it into there. Maybe it's faster than 1019 * checking alignment and calling bus_dma(9) etc. 1020 */ 1021 DPRINTF(MEC_DEBUG_START, ("mec_start: short packet\n")); 1022 IFQ_DEQUEUE(&ifp->if_snd, m0); 1023 1024 /* 1025 * I don't know if MEC chip does auto padding, 1026 * but do it manually for safety. 1027 */ 1028 if (len < ETHER_PAD_LEN) { 1029 MEC_EVCNT_INCR(&sc->sc_ev_txdpad); 1030 bufoff = MEC_TXD_BUFSTART(ETHER_PAD_LEN); 1031 m_copydata(m0, 0, len, txd->txd_buf + bufoff); 1032 memset(txd->txd_buf + bufoff + len, 0, 1033 ETHER_PAD_LEN - len); 1034 len = buflen = ETHER_PAD_LEN; 1035 } else { 1036 MEC_EVCNT_INCR(&sc->sc_ev_txdbuf); 1037 bufoff = MEC_TXD_BUFSTART(len); 1038 m_copydata(m0, 0, len, txd->txd_buf + bufoff); 1039 buflen = len; 1040 } 1041 } else { 1042 /* 1043 * If the packet won't fit the static buffer in txdesc, 1044 * we have to use the concatenate pointers to handle it. 1045 */ 1046 DPRINTF(MEC_DEBUG_START, ("mec_start: long packet\n")); 1047 txs->txs_flags = MEC_TXS_TXDPTR; 1048 1049 /* 1050 * Call bus_dmamap_load_mbuf(9) first to see 1051 * how many chains the TX mbuf has. 1052 */ 1053 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1054 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1055 if (error == 0) { 1056 /* 1057 * Check chains which might contain headers. 1058 * They might be so much fragmented and 1059 * it's better to copy them into txdesc buffer 1060 * since they would be small enough. 1061 */ 1062 nsegs = dmamap->dm_nsegs; 1063 for (pseg = 0; pseg < nsegs; pseg++) { 1064 slen = dmamap->dm_segs[pseg].ds_len; 1065 if (buflen + slen > 1066 MEC_TXD_BUFSIZE1 - MEC_TXD_ALIGN) 1067 break; 1068 buflen += slen; 1069 } 1070 /* 1071 * Check if the rest chains can be fit into 1072 * the concatinate pointers. 1073 */ 1074 align = dmamap->dm_segs[pseg].ds_addr & 1075 MEC_TXD_ALIGNMASK; 1076 if (align > 0) { 1077 /* 1078 * If the first chain isn't uint64_t 1079 * aligned, append the unaligned part 1080 * into txdesc buffer too. 1081 */ 1082 resid = MEC_TXD_ALIGN - align; 1083 buflen += resid; 1084 for (; pseg < nsegs; pseg++) { 1085 slen = 1086 dmamap->dm_segs[pseg].ds_len; 1087 if (slen > resid) 1088 break; 1089 resid -= slen; 1090 } 1091 } else if (pseg == 0) { 1092 /* 1093 * In this case, the first chain is 1094 * uint64_t aligned but it's too long 1095 * to put into txdesc buf. 1096 * We have to put some data into 1097 * txdesc buf even in this case, 1098 * so put MEC_TXD_ALIGN bytes there. 1099 */ 1100 buflen = resid = MEC_TXD_ALIGN; 1101 } 1102 nptr = nsegs - pseg; 1103 if (nptr <= MEC_NTXPTR) { 1104 bufoff = MEC_TXD_BUFSTART(buflen); 1105 1106 /* 1107 * Check if all the rest chains are 1108 * uint64_t aligned. 1109 */ 1110 align = 0; 1111 for (i = pseg + 1; i < nsegs; i++) 1112 align |= 1113 dmamap->dm_segs[i].ds_addr 1114 & MEC_TXD_ALIGNMASK; 1115 if (align != 0) { 1116 /* chains are not aligned */ 1117 error = -1; 1118 } 1119 } else { 1120 /* The TX mbuf chains doesn't fit. */ 1121 error = -1; 1122 } 1123 if (error == -1) 1124 bus_dmamap_unload(sc->sc_dmat, dmamap); 1125 } 1126 if (error != 0) { 1127 /* 1128 * The TX mbuf chains can't be put into 1129 * the concatinate buffers. In this case, 1130 * we have to allocate a new contiguous mbuf 1131 * and copy data into it. 1132 * 1133 * Even in this case, the Ethernet header in 1134 * the TX mbuf might be unaligned and trailing 1135 * data might be word aligned, so put 2 byte 1136 * (MEC_ETHER_ALIGN) padding at the top of the 1137 * allocated mbuf and copy TX packets. 1138 * 6 bytes (MEC_ALIGN_BYTES - MEC_ETHER_ALIGN) 1139 * at the top of the new mbuf won't be uint64_t 1140 * alignd, but we have to put some data into 1141 * txdesc buffer anyway even if the buffer 1142 * is uint64_t aligned. 1143 */ 1144 DPRINTF(MEC_DEBUG_START|MEC_DEBUG_TXSEGS, 1145 ("mec_start: re-allocating mbuf\n")); 1146 1147 MGETHDR(m, M_DONTWAIT, MT_DATA); 1148 if (m == NULL) { 1149 printf("%s: unable to allocate " 1150 "TX mbuf\n", 1151 device_xname(sc->sc_dev)); 1152 break; 1153 } 1154 if (len > (MHLEN - MEC_ETHER_ALIGN)) { 1155 MCLGET(m, M_DONTWAIT); 1156 if ((m->m_flags & M_EXT) == 0) { 1157 printf("%s: unable to allocate " 1158 "TX cluster\n", 1159 device_xname(sc->sc_dev)); 1160 m_freem(m); 1161 break; 1162 } 1163 } 1164 m->m_data += MEC_ETHER_ALIGN; 1165 1166 /* 1167 * Copy whole data (including unaligned part) 1168 * for following bpf_mtap(). 1169 */ 1170 m_copydata(m0, 0, len, mtod(m, void *)); 1171 m->m_pkthdr.len = m->m_len = len; 1172 error = bus_dmamap_load_mbuf(sc->sc_dmat, 1173 dmamap, m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1174 if (dmamap->dm_nsegs > 1) { 1175 /* should not happen, but for sanity */ 1176 bus_dmamap_unload(sc->sc_dmat, dmamap); 1177 error = -1; 1178 } 1179 if (error != 0) { 1180 printf("%s: unable to load TX buffer, " 1181 "error = %d\n", 1182 device_xname(sc->sc_dev), error); 1183 m_freem(m); 1184 break; 1185 } 1186 /* 1187 * Only the first segment should be put into 1188 * the concatinate pointer in this case. 1189 */ 1190 pseg = 0; 1191 nptr = 1; 1192 1193 /* 1194 * Set lenght of unaligned part which will be 1195 * copied into txdesc buffer. 1196 */ 1197 buflen = MEC_TXD_ALIGN - MEC_ETHER_ALIGN; 1198 bufoff = MEC_TXD_BUFSTART(buflen); 1199 resid = buflen; 1200 #ifdef MEC_EVENT_COUNTERS 1201 MEC_EVCNT_INCR(&sc->sc_ev_txmbuf); 1202 if (len <= 160) 1203 MEC_EVCNT_INCR(&sc->sc_ev_txmbufa); 1204 else if (len <= 256) 1205 MEC_EVCNT_INCR(&sc->sc_ev_txmbufb); 1206 else if (len <= 512) 1207 MEC_EVCNT_INCR(&sc->sc_ev_txmbufc); 1208 else if (len <= 1024) 1209 MEC_EVCNT_INCR(&sc->sc_ev_txmbufd); 1210 else 1211 MEC_EVCNT_INCR(&sc->sc_ev_txmbufe); 1212 #endif 1213 } 1214 #ifdef MEC_EVENT_COUNTERS 1215 else { 1216 MEC_EVCNT_INCR(&sc->sc_ev_txptrs); 1217 if (nptr == 1) { 1218 MEC_EVCNT_INCR(&sc->sc_ev_txptr1); 1219 if (len <= 160) 1220 MEC_EVCNT_INCR( 1221 &sc->sc_ev_txptr1a); 1222 else if (len <= 256) 1223 MEC_EVCNT_INCR( 1224 &sc->sc_ev_txptr1b); 1225 else if (len <= 512) 1226 MEC_EVCNT_INCR( 1227 &sc->sc_ev_txptr1c); 1228 else if (len <= 1024) 1229 MEC_EVCNT_INCR( 1230 &sc->sc_ev_txptr1d); 1231 else 1232 MEC_EVCNT_INCR( 1233 &sc->sc_ev_txptr1e); 1234 } else if (nptr == 2) { 1235 MEC_EVCNT_INCR(&sc->sc_ev_txptr2); 1236 if (len <= 160) 1237 MEC_EVCNT_INCR( 1238 &sc->sc_ev_txptr2a); 1239 else if (len <= 256) 1240 MEC_EVCNT_INCR( 1241 &sc->sc_ev_txptr2b); 1242 else if (len <= 512) 1243 MEC_EVCNT_INCR( 1244 &sc->sc_ev_txptr2c); 1245 else if (len <= 1024) 1246 MEC_EVCNT_INCR( 1247 &sc->sc_ev_txptr2d); 1248 else 1249 MEC_EVCNT_INCR( 1250 &sc->sc_ev_txptr2e); 1251 } else if (nptr == 3) { 1252 MEC_EVCNT_INCR(&sc->sc_ev_txptr3); 1253 if (len <= 160) 1254 MEC_EVCNT_INCR( 1255 &sc->sc_ev_txptr3a); 1256 else if (len <= 256) 1257 MEC_EVCNT_INCR( 1258 &sc->sc_ev_txptr3b); 1259 else if (len <= 512) 1260 MEC_EVCNT_INCR( 1261 &sc->sc_ev_txptr3c); 1262 else if (len <= 1024) 1263 MEC_EVCNT_INCR( 1264 &sc->sc_ev_txptr3d); 1265 else 1266 MEC_EVCNT_INCR( 1267 &sc->sc_ev_txptr3e); 1268 } 1269 if (pseg == 0) 1270 MEC_EVCNT_INCR(&sc->sc_ev_txptrc0); 1271 else if (pseg == 1) 1272 MEC_EVCNT_INCR(&sc->sc_ev_txptrc1); 1273 else if (pseg == 2) 1274 MEC_EVCNT_INCR(&sc->sc_ev_txptrc2); 1275 else if (pseg == 3) 1276 MEC_EVCNT_INCR(&sc->sc_ev_txptrc3); 1277 else if (pseg == 4) 1278 MEC_EVCNT_INCR(&sc->sc_ev_txptrc4); 1279 else if (pseg == 5) 1280 MEC_EVCNT_INCR(&sc->sc_ev_txptrc5); 1281 else 1282 MEC_EVCNT_INCR(&sc->sc_ev_txptrc6); 1283 if (buflen <= 8) 1284 MEC_EVCNT_INCR(&sc->sc_ev_txptrh0); 1285 else if (buflen <= 16) 1286 MEC_EVCNT_INCR(&sc->sc_ev_txptrh1); 1287 else if (buflen <= 32) 1288 MEC_EVCNT_INCR(&sc->sc_ev_txptrh2); 1289 else if (buflen <= 64) 1290 MEC_EVCNT_INCR(&sc->sc_ev_txptrh3); 1291 else if (buflen <= 80) 1292 MEC_EVCNT_INCR(&sc->sc_ev_txptrh4); 1293 else 1294 MEC_EVCNT_INCR(&sc->sc_ev_txptrh5); 1295 } 1296 #endif 1297 m_copydata(m0, 0, buflen, txd->txd_buf + bufoff); 1298 1299 IFQ_DEQUEUE(&ifp->if_snd, m0); 1300 if (m != NULL) { 1301 m_freem(m0); 1302 m0 = m; 1303 } 1304 1305 /* 1306 * sync the DMA map for TX mbuf 1307 */ 1308 bus_dmamap_sync(sc->sc_dmat, dmamap, buflen, 1309 len - buflen, BUS_DMASYNC_PREWRITE); 1310 } 1311 1312 #if NBPFILTER > 0 1313 /* 1314 * Pass packet to bpf if there is a listener. 1315 */ 1316 if (ifp->if_bpf) 1317 bpf_mtap(ifp->if_bpf, m0); 1318 #endif 1319 MEC_EVCNT_INCR(&sc->sc_ev_txpkts); 1320 1321 /* 1322 * setup the transmit descriptor. 1323 */ 1324 txdcmd = TXCMD_BUFSTART(MEC_TXDESCSIZE - buflen) | (len - 1); 1325 1326 /* 1327 * Set MEC_TXCMD_TXINT every MEC_NTXDESC_INTR packets 1328 * if more than half txdescs have been queued 1329 * because TX_EMPTY interrupts will rarely happen 1330 * if TX queue is so stacked. 1331 */ 1332 if (sc->sc_txpending > (MEC_NTXDESC / 2) && 1333 (nexttx & (MEC_NTXDESC_INTR - 1)) == 0) 1334 txdcmd |= MEC_TXCMD_TXINT; 1335 1336 if ((txs->txs_flags & MEC_TXS_TXDPTR) != 0) { 1337 bus_dma_segment_t *segs = dmamap->dm_segs; 1338 1339 DPRINTF(MEC_DEBUG_TXSEGS, 1340 ("mec_start: nsegs = %d, pseg = %d, nptr = %d\n", 1341 dmamap->dm_nsegs, pseg, nptr)); 1342 1343 switch (nptr) { 1344 case 3: 1345 KASSERT((segs[pseg + 2].ds_addr & 1346 MEC_TXD_ALIGNMASK) == 0); 1347 txdcmd |= MEC_TXCMD_PTR3; 1348 txd->txd_ptr[2] = 1349 TXPTR_LEN(segs[pseg + 2].ds_len - 1) | 1350 segs[pseg + 2].ds_addr; 1351 /* FALLTHROUGH */ 1352 case 2: 1353 KASSERT((segs[pseg + 1].ds_addr & 1354 MEC_TXD_ALIGNMASK) == 0); 1355 txdcmd |= MEC_TXCMD_PTR2; 1356 txd->txd_ptr[1] = 1357 TXPTR_LEN(segs[pseg + 1].ds_len - 1) | 1358 segs[pseg + 1].ds_addr; 1359 /* FALLTHROUGH */ 1360 case 1: 1361 txdcmd |= MEC_TXCMD_PTR1; 1362 txd->txd_ptr[0] = 1363 TXPTR_LEN(segs[pseg].ds_len - resid - 1) | 1364 (segs[pseg].ds_addr + resid); 1365 break; 1366 default: 1367 panic("%s: impossible nptr in %s", 1368 device_xname(sc->sc_dev), __func__); 1369 /* NOTREACHED */ 1370 } 1371 /* 1372 * Store a pointer to the packet so we can 1373 * free it later. 1374 */ 1375 txs->txs_mbuf = m0; 1376 } else { 1377 /* 1378 * In this case all data are copied to buffer in txdesc, 1379 * we can free TX mbuf here. 1380 */ 1381 m_freem(m0); 1382 } 1383 txd->txd_cmd = txdcmd; 1384 1385 DPRINTF(MEC_DEBUG_START, 1386 ("mec_start: txd_cmd = 0x%016llx\n", txd->txd_cmd)); 1387 DPRINTF(MEC_DEBUG_START, 1388 ("mec_start: txd_ptr[0] = 0x%016llx\n", txd->txd_ptr[0])); 1389 DPRINTF(MEC_DEBUG_START, 1390 ("mec_start: txd_ptr[1] = 0x%016llx\n", txd->txd_ptr[1])); 1391 DPRINTF(MEC_DEBUG_START, 1392 ("mec_start: txd_ptr[2] = 0x%016llx\n", txd->txd_ptr[2])); 1393 DPRINTF(MEC_DEBUG_START, 1394 ("mec_start: len = %d (0x%04x), buflen = %d (0x%02x)\n", 1395 len, len, buflen, buflen)); 1396 1397 /* sync TX descriptor */ 1398 MEC_TXDESCSYNC(sc, nexttx, 1399 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1400 1401 /* start TX */ 1402 bus_space_write_8(st, sh, MEC_TX_RING_PTR, MEC_NEXTTX(nexttx)); 1403 1404 /* advance the TX pointer. */ 1405 sc->sc_txpending++; 1406 sc->sc_txlast = nexttx; 1407 } 1408 1409 if (sc->sc_txpending == MEC_NTXDESC - 1) { 1410 /* No more slots; notify upper layer. */ 1411 MEC_EVCNT_INCR(&sc->sc_ev_txdstall); 1412 ifp->if_flags |= IFF_OACTIVE; 1413 } 1414 1415 if (sc->sc_txpending != opending) { 1416 /* 1417 * If the transmitter was idle, 1418 * reset the txdirty pointer and re-enable TX interrupt. 1419 */ 1420 if (opending == 0) { 1421 sc->sc_txdirty = firsttx; 1422 bus_space_write_8(st, sh, MEC_TX_ALIAS, 1423 MEC_TX_ALIAS_INT_ENABLE); 1424 } 1425 1426 /* Set a watchdog timer in case the chip flakes out. */ 1427 ifp->if_timer = 5; 1428 } 1429 } 1430 1431 static void 1432 mec_stop(struct ifnet *ifp, int disable) 1433 { 1434 struct mec_softc *sc = ifp->if_softc; 1435 struct mec_txsoft *txs; 1436 int i; 1437 1438 DPRINTF(MEC_DEBUG_STOP, ("mec_stop\n")); 1439 1440 ifp->if_timer = 0; 1441 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1442 1443 callout_stop(&sc->sc_tick_ch); 1444 mii_down(&sc->sc_mii); 1445 1446 /* release any TX buffers */ 1447 for (i = 0; i < MEC_NTXDESC; i++) { 1448 txs = &sc->sc_txsoft[i]; 1449 if ((txs->txs_flags & MEC_TXS_TXDPTR) != 0) { 1450 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1451 m_freem(txs->txs_mbuf); 1452 txs->txs_mbuf = NULL; 1453 } 1454 } 1455 } 1456 1457 static int 1458 mec_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1459 { 1460 int s, error; 1461 1462 s = splnet(); 1463 1464 error = ether_ioctl(ifp, cmd, data); 1465 if (error == ENETRESET) { 1466 /* 1467 * Multicast list has changed; set the hardware filter 1468 * accordingly. 1469 */ 1470 if (ifp->if_flags & IFF_RUNNING) 1471 error = mec_init(ifp); 1472 else 1473 error = 0; 1474 } 1475 1476 /* Try to get more packets going. */ 1477 mec_start(ifp); 1478 1479 splx(s); 1480 return error; 1481 } 1482 1483 static void 1484 mec_watchdog(struct ifnet *ifp) 1485 { 1486 struct mec_softc *sc = ifp->if_softc; 1487 1488 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 1489 ifp->if_oerrors++; 1490 1491 mec_init(ifp); 1492 } 1493 1494 static void 1495 mec_tick(void *arg) 1496 { 1497 struct mec_softc *sc = arg; 1498 int s; 1499 1500 s = splnet(); 1501 mii_tick(&sc->sc_mii); 1502 splx(s); 1503 1504 callout_reset(&sc->sc_tick_ch, hz, mec_tick, sc); 1505 } 1506 1507 static void 1508 mec_setfilter(struct mec_softc *sc) 1509 { 1510 struct ethercom *ec = &sc->sc_ethercom; 1511 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1512 struct ether_multi *enm; 1513 struct ether_multistep step; 1514 bus_space_tag_t st = sc->sc_st; 1515 bus_space_handle_t sh = sc->sc_sh; 1516 uint64_t mchash; 1517 uint32_t control, hash; 1518 int mcnt; 1519 1520 control = bus_space_read_8(st, sh, MEC_MAC_CONTROL); 1521 control &= ~MEC_MAC_FILTER_MASK; 1522 1523 if (ifp->if_flags & IFF_PROMISC) { 1524 control |= MEC_MAC_FILTER_PROMISC; 1525 bus_space_write_8(st, sh, MEC_MULTICAST, 0xffffffffffffffffULL); 1526 bus_space_write_8(st, sh, MEC_MAC_CONTROL, control); 1527 return; 1528 } 1529 1530 mcnt = 0; 1531 mchash = 0; 1532 ETHER_FIRST_MULTI(step, ec, enm); 1533 while (enm != NULL) { 1534 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1535 /* set allmulti for a range of multicast addresses */ 1536 control |= MEC_MAC_FILTER_ALLMULTI; 1537 bus_space_write_8(st, sh, MEC_MULTICAST, 1538 0xffffffffffffffffULL); 1539 bus_space_write_8(st, sh, MEC_MAC_CONTROL, control); 1540 return; 1541 } 1542 1543 #define mec_calchash(addr) (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26) 1544 1545 hash = mec_calchash(enm->enm_addrlo); 1546 mchash |= 1 << hash; 1547 mcnt++; 1548 ETHER_NEXT_MULTI(step, enm); 1549 } 1550 1551 ifp->if_flags &= ~IFF_ALLMULTI; 1552 1553 if (mcnt > 0) 1554 control |= MEC_MAC_FILTER_MATCHMULTI; 1555 1556 bus_space_write_8(st, sh, MEC_MULTICAST, mchash); 1557 bus_space_write_8(st, sh, MEC_MAC_CONTROL, control); 1558 } 1559 1560 static int 1561 mec_intr(void *arg) 1562 { 1563 struct mec_softc *sc = arg; 1564 bus_space_tag_t st = sc->sc_st; 1565 bus_space_handle_t sh = sc->sc_sh; 1566 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1567 uint32_t statreg, statack, txptr; 1568 int handled, sent; 1569 1570 DPRINTF(MEC_DEBUG_INTR, ("mec_intr: called\n")); 1571 1572 handled = sent = 0; 1573 1574 for (;;) { 1575 statreg = bus_space_read_8(st, sh, MEC_INT_STATUS); 1576 1577 DPRINTF(MEC_DEBUG_INTR, 1578 ("mec_intr: INT_STAT = 0x%08x\n", statreg)); 1579 1580 statack = statreg & MEC_INT_STATUS_MASK; 1581 if (statack == 0) 1582 break; 1583 bus_space_write_8(st, sh, MEC_INT_STATUS, statack); 1584 1585 handled = 1; 1586 1587 if (statack & 1588 (MEC_INT_RX_THRESHOLD | 1589 MEC_INT_RX_FIFO_UNDERFLOW)) { 1590 mec_rxintr(sc); 1591 } 1592 1593 if (statack & 1594 (MEC_INT_TX_EMPTY | 1595 MEC_INT_TX_PACKET_SENT | 1596 MEC_INT_TX_ABORT)) { 1597 txptr = (statreg & MEC_INT_TX_RING_BUFFER_ALIAS) 1598 >> MEC_INT_TX_RING_BUFFER_SHIFT; 1599 mec_txintr(sc, txptr); 1600 sent = 1; 1601 if ((statack & MEC_INT_TX_EMPTY) != 0) { 1602 /* 1603 * disable TX interrupt to stop 1604 * TX empty interrupt 1605 */ 1606 bus_space_write_8(st, sh, MEC_TX_ALIAS, 0); 1607 DPRINTF(MEC_DEBUG_INTR, 1608 ("mec_intr: disable TX_INT\n")); 1609 } 1610 #ifdef MEC_EVENT_COUNTERS 1611 if ((statack & MEC_INT_TX_EMPTY) != 0) 1612 MEC_EVCNT_INCR(&sc->sc_ev_txempty); 1613 if ((statack & MEC_INT_TX_PACKET_SENT) != 0) 1614 MEC_EVCNT_INCR(&sc->sc_ev_txsent); 1615 #endif 1616 } 1617 1618 if (statack & 1619 (MEC_INT_TX_LINK_FAIL | 1620 MEC_INT_TX_MEM_ERROR | 1621 MEC_INT_TX_ABORT | 1622 MEC_INT_RX_FIFO_UNDERFLOW | 1623 MEC_INT_RX_DMA_UNDERFLOW)) { 1624 printf("%s: mec_intr: interrupt status = 0x%08x\n", 1625 device_xname(sc->sc_dev), statreg); 1626 mec_init(ifp); 1627 break; 1628 } 1629 } 1630 1631 if (sent && !IFQ_IS_EMPTY(&ifp->if_snd)) { 1632 /* try to get more packets going */ 1633 mec_start(ifp); 1634 } 1635 1636 #if NRND > 0 1637 if (handled) 1638 rnd_add_uint32(&sc->sc_rnd_source, statreg); 1639 #endif 1640 1641 return handled; 1642 } 1643 1644 static void 1645 mec_rxintr(struct mec_softc *sc) 1646 { 1647 bus_space_tag_t st = sc->sc_st; 1648 bus_space_handle_t sh = sc->sc_sh; 1649 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1650 struct mbuf *m; 1651 struct mec_rxdesc *rxd; 1652 uint64_t rxstat; 1653 u_int len; 1654 int i; 1655 1656 DPRINTF(MEC_DEBUG_RXINTR, ("mec_rxintr: called\n")); 1657 1658 for (i = sc->sc_rxptr;; i = MEC_NEXTRX(i)) { 1659 rxd = &sc->sc_rxdesc[i]; 1660 1661 MEC_RXSTATSYNC(sc, i, BUS_DMASYNC_POSTREAD); 1662 rxstat = rxd->rxd_stat; 1663 1664 DPRINTF(MEC_DEBUG_RXINTR, 1665 ("mec_rxintr: rxstat = 0x%016llx, rxptr = %d\n", 1666 rxstat, i)); 1667 DPRINTF(MEC_DEBUG_RXINTR, ("mec_rxintr: rxfifo = 0x%08x\n", 1668 (u_int)bus_space_read_8(st, sh, MEC_RX_FIFO))); 1669 1670 if ((rxstat & MEC_RXSTAT_RECEIVED) == 0) { 1671 MEC_RXSTATSYNC(sc, i, BUS_DMASYNC_PREREAD); 1672 break; 1673 } 1674 1675 len = rxstat & MEC_RXSTAT_LEN; 1676 1677 if (len < ETHER_MIN_LEN || 1678 len > (MCLBYTES - MEC_ETHER_ALIGN)) { 1679 /* invalid length packet; drop it. */ 1680 DPRINTF(MEC_DEBUG_RXINTR, 1681 ("mec_rxintr: wrong packet\n")); 1682 dropit: 1683 ifp->if_ierrors++; 1684 rxd->rxd_stat = 0; 1685 MEC_RXSTATSYNC(sc, i, BUS_DMASYNC_PREREAD); 1686 bus_space_write_8(st, sh, MEC_MCL_RX_FIFO, 1687 MEC_CDRXADDR(sc, i)); 1688 continue; 1689 } 1690 1691 if (rxstat & 1692 (MEC_RXSTAT_BADPACKET | 1693 MEC_RXSTAT_LONGEVENT | 1694 MEC_RXSTAT_INVALID | 1695 MEC_RXSTAT_CRCERROR | 1696 MEC_RXSTAT_VIOLATION)) { 1697 printf("%s: mec_rxintr: status = 0x%016llx\n", 1698 device_xname(sc->sc_dev), rxstat); 1699 goto dropit; 1700 } 1701 1702 /* 1703 * The MEC includes the CRC with every packet. Trim 1704 * it off here. 1705 */ 1706 len -= ETHER_CRC_LEN; 1707 1708 /* 1709 * now allocate an mbuf (and possibly a cluster) to hold 1710 * the received packet. 1711 */ 1712 MGETHDR(m, M_DONTWAIT, MT_DATA); 1713 if (m == NULL) { 1714 printf("%s: unable to allocate RX mbuf\n", 1715 device_xname(sc->sc_dev)); 1716 goto dropit; 1717 } 1718 if (len > (MHLEN - MEC_ETHER_ALIGN)) { 1719 MCLGET(m, M_DONTWAIT); 1720 if ((m->m_flags & M_EXT) == 0) { 1721 printf("%s: unable to allocate RX cluster\n", 1722 device_xname(sc->sc_dev)); 1723 m_freem(m); 1724 m = NULL; 1725 goto dropit; 1726 } 1727 } 1728 1729 /* 1730 * Note MEC chip seems to insert 2 byte padding at the top of 1731 * RX buffer, but we copy whole buffer to avoid unaligned copy. 1732 */ 1733 MEC_RXBUFSYNC(sc, i, len, BUS_DMASYNC_POSTREAD); 1734 memcpy(mtod(m, void *), rxd->rxd_buf, MEC_ETHER_ALIGN + len); 1735 MEC_RXBUFSYNC(sc, i, ETHER_MAX_LEN, BUS_DMASYNC_PREREAD); 1736 m->m_data += MEC_ETHER_ALIGN; 1737 1738 /* put RX buffer into FIFO again */ 1739 rxd->rxd_stat = 0; 1740 MEC_RXSTATSYNC(sc, i, BUS_DMASYNC_PREREAD); 1741 bus_space_write_8(st, sh, MEC_MCL_RX_FIFO, MEC_CDRXADDR(sc, i)); 1742 1743 m->m_pkthdr.rcvif = ifp; 1744 m->m_pkthdr.len = m->m_len = len; 1745 1746 ifp->if_ipackets++; 1747 1748 #if NBPFILTER > 0 1749 /* 1750 * Pass this up to any BPF listeners, but only 1751 * pass it up the stack if it's for us. 1752 */ 1753 if (ifp->if_bpf) 1754 bpf_mtap(ifp->if_bpf, m); 1755 #endif 1756 1757 /* Pass it on. */ 1758 (*ifp->if_input)(ifp, m); 1759 } 1760 1761 /* update RX pointer */ 1762 sc->sc_rxptr = i; 1763 } 1764 1765 static void 1766 mec_txintr(struct mec_softc *sc, uint32_t txptr) 1767 { 1768 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1769 struct mec_txdesc *txd; 1770 struct mec_txsoft *txs; 1771 bus_dmamap_t dmamap; 1772 uint64_t txstat; 1773 int i; 1774 u_int col; 1775 1776 DPRINTF(MEC_DEBUG_TXINTR, ("mec_txintr: called\n")); 1777 1778 for (i = sc->sc_txdirty; i != txptr && sc->sc_txpending != 0; 1779 i = MEC_NEXTTX(i), sc->sc_txpending--) { 1780 txd = &sc->sc_txdesc[i]; 1781 1782 MEC_TXCMDSYNC(sc, i, 1783 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1784 1785 txstat = txd->txd_stat; 1786 DPRINTF(MEC_DEBUG_TXINTR, 1787 ("mec_txintr: dirty = %d, txstat = 0x%016llx\n", 1788 i, txstat)); 1789 if ((txstat & MEC_TXSTAT_SENT) == 0) { 1790 MEC_TXCMDSYNC(sc, i, BUS_DMASYNC_PREREAD); 1791 break; 1792 } 1793 1794 txs = &sc->sc_txsoft[i]; 1795 if ((txs->txs_flags & MEC_TXS_TXDPTR) != 0) { 1796 dmamap = txs->txs_dmamap; 1797 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, 1798 dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1799 bus_dmamap_unload(sc->sc_dmat, dmamap); 1800 m_freem(txs->txs_mbuf); 1801 txs->txs_mbuf = NULL; 1802 } 1803 1804 col = (txstat & MEC_TXSTAT_COLCNT) >> MEC_TXSTAT_COLCNT_SHIFT; 1805 ifp->if_collisions += col; 1806 1807 if ((txstat & MEC_TXSTAT_SUCCESS) == 0) { 1808 printf("%s: TX error: txstat = 0x%016llx\n", 1809 device_xname(sc->sc_dev), txstat); 1810 ifp->if_oerrors++; 1811 } else 1812 ifp->if_opackets++; 1813 } 1814 1815 /* update the dirty TX buffer pointer */ 1816 sc->sc_txdirty = i; 1817 DPRINTF(MEC_DEBUG_INTR, 1818 ("mec_txintr: sc_txdirty = %2d, sc_txpending = %2d\n", 1819 sc->sc_txdirty, sc->sc_txpending)); 1820 1821 /* cancel the watchdog timer if there are no pending TX packets */ 1822 if (sc->sc_txpending == 0) 1823 ifp->if_timer = 0; 1824 if (sc->sc_txpending < MEC_NTXDESC - MEC_NTXDESC_RSVD) 1825 ifp->if_flags &= ~IFF_OACTIVE; 1826 } 1827 1828 static void 1829 mec_shutdown(void *arg) 1830 { 1831 struct mec_softc *sc = arg; 1832 1833 mec_stop(&sc->sc_ethercom.ec_if, 1); 1834 /* make sure to stop DMA etc. */ 1835 mec_reset(sc); 1836 } 1837
Indexes created Tue Sep 30 17:09:57 GMT 2025