if_mec.c revision 1.58
1 /* $NetBSD: if_mec.c,v 1.58 2019/01/22 03:42:26 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2004, 2008 Izumi Tsutsui. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /* 28 * Copyright (c) 2003 Christopher SEKIYA 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 1. Redistributions of source code must retain the above copyright 35 * notice, this list of conditions and the following disclaimer. 36 * 2. Redistributions in binary form must reproduce the above copyright 37 * notice, this list of conditions and the following disclaimer in the 38 * documentation and/or other materials provided with the distribution. 39 * 3. All advertising materials mentioning features or use of this software 40 * must display the following acknowledgement: 41 * This product includes software developed for the 42 * NetBSD Project. See http://www.NetBSD.org/ for 43 * information about NetBSD. 44 * 4. The name of the author may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 /* 60 * MACE MAC-110 Ethernet driver 61 */ 62 63 #include <sys/cdefs.h> 64 __KERNEL_RCSID(0, "$NetBSD: if_mec.c,v 1.58 2019/01/22 03:42:26 msaitoh Exp $"); 65 66 #include "opt_ddb.h" 67 68 #include <sys/param.h> 69 #include <sys/systm.h> 70 #include <sys/device.h> 71 #include <sys/callout.h> 72 #include <sys/mbuf.h> 73 #include <sys/malloc.h> 74 #include <sys/kernel.h> 75 #include <sys/socket.h> 76 #include <sys/ioctl.h> 77 #include <sys/errno.h> 78 79 #include <sys/rndsource.h> 80 81 #include <net/if.h> 82 #include <net/if_dl.h> 83 #include <net/if_media.h> 84 #include <net/if_ether.h> 85 86 #include <netinet/in.h> 87 #include <netinet/in_systm.h> 88 #include <netinet/ip.h> 89 #include <netinet/tcp.h> 90 #include <netinet/udp.h> 91 92 #include <net/bpf.h> 93 94 #include <sys/bus.h> 95 #include <machine/intr.h> 96 #include <machine/machtype.h> 97 98 #include <dev/mii/mii.h> 99 #include <dev/mii/miivar.h> 100 101 #include <sgimips/mace/macevar.h> 102 #include <sgimips/mace/if_mecreg.h> 103 104 #include <dev/arcbios/arcbios.h> 105 #include <dev/arcbios/arcbiosvar.h> 106 107 /* #define MEC_DEBUG */ 108 109 #ifdef MEC_DEBUG 110 #define MEC_DEBUG_RESET 0x01 111 #define MEC_DEBUG_START 0x02 112 #define MEC_DEBUG_STOP 0x04 113 #define MEC_DEBUG_INTR 0x08 114 #define MEC_DEBUG_RXINTR 0x10 115 #define MEC_DEBUG_TXINTR 0x20 116 #define MEC_DEBUG_TXSEGS 0x40 117 uint32_t mec_debug = 0; 118 #define DPRINTF(x, y) if (mec_debug & (x)) printf y 119 #else 120 #define DPRINTF(x, y) /* nothing */ 121 #endif 122 123 /* #define MEC_EVENT_COUNTERS */ 124 125 #ifdef MEC_EVENT_COUNTERS 126 #define MEC_EVCNT_INCR(ev) (ev)->ev_count++ 127 #else 128 #define MEC_EVCNT_INCR(ev) do {} while (/* CONSTCOND */ 0) 129 #endif 130 131 /* 132 * Transmit descriptor list size 133 */ 134 #define MEC_NTXDESC 64 135 #define MEC_NTXDESC_MASK (MEC_NTXDESC - 1) 136 #define MEC_NEXTTX(x) (((x) + 1) & MEC_NTXDESC_MASK) 137 #define MEC_NTXDESC_RSVD 4 138 #define MEC_NTXDESC_INTR 8 139 140 /* 141 * software state for TX 142 */ 143 struct mec_txsoft { 144 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 145 bus_dmamap_t txs_dmamap; /* our DMA map */ 146 uint32_t txs_flags; 147 #define MEC_TXS_BUFLEN_MASK 0x0000007f /* data len in txd_buf */ 148 #define MEC_TXS_TXDPTR 0x00000080 /* concat txd_ptr is used */ 149 }; 150 151 /* 152 * Transmit buffer descriptor 153 */ 154 #define MEC_TXDESCSIZE 128 155 #define MEC_NTXPTR 3 156 #define MEC_TXD_BUFOFFSET sizeof(uint64_t) 157 #define MEC_TXD_BUFOFFSET1 \ 158 (sizeof(uint64_t) + sizeof(uint64_t) * MEC_NTXPTR) 159 #define MEC_TXD_BUFSIZE (MEC_TXDESCSIZE - MEC_TXD_BUFOFFSET) 160 #define MEC_TXD_BUFSIZE1 (MEC_TXDESCSIZE - MEC_TXD_BUFOFFSET1) 161 #define MEC_TXD_BUFSTART(len) (MEC_TXD_BUFSIZE - (len)) 162 #define MEC_TXD_ALIGN 8 163 #define MEC_TXD_ALIGNMASK (MEC_TXD_ALIGN - 1) 164 #define MEC_TXD_ROUNDUP(addr) \ 165 (((addr) + MEC_TXD_ALIGNMASK) & ~(uint64_t)MEC_TXD_ALIGNMASK) 166 #define MEC_NTXSEG 16 167 168 struct mec_txdesc { 169 volatile uint64_t txd_cmd; 170 #define MEC_TXCMD_DATALEN 0x000000000000ffff /* data length */ 171 #define MEC_TXCMD_BUFSTART 0x00000000007f0000 /* start byte offset */ 172 #define TXCMD_BUFSTART(x) ((x) << 16) 173 #define MEC_TXCMD_TERMDMA 0x0000000000800000 /* stop DMA on abort */ 174 #define MEC_TXCMD_TXINT 0x0000000001000000 /* INT after TX done */ 175 #define MEC_TXCMD_PTR1 0x0000000002000000 /* valid 1st txd_ptr */ 176 #define MEC_TXCMD_PTR2 0x0000000004000000 /* valid 2nd txd_ptr */ 177 #define MEC_TXCMD_PTR3 0x0000000008000000 /* valid 3rd txd_ptr */ 178 #define MEC_TXCMD_UNUSED 0xfffffffff0000000ULL /* should be zero */ 179 180 #define txd_stat txd_cmd 181 #define MEC_TXSTAT_LEN 0x000000000000ffff /* TX length */ 182 #define MEC_TXSTAT_COLCNT 0x00000000000f0000 /* collision count */ 183 #define MEC_TXSTAT_COLCNT_SHIFT 16 184 #define MEC_TXSTAT_LATE_COL 0x0000000000100000 /* late collision */ 185 #define MEC_TXSTAT_CRCERROR 0x0000000000200000 /* */ 186 #define MEC_TXSTAT_DEFERRED 0x0000000000400000 /* */ 187 #define MEC_TXSTAT_SUCCESS 0x0000000000800000 /* TX complete */ 188 #define MEC_TXSTAT_TOOBIG 0x0000000001000000 /* */ 189 #define MEC_TXSTAT_UNDERRUN 0x0000000002000000 /* */ 190 #define MEC_TXSTAT_COLLISIONS 0x0000000004000000 /* */ 191 #define MEC_TXSTAT_EXDEFERRAL 0x0000000008000000 /* */ 192 #define MEC_TXSTAT_COLLIDED 0x0000000010000000 /* */ 193 #define MEC_TXSTAT_UNUSED 0x7fffffffe0000000ULL /* should be zero */ 194 #define MEC_TXSTAT_SENT 0x8000000000000000ULL /* packet sent */ 195 196 union { 197 uint64_t txptr[MEC_NTXPTR]; 198 #define MEC_TXPTR_UNUSED2 0x0000000000000007 /* should be zero */ 199 #define MEC_TXPTR_DMAADDR 0x00000000fffffff8 /* TX DMA address */ 200 #define MEC_TXPTR_LEN 0x0000ffff00000000ULL /* buffer length */ 201 #define TXPTR_LEN(x) ((uint64_t)(x) << 32) 202 #define MEC_TXPTR_UNUSED1 0xffff000000000000ULL /* should be zero */ 203 204 uint8_t txbuf[MEC_TXD_BUFSIZE]; 205 } txd_data; 206 #define txd_ptr txd_data.txptr 207 #define txd_buf txd_data.txbuf 208 }; 209 210 /* 211 * Receive buffer size 212 */ 213 #define MEC_NRXDESC 16 214 #define MEC_NRXDESC_MASK (MEC_NRXDESC - 1) 215 #define MEC_NEXTRX(x) (((x) + 1) & MEC_NRXDESC_MASK) 216 217 /* 218 * Receive buffer description 219 */ 220 #define MEC_RXDESCSIZE 4096 /* umm, should be 4kbyte aligned */ 221 #define MEC_RXD_NRXPAD 3 222 #define MEC_RXD_DMAOFFSET (1 + MEC_RXD_NRXPAD) 223 #define MEC_RXD_BUFOFFSET (MEC_RXD_DMAOFFSET * sizeof(uint64_t)) 224 #define MEC_RXD_BUFSIZE (MEC_RXDESCSIZE - MEC_RXD_BUFOFFSET) 225 226 struct mec_rxdesc { 227 volatile uint64_t rxd_stat; 228 #define MEC_RXSTAT_LEN 0x000000000000ffff /* data length */ 229 #define MEC_RXSTAT_VIOLATION 0x0000000000010000 /* code violation (?) */ 230 #define MEC_RXSTAT_UNUSED2 0x0000000000020000 /* unknown (?) */ 231 #define MEC_RXSTAT_CRCERROR 0x0000000000040000 /* CRC error */ 232 #define MEC_RXSTAT_MULTICAST 0x0000000000080000 /* multicast packet */ 233 #define MEC_RXSTAT_BROADCAST 0x0000000000100000 /* broadcast packet */ 234 #define MEC_RXSTAT_INVALID 0x0000000000200000 /* invalid preamble */ 235 #define MEC_RXSTAT_LONGEVENT 0x0000000000400000 /* long packet */ 236 #define MEC_RXSTAT_BADPACKET 0x0000000000800000 /* bad packet */ 237 #define MEC_RXSTAT_CAREVENT 0x0000000001000000 /* carrier event */ 238 #define MEC_RXSTAT_MATCHMCAST 0x0000000002000000 /* match multicast */ 239 #define MEC_RXSTAT_MATCHMAC 0x0000000004000000 /* match MAC */ 240 #define MEC_RXSTAT_SEQNUM 0x00000000f8000000 /* sequence number */ 241 #define MEC_RXSTAT_CKSUM 0x0000ffff00000000ULL /* IP checksum */ 242 #define RXSTAT_CKSUM(x) (((uint64_t)(x) & MEC_RXSTAT_CKSUM) >> 32) 243 #define MEC_RXSTAT_UNUSED1 0x7fff000000000000ULL /* should be zero */ 244 #define MEC_RXSTAT_RECEIVED 0x8000000000000000ULL /* set to 1 on RX */ 245 uint64_t rxd_pad1[MEC_RXD_NRXPAD]; 246 uint8_t rxd_buf[MEC_RXD_BUFSIZE]; 247 }; 248 249 /* 250 * control structures for DMA ops 251 */ 252 struct mec_control_data { 253 /* 254 * TX descriptors and buffers 255 */ 256 struct mec_txdesc mcd_txdesc[MEC_NTXDESC]; 257 258 /* 259 * RX descriptors and buffers 260 */ 261 struct mec_rxdesc mcd_rxdesc[MEC_NRXDESC]; 262 }; 263 264 /* 265 * It _seems_ there are some restrictions on descriptor address: 266 * 267 * - Base address of txdescs should be 8kbyte aligned 268 * - Each txdesc should be 128byte aligned 269 * - Each rxdesc should be 4kbyte aligned 270 * 271 * So we should specify 8k align to allocalte txdescs. 272 * In this case, sizeof(struct mec_txdesc) * MEC_NTXDESC is 8192 273 * so rxdescs are also allocated at 4kbyte aligned. 274 */ 275 #define MEC_CONTROL_DATA_ALIGN (8 * 1024) 276 277 #define MEC_CDOFF(x) offsetof(struct mec_control_data, x) 278 #define MEC_CDTXOFF(x) MEC_CDOFF(mcd_txdesc[(x)]) 279 #define MEC_CDRXOFF(x) MEC_CDOFF(mcd_rxdesc[(x)]) 280 281 /* 282 * software state per device 283 */ 284 struct mec_softc { 285 device_t sc_dev; /* generic device structures */ 286 287 bus_space_tag_t sc_st; /* bus_space tag */ 288 bus_space_handle_t sc_sh; /* bus_space handle */ 289 bus_dma_tag_t sc_dmat; /* bus_dma tag */ 290 291 struct ethercom sc_ethercom; /* Ethernet common part */ 292 293 struct mii_data sc_mii; /* MII/media information */ 294 int sc_phyaddr; /* MII address */ 295 struct callout sc_tick_ch; /* tick callout */ 296 297 uint8_t sc_enaddr[ETHER_ADDR_LEN]; /* MAC address */ 298 299 bus_dmamap_t sc_cddmamap; /* bus_dma map for control data */ 300 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 301 302 /* pointer to allocated control data */ 303 struct mec_control_data *sc_control_data; 304 #define sc_txdesc sc_control_data->mcd_txdesc 305 #define sc_rxdesc sc_control_data->mcd_rxdesc 306 307 /* software state for TX descs */ 308 struct mec_txsoft sc_txsoft[MEC_NTXDESC]; 309 310 int sc_txpending; /* number of TX requests pending */ 311 int sc_txdirty; /* first dirty TX descriptor */ 312 int sc_txlast; /* last used TX descriptor */ 313 314 int sc_rxptr; /* next ready RX buffer */ 315 316 krndsource_t sc_rnd_source; /* random source */ 317 #ifdef MEC_EVENT_COUNTERS 318 struct evcnt sc_ev_txpkts; /* TX packets queued total */ 319 struct evcnt sc_ev_txdpad; /* TX packets padded in txdesc buf */ 320 struct evcnt sc_ev_txdbuf; /* TX packets copied to txdesc buf */ 321 struct evcnt sc_ev_txptr1; /* TX packets using concat ptr1 */ 322 struct evcnt sc_ev_txptr1a; /* TX packets w/ptr1 ~160bytes */ 323 struct evcnt sc_ev_txptr1b; /* TX packets w/ptr1 ~256bytes */ 324 struct evcnt sc_ev_txptr1c; /* TX packets w/ptr1 ~512bytes */ 325 struct evcnt sc_ev_txptr1d; /* TX packets w/ptr1 ~1024bytes */ 326 struct evcnt sc_ev_txptr1e; /* TX packets w/ptr1 >1024bytes */ 327 struct evcnt sc_ev_txptr2; /* TX packets using concat ptr1,2 */ 328 struct evcnt sc_ev_txptr2a; /* TX packets w/ptr2 ~160bytes */ 329 struct evcnt sc_ev_txptr2b; /* TX packets w/ptr2 ~256bytes */ 330 struct evcnt sc_ev_txptr2c; /* TX packets w/ptr2 ~512bytes */ 331 struct evcnt sc_ev_txptr2d; /* TX packets w/ptr2 ~1024bytes */ 332 struct evcnt sc_ev_txptr2e; /* TX packets w/ptr2 >1024bytes */ 333 struct evcnt sc_ev_txptr3; /* TX packets using concat ptr1,2,3 */ 334 struct evcnt sc_ev_txptr3a; /* TX packets w/ptr3 ~160bytes */ 335 struct evcnt sc_ev_txptr3b; /* TX packets w/ptr3 ~256bytes */ 336 struct evcnt sc_ev_txptr3c; /* TX packets w/ptr3 ~512bytes */ 337 struct evcnt sc_ev_txptr3d; /* TX packets w/ptr3 ~1024bytes */ 338 struct evcnt sc_ev_txptr3e; /* TX packets w/ptr3 >1024bytes */ 339 struct evcnt sc_ev_txmbuf; /* TX packets copied to new mbufs */ 340 struct evcnt sc_ev_txmbufa; /* TX packets w/mbuf ~160bytes */ 341 struct evcnt sc_ev_txmbufb; /* TX packets w/mbuf ~256bytes */ 342 struct evcnt sc_ev_txmbufc; /* TX packets w/mbuf ~512bytes */ 343 struct evcnt sc_ev_txmbufd; /* TX packets w/mbuf ~1024bytes */ 344 struct evcnt sc_ev_txmbufe; /* TX packets w/mbuf >1024bytes */ 345 struct evcnt sc_ev_txptrs; /* TX packets using ptrs total */ 346 struct evcnt sc_ev_txptrc0; /* TX packets w/ptrs no hdr chain */ 347 struct evcnt sc_ev_txptrc1; /* TX packets w/ptrs 1 hdr chain */ 348 struct evcnt sc_ev_txptrc2; /* TX packets w/ptrs 2 hdr chains */ 349 struct evcnt sc_ev_txptrc3; /* TX packets w/ptrs 3 hdr chains */ 350 struct evcnt sc_ev_txptrc4; /* TX packets w/ptrs 4 hdr chains */ 351 struct evcnt sc_ev_txptrc5; /* TX packets w/ptrs 5 hdr chains */ 352 struct evcnt sc_ev_txptrc6; /* TX packets w/ptrs >5 hdr chains */ 353 struct evcnt sc_ev_txptrh0; /* TX packets w/ptrs ~8bytes hdr */ 354 struct evcnt sc_ev_txptrh1; /* TX packets w/ptrs ~16bytes hdr */ 355 struct evcnt sc_ev_txptrh2; /* TX packets w/ptrs ~32bytes hdr */ 356 struct evcnt sc_ev_txptrh3; /* TX packets w/ptrs ~64bytes hdr */ 357 struct evcnt sc_ev_txptrh4; /* TX packets w/ptrs ~80bytes hdr */ 358 struct evcnt sc_ev_txptrh5; /* TX packets w/ptrs ~96bytes hdr */ 359 struct evcnt sc_ev_txdstall; /* TX stalled due to no txdesc */ 360 struct evcnt sc_ev_txempty; /* TX empty interrupts */ 361 struct evcnt sc_ev_txsent; /* TX sent interrupts */ 362 #endif 363 }; 364 365 #define MEC_CDTXADDR(sc, x) ((sc)->sc_cddma + MEC_CDTXOFF(x)) 366 #define MEC_CDRXADDR(sc, x) ((sc)->sc_cddma + MEC_CDRXOFF(x)) 367 368 #define MEC_TXDESCSYNC(sc, x, ops) \ 369 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 370 MEC_CDTXOFF(x), MEC_TXDESCSIZE, (ops)) 371 #define MEC_TXCMDSYNC(sc, x, ops) \ 372 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 373 MEC_CDTXOFF(x), sizeof(uint64_t), (ops)) 374 375 #define MEC_RXSTATSYNC(sc, x, ops) \ 376 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 377 MEC_CDRXOFF(x), sizeof(uint64_t), (ops)) 378 #define MEC_RXBUFSYNC(sc, x, len, ops) \ 379 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 380 MEC_CDRXOFF(x) + MEC_RXD_BUFOFFSET, \ 381 MEC_ETHER_ALIGN + (len), (ops)) 382 383 /* XXX these values should be moved to <net/if_ether.h> ? */ 384 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 385 #define MEC_ETHER_ALIGN 2 386 387 static int mec_match(device_t, cfdata_t, void *); 388 static void mec_attach(device_t, device_t, void *); 389 390 static int mec_mii_readreg(device_t, int, int, uint16_t *); 391 static int mec_mii_writereg(device_t, int, int, uint16_t); 392 static int mec_mii_wait(struct mec_softc *); 393 static void mec_statchg(struct ifnet *); 394 395 static int mec_init(struct ifnet * ifp); 396 static void mec_start(struct ifnet *); 397 static void mec_watchdog(struct ifnet *); 398 static void mec_tick(void *); 399 static int mec_ioctl(struct ifnet *, u_long, void *); 400 static void mec_reset(struct mec_softc *); 401 static void mec_setfilter(struct mec_softc *); 402 static int mec_intr(void *arg); 403 static void mec_stop(struct ifnet *, int); 404 static void mec_rxintr(struct mec_softc *); 405 static void mec_rxcsum(struct mec_softc *, struct mbuf *, uint16_t, 406 uint32_t); 407 static void mec_txintr(struct mec_softc *, uint32_t); 408 static bool mec_shutdown(device_t, int); 409 410 CFATTACH_DECL_NEW(mec, sizeof(struct mec_softc), 411 mec_match, mec_attach, NULL, NULL); 412 413 static int mec_matched = 0; 414 415 static int 416 mec_match(device_t parent, cfdata_t cf, void *aux) 417 { 418 419 /* allow only one device */ 420 if (mec_matched) 421 return 0; 422 423 mec_matched = 1; 424 return 1; 425 } 426 427 static void 428 mec_attach(device_t parent, device_t self, void *aux) 429 { 430 struct mec_softc *sc = device_private(self); 431 struct mace_attach_args *maa = aux; 432 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 433 uint64_t address, command; 434 const char *macaddr; 435 struct mii_softc *child; 436 bus_dma_segment_t seg; 437 int i, err, rseg; 438 bool mac_is_fake; 439 440 sc->sc_dev = self; 441 sc->sc_st = maa->maa_st; 442 if (bus_space_subregion(sc->sc_st, maa->maa_sh, 443 maa->maa_offset, 0, &sc->sc_sh) != 0) { 444 aprint_error(": can't map i/o space\n"); 445 return; 446 } 447 448 /* set up DMA structures */ 449 sc->sc_dmat = maa->maa_dmat; 450 451 /* 452 * Allocate the control data structures, and create and load the 453 * DMA map for it. 454 */ 455 if ((err = bus_dmamem_alloc(sc->sc_dmat, 456 sizeof(struct mec_control_data), MEC_CONTROL_DATA_ALIGN, 0, 457 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 458 aprint_error(": unable to allocate control data, error = %d\n", 459 err); 460 goto fail_0; 461 } 462 /* 463 * XXX needs re-think... 464 * control data structures contain whole RX data buffer, so 465 * BUS_DMA_COHERENT (which disables cache) may cause some performance 466 * issue on copying data from the RX buffer to mbuf on normal memory, 467 * though we have to make sure all bus_dmamap_sync(9) ops are called 468 * properly in that case. 469 */ 470 if ((err = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 471 sizeof(struct mec_control_data), 472 (void **)&sc->sc_control_data, /*BUS_DMA_COHERENT*/ 0)) != 0) { 473 aprint_error(": unable to map control data, error = %d\n", err); 474 goto fail_1; 475 } 476 memset(sc->sc_control_data, 0, sizeof(struct mec_control_data)); 477 478 if ((err = bus_dmamap_create(sc->sc_dmat, 479 sizeof(struct mec_control_data), 1, 480 sizeof(struct mec_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 481 aprint_error(": unable to create control data DMA map," 482 " error = %d\n", err); 483 goto fail_2; 484 } 485 if ((err = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 486 sc->sc_control_data, sizeof(struct mec_control_data), NULL, 487 BUS_DMA_NOWAIT)) != 0) { 488 aprint_error(": unable to load control data DMA map," 489 " error = %d\n", err); 490 goto fail_3; 491 } 492 493 /* create TX buffer DMA maps */ 494 for (i = 0; i < MEC_NTXDESC; i++) { 495 if ((err = bus_dmamap_create(sc->sc_dmat, 496 MCLBYTES, MEC_NTXSEG, MCLBYTES, PAGE_SIZE, 0, 497 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 498 aprint_error(": unable to create tx DMA map %d," 499 " error = %d\n", i, err); 500 goto fail_4; 501 } 502 } 503 504 callout_init(&sc->sc_tick_ch, 0); 505 506 /* get Ethernet address from ARCBIOS */ 507 if ((macaddr = arcbios_GetEnvironmentVariable("eaddr")) == NULL) { 508 aprint_error(": unable to get MAC address!\n"); 509 goto fail_4; 510 } 511 /* 512 * On some machines the DS2502 chip storing the serial number/ 513 * mac address is on the pci riser board - if this board is 514 * missing, ARCBIOS will not know a good ethernet address (but 515 * otherwise the machine will work fine). 516 */ 517 mac_is_fake = false; 518 if (strcmp(macaddr, "ff:ff:ff:ff:ff:ff") == 0) { 519 uint32_t ui = 0; 520 const char * netaddr = 521 arcbios_GetEnvironmentVariable("netaddr"); 522 523 /* 524 * Create a MAC address by abusing the "netaddr" env var 525 */ 526 sc->sc_enaddr[0] = 0xf2; 527 sc->sc_enaddr[1] = 0x0b; 528 sc->sc_enaddr[2] = 0xa4; 529 if (netaddr) { 530 mac_is_fake = true; 531 while (*netaddr) { 532 int v = 0; 533 while (*netaddr && *netaddr != '.') { 534 if (*netaddr >= '0' && *netaddr <= '9') 535 v = v*10 + (*netaddr - '0'); 536 netaddr++; 537 } 538 ui <<= 8; 539 ui |= v; 540 if (*netaddr == '.') 541 netaddr++; 542 } 543 } 544 memcpy(sc->sc_enaddr+3, ((uint8_t *)&ui)+1, 3); 545 } 546 if (!mac_is_fake) 547 ether_aton_r(sc->sc_enaddr, sizeof(sc->sc_enaddr), macaddr); 548 549 /* set the Ethernet address */ 550 address = 0; 551 for (i = 0; i < ETHER_ADDR_LEN; i++) { 552 address = address << 8; 553 address |= sc->sc_enaddr[i]; 554 } 555 bus_space_write_8(sc->sc_st, sc->sc_sh, MEC_STATION, address); 556 557 /* reset device */ 558 mec_reset(sc); 559 560 command = bus_space_read_8(sc->sc_st, sc->sc_sh, MEC_MAC_CONTROL); 561 562 aprint_normal(": MAC-110 Ethernet, rev %u\n", 563 (u_int)((command & MEC_MAC_REVISION) >> MEC_MAC_REVISION_SHIFT)); 564 565 if (mac_is_fake) 566 aprint_normal_dev(self, 567 "could not get ethernet address from firmware" 568 " - generated one from the \"netaddr\" environment" 569 " variable\n"); 570 aprint_normal_dev(self, "Ethernet address %s\n", 571 ether_sprintf(sc->sc_enaddr)); 572 573 /* Done, now attach everything */ 574 575 sc->sc_mii.mii_ifp = ifp; 576 sc->sc_mii.mii_readreg = mec_mii_readreg; 577 sc->sc_mii.mii_writereg = mec_mii_writereg; 578 sc->sc_mii.mii_statchg = mec_statchg; 579 580 /* Set up PHY properties */ 581 sc->sc_ethercom.ec_mii = &sc->sc_mii; 582 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 583 ether_mediastatus); 584 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 585 MII_OFFSET_ANY, 0); 586 587 child = LIST_FIRST(&sc->sc_mii.mii_phys); 588 if (child == NULL) { 589 /* No PHY attached */ 590 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL, 591 0, NULL); 592 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL); 593 } else { 594 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 595 sc->sc_phyaddr = child->mii_phy; 596 } 597 598 strcpy(ifp->if_xname, device_xname(self)); 599 ifp->if_softc = sc; 600 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 601 ifp->if_ioctl = mec_ioctl; 602 ifp->if_start = mec_start; 603 ifp->if_watchdog = mec_watchdog; 604 ifp->if_init = mec_init; 605 ifp->if_stop = mec_stop; 606 ifp->if_mtu = ETHERMTU; 607 IFQ_SET_READY(&ifp->if_snd); 608 609 /* mec has dumb RX cksum support */ 610 ifp->if_capabilities = IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx; 611 612 /* We can support 802.1Q VLAN-sized frames. */ 613 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 614 615 /* attach the interface */ 616 if_attach(ifp); 617 if_deferred_start_init(ifp, NULL); 618 ether_ifattach(ifp, sc->sc_enaddr); 619 620 /* establish interrupt */ 621 cpu_intr_establish(maa->maa_intr, maa->maa_intrmask, mec_intr, sc); 622 623 rnd_attach_source(&sc->sc_rnd_source, device_xname(self), 624 RND_TYPE_NET, RND_FLAG_DEFAULT); 625 626 #ifdef MEC_EVENT_COUNTERS 627 evcnt_attach_dynamic(&sc->sc_ev_txpkts , EVCNT_TYPE_MISC, 628 NULL, device_xname(self), "TX pkts queued total"); 629 evcnt_attach_dynamic(&sc->sc_ev_txdpad , EVCNT_TYPE_MISC, 630 NULL, device_xname(self), "TX pkts padded in txdesc buf"); 631 evcnt_attach_dynamic(&sc->sc_ev_txdbuf , EVCNT_TYPE_MISC, 632 NULL, device_xname(self), "TX pkts copied to txdesc buf"); 633 evcnt_attach_dynamic(&sc->sc_ev_txptr1 , EVCNT_TYPE_MISC, 634 NULL, device_xname(self), "TX pkts using concat ptr1"); 635 evcnt_attach_dynamic(&sc->sc_ev_txptr1a , EVCNT_TYPE_MISC, 636 NULL, device_xname(self), "TX pkts w/ptr1 ~160bytes"); 637 evcnt_attach_dynamic(&sc->sc_ev_txptr1b , EVCNT_TYPE_MISC, 638 NULL, device_xname(self), "TX pkts w/ptr1 ~256bytes"); 639 evcnt_attach_dynamic(&sc->sc_ev_txptr1c , EVCNT_TYPE_MISC, 640 NULL, device_xname(self), "TX pkts w/ptr1 ~512bytes"); 641 evcnt_attach_dynamic(&sc->sc_ev_txptr1d , EVCNT_TYPE_MISC, 642 NULL, device_xname(self), "TX pkts w/ptr1 ~1024bytes"); 643 evcnt_attach_dynamic(&sc->sc_ev_txptr1e , EVCNT_TYPE_MISC, 644 NULL, device_xname(self), "TX pkts w/ptr1 >1024bytes"); 645 evcnt_attach_dynamic(&sc->sc_ev_txptr2 , EVCNT_TYPE_MISC, 646 NULL, device_xname(self), "TX pkts using concat ptr1,2"); 647 evcnt_attach_dynamic(&sc->sc_ev_txptr2a , EVCNT_TYPE_MISC, 648 NULL, device_xname(self), "TX pkts w/ptr2 ~160bytes"); 649 evcnt_attach_dynamic(&sc->sc_ev_txptr2b , EVCNT_TYPE_MISC, 650 NULL, device_xname(self), "TX pkts w/ptr2 ~256bytes"); 651 evcnt_attach_dynamic(&sc->sc_ev_txptr2c , EVCNT_TYPE_MISC, 652 NULL, device_xname(self), "TX pkts w/ptr2 ~512bytes"); 653 evcnt_attach_dynamic(&sc->sc_ev_txptr2d , EVCNT_TYPE_MISC, 654 NULL, device_xname(self), "TX pkts w/ptr2 ~1024bytes"); 655 evcnt_attach_dynamic(&sc->sc_ev_txptr2e , EVCNT_TYPE_MISC, 656 NULL, device_xname(self), "TX pkts w/ptr2 >1024bytes"); 657 evcnt_attach_dynamic(&sc->sc_ev_txptr3 , EVCNT_TYPE_MISC, 658 NULL, device_xname(self), "TX pkts using concat ptr1,2,3"); 659 evcnt_attach_dynamic(&sc->sc_ev_txptr3a , EVCNT_TYPE_MISC, 660 NULL, device_xname(self), "TX pkts w/ptr3 ~160bytes"); 661 evcnt_attach_dynamic(&sc->sc_ev_txptr3b , EVCNT_TYPE_MISC, 662 NULL, device_xname(self), "TX pkts w/ptr3 ~256bytes"); 663 evcnt_attach_dynamic(&sc->sc_ev_txptr3c , EVCNT_TYPE_MISC, 664 NULL, device_xname(self), "TX pkts w/ptr3 ~512bytes"); 665 evcnt_attach_dynamic(&sc->sc_ev_txptr3d , EVCNT_TYPE_MISC, 666 NULL, device_xname(self), "TX pkts w/ptr3 ~1024bytes"); 667 evcnt_attach_dynamic(&sc->sc_ev_txptr3e , EVCNT_TYPE_MISC, 668 NULL, device_xname(self), "TX pkts w/ptr3 >1024bytes"); 669 evcnt_attach_dynamic(&sc->sc_ev_txmbuf , EVCNT_TYPE_MISC, 670 NULL, device_xname(self), "TX pkts copied to new mbufs"); 671 evcnt_attach_dynamic(&sc->sc_ev_txmbufa , EVCNT_TYPE_MISC, 672 NULL, device_xname(self), "TX pkts w/mbuf ~160bytes"); 673 evcnt_attach_dynamic(&sc->sc_ev_txmbufb , EVCNT_TYPE_MISC, 674 NULL, device_xname(self), "TX pkts w/mbuf ~256bytes"); 675 evcnt_attach_dynamic(&sc->sc_ev_txmbufc , EVCNT_TYPE_MISC, 676 NULL, device_xname(self), "TX pkts w/mbuf ~512bytes"); 677 evcnt_attach_dynamic(&sc->sc_ev_txmbufd , EVCNT_TYPE_MISC, 678 NULL, device_xname(self), "TX pkts w/mbuf ~1024bytes"); 679 evcnt_attach_dynamic(&sc->sc_ev_txmbufe , EVCNT_TYPE_MISC, 680 NULL, device_xname(self), "TX pkts w/mbuf >1024bytes"); 681 evcnt_attach_dynamic(&sc->sc_ev_txptrs , EVCNT_TYPE_MISC, 682 NULL, device_xname(self), "TX pkts using ptrs total"); 683 evcnt_attach_dynamic(&sc->sc_ev_txptrc0 , EVCNT_TYPE_MISC, 684 NULL, device_xname(self), "TX pkts w/ptrs no hdr chain"); 685 evcnt_attach_dynamic(&sc->sc_ev_txptrc1 , EVCNT_TYPE_MISC, 686 NULL, device_xname(self), "TX pkts w/ptrs 1 hdr chain"); 687 evcnt_attach_dynamic(&sc->sc_ev_txptrc2 , EVCNT_TYPE_MISC, 688 NULL, device_xname(self), "TX pkts w/ptrs 2 hdr chains"); 689 evcnt_attach_dynamic(&sc->sc_ev_txptrc3 , EVCNT_TYPE_MISC, 690 NULL, device_xname(self), "TX pkts w/ptrs 3 hdr chains"); 691 evcnt_attach_dynamic(&sc->sc_ev_txptrc4 , EVCNT_TYPE_MISC, 692 NULL, device_xname(self), "TX pkts w/ptrs 4 hdr chains"); 693 evcnt_attach_dynamic(&sc->sc_ev_txptrc5 , EVCNT_TYPE_MISC, 694 NULL, device_xname(self), "TX pkts w/ptrs 5 hdr chains"); 695 evcnt_attach_dynamic(&sc->sc_ev_txptrc6 , EVCNT_TYPE_MISC, 696 NULL, device_xname(self), "TX pkts w/ptrs >5 hdr chains"); 697 evcnt_attach_dynamic(&sc->sc_ev_txptrh0 , EVCNT_TYPE_MISC, 698 NULL, device_xname(self), "TX pkts w/ptrs ~8bytes hdr"); 699 evcnt_attach_dynamic(&sc->sc_ev_txptrh1 , EVCNT_TYPE_MISC, 700 NULL, device_xname(self), "TX pkts w/ptrs ~16bytes hdr"); 701 evcnt_attach_dynamic(&sc->sc_ev_txptrh2 , EVCNT_TYPE_MISC, 702 NULL, device_xname(self), "TX pkts w/ptrs ~32bytes hdr"); 703 evcnt_attach_dynamic(&sc->sc_ev_txptrh3 , EVCNT_TYPE_MISC, 704 NULL, device_xname(self), "TX pkts w/ptrs ~64bytes hdr"); 705 evcnt_attach_dynamic(&sc->sc_ev_txptrh4 , EVCNT_TYPE_MISC, 706 NULL, device_xname(self), "TX pkts w/ptrs ~80bytes hdr"); 707 evcnt_attach_dynamic(&sc->sc_ev_txptrh5 , EVCNT_TYPE_MISC, 708 NULL, device_xname(self), "TX pkts w/ptrs ~96bytes hdr"); 709 evcnt_attach_dynamic(&sc->sc_ev_txdstall , EVCNT_TYPE_MISC, 710 NULL, device_xname(self), "TX stalled due to no txdesc"); 711 evcnt_attach_dynamic(&sc->sc_ev_txempty , EVCNT_TYPE_MISC, 712 NULL, device_xname(self), "TX empty interrupts"); 713 evcnt_attach_dynamic(&sc->sc_ev_txsent , EVCNT_TYPE_MISC, 714 NULL, device_xname(self), "TX sent interrupts"); 715 #endif 716 717 /* set shutdown hook to reset interface on powerdown */ 718 if (pmf_device_register1(self, NULL, NULL, mec_shutdown)) 719 pmf_class_network_register(self, ifp); 720 else 721 aprint_error_dev(self, "couldn't establish power handler\n"); 722 723 return; 724 725 /* 726 * Free any resources we've allocated during the failed attach 727 * attempt. Do this in reverse order and fall though. 728 */ 729 fail_4: 730 for (i = 0; i < MEC_NTXDESC; i++) { 731 if (sc->sc_txsoft[i].txs_dmamap != NULL) 732 bus_dmamap_destroy(sc->sc_dmat, 733 sc->sc_txsoft[i].txs_dmamap); 734 } 735 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 736 fail_3: 737 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 738 fail_2: 739 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 740 sizeof(struct mec_control_data)); 741 fail_1: 742 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 743 fail_0: 744 return; 745 } 746 747 static int 748 mec_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 749 { 750 struct mec_softc *sc = device_private(self); 751 bus_space_tag_t st = sc->sc_st; 752 bus_space_handle_t sh = sc->sc_sh; 753 uint64_t data; 754 int i, rv; 755 756 if ((rv = mec_mii_wait(sc)) != 0) 757 return rv; 758 759 bus_space_write_8(st, sh, MEC_PHY_ADDRESS, 760 (phy << MEC_PHY_ADDR_DEVSHIFT) | (reg & MEC_PHY_ADDR_REGISTER)); 761 delay(25); 762 bus_space_write_8(st, sh, MEC_PHY_READ_INITIATE, 1); 763 delay(25); 764 mec_mii_wait(sc); 765 766 for (i = 0; i < 20; i++) { 767 delay(30); 768 769 data = bus_space_read_8(st, sh, MEC_PHY_DATA); 770 771 if ((data & MEC_PHY_DATA_BUSY) == 0) { 772 *val = data & MEC_PHY_DATA_VALUE; 773 return 0; 774 } 775 } 776 return -1; 777 } 778 779 static int 780 mec_mii_writereg(device_t self, int phy, int reg, uint16_t val) 781 { 782 struct mec_softc *sc = device_private(self); 783 bus_space_tag_t st = sc->sc_st; 784 bus_space_handle_t sh = sc->sc_sh; 785 int rv; 786 787 if ((rv = mec_mii_wait(sc)) != 0) { 788 printf("timed out writing %x: %hx\n", reg, val); 789 return rv; 790 } 791 792 bus_space_write_8(st, sh, MEC_PHY_ADDRESS, 793 (phy << MEC_PHY_ADDR_DEVSHIFT) | (reg & MEC_PHY_ADDR_REGISTER)); 794 795 delay(60); 796 797 bus_space_write_8(st, sh, MEC_PHY_DATA, val & MEC_PHY_DATA_VALUE); 798 799 delay(60); 800 801 mec_mii_wait(sc); 802 803 return 0; 804 } 805 806 static int 807 mec_mii_wait(struct mec_softc *sc) 808 { 809 uint32_t busy; 810 int i, s; 811 812 for (i = 0; i < 100; i++) { 813 delay(30); 814 815 s = splhigh(); 816 busy = bus_space_read_8(sc->sc_st, sc->sc_sh, MEC_PHY_DATA); 817 splx(s); 818 819 if ((busy & MEC_PHY_DATA_BUSY) == 0) 820 return 0; 821 #if 0 822 if (busy == 0xffff) /* XXX ? */ 823 return 0; 824 #endif 825 } 826 827 printf("%s: MII timed out\n", device_xname(sc->sc_dev)); 828 return ETIMEDOUT; 829 } 830 831 static void 832 mec_statchg(struct ifnet *ifp) 833 { 834 struct mec_softc *sc = ifp->if_softc; 835 bus_space_tag_t st = sc->sc_st; 836 bus_space_handle_t sh = sc->sc_sh; 837 uint32_t control; 838 839 control = bus_space_read_8(st, sh, MEC_MAC_CONTROL); 840 control &= ~(MEC_MAC_IPGT | MEC_MAC_IPGR1 | MEC_MAC_IPGR2 | 841 MEC_MAC_FULL_DUPLEX | MEC_MAC_SPEED_SELECT); 842 843 /* must also set IPG here for duplex stuff ... */ 844 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) { 845 control |= MEC_MAC_FULL_DUPLEX; 846 } else { 847 /* set IPG */ 848 control |= MEC_MAC_IPG_DEFAULT; 849 } 850 851 bus_space_write_8(st, sh, MEC_MAC_CONTROL, control); 852 } 853 854 static int 855 mec_init(struct ifnet *ifp) 856 { 857 struct mec_softc *sc = ifp->if_softc; 858 bus_space_tag_t st = sc->sc_st; 859 bus_space_handle_t sh = sc->sc_sh; 860 struct mec_rxdesc *rxd; 861 int i, rc; 862 863 /* cancel any pending I/O */ 864 mec_stop(ifp, 0); 865 866 /* reset device */ 867 mec_reset(sc); 868 869 /* setup filter for multicast or promisc mode */ 870 mec_setfilter(sc); 871 872 /* set the TX ring pointer to the base address */ 873 bus_space_write_8(st, sh, MEC_TX_RING_BASE, MEC_CDTXADDR(sc, 0)); 874 875 sc->sc_txpending = 0; 876 sc->sc_txdirty = 0; 877 sc->sc_txlast = MEC_NTXDESC - 1; 878 879 /* put RX buffers into FIFO */ 880 for (i = 0; i < MEC_NRXDESC; i++) { 881 rxd = &sc->sc_rxdesc[i]; 882 rxd->rxd_stat = 0; 883 MEC_RXSTATSYNC(sc, i, BUS_DMASYNC_PREREAD); 884 MEC_RXBUFSYNC(sc, i, ETHER_MAX_LEN, BUS_DMASYNC_PREREAD); 885 bus_space_write_8(st, sh, MEC_MCL_RX_FIFO, MEC_CDRXADDR(sc, i)); 886 } 887 sc->sc_rxptr = 0; 888 889 #if 0 /* XXX no info */ 890 bus_space_write_8(st, sh, MEC_TIMER, 0); 891 #endif 892 893 /* 894 * MEC_DMA_TX_INT_ENABLE will be set later otherwise it causes 895 * spurious interrupts when TX buffers are empty 896 */ 897 bus_space_write_8(st, sh, MEC_DMA_CONTROL, 898 (MEC_RXD_DMAOFFSET << MEC_DMA_RX_DMA_OFFSET_SHIFT) | 899 (MEC_NRXDESC << MEC_DMA_RX_INT_THRESH_SHIFT) | 900 MEC_DMA_TX_DMA_ENABLE | /* MEC_DMA_TX_INT_ENABLE | */ 901 MEC_DMA_RX_DMA_ENABLE | MEC_DMA_RX_INT_ENABLE); 902 903 callout_reset(&sc->sc_tick_ch, hz, mec_tick, sc); 904 905 if ((rc = ether_mediachange(ifp)) != 0) 906 return rc; 907 908 ifp->if_flags |= IFF_RUNNING; 909 ifp->if_flags &= ~IFF_OACTIVE; 910 mec_start(ifp); 911 912 return 0; 913 } 914 915 static void 916 mec_reset(struct mec_softc *sc) 917 { 918 bus_space_tag_t st = sc->sc_st; 919 bus_space_handle_t sh = sc->sc_sh; 920 uint64_t control; 921 922 /* stop DMA first */ 923 bus_space_write_8(st, sh, MEC_DMA_CONTROL, 0); 924 925 /* reset chip */ 926 bus_space_write_8(st, sh, MEC_MAC_CONTROL, MEC_MAC_CORE_RESET); 927 delay(1000); 928 bus_space_write_8(st, sh, MEC_MAC_CONTROL, 0); 929 delay(1000); 930 931 /* Default to 100/half and let auto-negotiation work its magic */ 932 control = MEC_MAC_SPEED_SELECT | MEC_MAC_FILTER_MATCHMULTI | 933 MEC_MAC_IPG_DEFAULT; 934 935 bus_space_write_8(st, sh, MEC_MAC_CONTROL, control); 936 /* stop DMA again for sanity */ 937 bus_space_write_8(st, sh, MEC_DMA_CONTROL, 0); 938 939 DPRINTF(MEC_DEBUG_RESET, ("mec: control now %llx\n", 940 bus_space_read_8(st, sh, MEC_MAC_CONTROL))); 941 } 942 943 static void 944 mec_start(struct ifnet *ifp) 945 { 946 struct mec_softc *sc = ifp->if_softc; 947 struct mbuf *m0, *m; 948 struct mec_txdesc *txd; 949 struct mec_txsoft *txs; 950 bus_dmamap_t dmamap; 951 bus_space_tag_t st = sc->sc_st; 952 bus_space_handle_t sh = sc->sc_sh; 953 int error, firsttx, nexttx, opending; 954 int len, bufoff, buflen, nsegs, align, resid, pseg, nptr, slen, i; 955 uint32_t txdcmd; 956 957 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 958 return; 959 960 /* 961 * Remember the previous txpending and the first transmit descriptor. 962 */ 963 opending = sc->sc_txpending; 964 firsttx = MEC_NEXTTX(sc->sc_txlast); 965 966 DPRINTF(MEC_DEBUG_START, 967 ("%s: opending = %d, firsttx = %d\n", __func__, opending, firsttx)); 968 969 while (sc->sc_txpending < MEC_NTXDESC - 1) { 970 /* Grab a packet off the queue. */ 971 IFQ_POLL(&ifp->if_snd, m0); 972 if (m0 == NULL) 973 break; 974 m = NULL; 975 976 /* 977 * Get the next available transmit descriptor. 978 */ 979 nexttx = MEC_NEXTTX(sc->sc_txlast); 980 txd = &sc->sc_txdesc[nexttx]; 981 txs = &sc->sc_txsoft[nexttx]; 982 dmamap = txs->txs_dmamap; 983 txs->txs_flags = 0; 984 985 buflen = 0; 986 bufoff = 0; 987 resid = 0; 988 nptr = 0; /* XXX gcc */ 989 pseg = 0; /* XXX gcc */ 990 991 len = m0->m_pkthdr.len; 992 993 DPRINTF(MEC_DEBUG_START, 994 ("%s: len = %d, nexttx = %d, txpending = %d\n", 995 __func__, len, nexttx, sc->sc_txpending)); 996 997 if (len <= MEC_TXD_BUFSIZE) { 998 /* 999 * If a TX packet will fit into small txdesc buffer, 1000 * just copy it into there. Maybe it's faster than 1001 * checking alignment and calling bus_dma(9) etc. 1002 */ 1003 DPRINTF(MEC_DEBUG_START, ("%s: short packet\n", 1004 __func__)); 1005 IFQ_DEQUEUE(&ifp->if_snd, m0); 1006 1007 /* 1008 * I don't know if MEC chip does auto padding, 1009 * but do it manually for safety. 1010 */ 1011 if (len < ETHER_PAD_LEN) { 1012 MEC_EVCNT_INCR(&sc->sc_ev_txdpad); 1013 bufoff = MEC_TXD_BUFSTART(ETHER_PAD_LEN); 1014 m_copydata(m0, 0, len, txd->txd_buf + bufoff); 1015 memset(txd->txd_buf + bufoff + len, 0, 1016 ETHER_PAD_LEN - len); 1017 len = buflen = ETHER_PAD_LEN; 1018 } else { 1019 MEC_EVCNT_INCR(&sc->sc_ev_txdbuf); 1020 bufoff = MEC_TXD_BUFSTART(len); 1021 m_copydata(m0, 0, len, txd->txd_buf + bufoff); 1022 buflen = len; 1023 } 1024 } else { 1025 /* 1026 * If the packet won't fit the static buffer in txdesc, 1027 * we have to use the concatenate pointers to handle it. 1028 */ 1029 DPRINTF(MEC_DEBUG_START, ("%s: long packet\n", 1030 __func__)); 1031 txs->txs_flags = MEC_TXS_TXDPTR; 1032 1033 /* 1034 * Call bus_dmamap_load_mbuf(9) first to see 1035 * how many chains the TX mbuf has. 1036 */ 1037 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1038 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1039 if (error == 0) { 1040 /* 1041 * Check chains which might contain headers. 1042 * They might be so much fragmented and 1043 * it's better to copy them into txdesc buffer 1044 * since they would be small enough. 1045 */ 1046 nsegs = dmamap->dm_nsegs; 1047 for (pseg = 0; pseg < nsegs; pseg++) { 1048 slen = dmamap->dm_segs[pseg].ds_len; 1049 if (buflen + slen > 1050 MEC_TXD_BUFSIZE1 - MEC_TXD_ALIGN) 1051 break; 1052 buflen += slen; 1053 } 1054 /* 1055 * Check if the rest chains can be fit into 1056 * the concatinate pointers. 1057 */ 1058 align = dmamap->dm_segs[pseg].ds_addr & 1059 MEC_TXD_ALIGNMASK; 1060 if (align > 0) { 1061 /* 1062 * If the first chain isn't uint64_t 1063 * aligned, append the unaligned part 1064 * into txdesc buffer too. 1065 */ 1066 resid = MEC_TXD_ALIGN - align; 1067 buflen += resid; 1068 for (; pseg < nsegs; pseg++) { 1069 slen = 1070 dmamap->dm_segs[pseg].ds_len; 1071 if (slen > resid) 1072 break; 1073 resid -= slen; 1074 } 1075 } else if (pseg == 0) { 1076 /* 1077 * In this case, the first chain is 1078 * uint64_t aligned but it's too long 1079 * to put into txdesc buf. 1080 * We have to put some data into 1081 * txdesc buf even in this case, 1082 * so put MEC_TXD_ALIGN bytes there. 1083 */ 1084 buflen = resid = MEC_TXD_ALIGN; 1085 } 1086 nptr = nsegs - pseg; 1087 if (nptr <= MEC_NTXPTR) { 1088 bufoff = MEC_TXD_BUFSTART(buflen); 1089 1090 /* 1091 * Check if all the rest chains are 1092 * uint64_t aligned. 1093 */ 1094 align = 0; 1095 for (i = pseg + 1; i < nsegs; i++) 1096 align |= 1097 dmamap->dm_segs[i].ds_addr 1098 & MEC_TXD_ALIGNMASK; 1099 if (align != 0) { 1100 /* chains are not aligned */ 1101 error = -1; 1102 } 1103 } else { 1104 /* The TX mbuf chains doesn't fit. */ 1105 error = -1; 1106 } 1107 if (error == -1) 1108 bus_dmamap_unload(sc->sc_dmat, dmamap); 1109 } 1110 if (error != 0) { 1111 /* 1112 * The TX mbuf chains can't be put into 1113 * the concatinate buffers. In this case, 1114 * we have to allocate a new contiguous mbuf 1115 * and copy data into it. 1116 * 1117 * Even in this case, the Ethernet header in 1118 * the TX mbuf might be unaligned and trailing 1119 * data might be word aligned, so put 2 byte 1120 * (MEC_ETHER_ALIGN) padding at the top of the 1121 * allocated mbuf and copy TX packets. 1122 * 6 bytes (MEC_ALIGN_BYTES - MEC_ETHER_ALIGN) 1123 * at the top of the new mbuf won't be uint64_t 1124 * alignd, but we have to put some data into 1125 * txdesc buffer anyway even if the buffer 1126 * is uint64_t aligned. 1127 */ 1128 DPRINTF(MEC_DEBUG_START|MEC_DEBUG_TXSEGS, 1129 ("%s: re-allocating mbuf\n", __func__)); 1130 1131 MGETHDR(m, M_DONTWAIT, MT_DATA); 1132 if (m == NULL) { 1133 printf("%s: unable to allocate " 1134 "TX mbuf\n", 1135 device_xname(sc->sc_dev)); 1136 break; 1137 } 1138 if (len > (MHLEN - MEC_ETHER_ALIGN)) { 1139 MCLGET(m, M_DONTWAIT); 1140 if ((m->m_flags & M_EXT) == 0) { 1141 printf("%s: unable to allocate " 1142 "TX cluster\n", 1143 device_xname(sc->sc_dev)); 1144 m_freem(m); 1145 break; 1146 } 1147 } 1148 m->m_data += MEC_ETHER_ALIGN; 1149 1150 /* 1151 * Copy whole data (including unaligned part) 1152 * for following bpf_mtap(). 1153 */ 1154 m_copydata(m0, 0, len, mtod(m, void *)); 1155 m->m_pkthdr.len = m->m_len = len; 1156 error = bus_dmamap_load_mbuf(sc->sc_dmat, 1157 dmamap, m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1158 if (dmamap->dm_nsegs > 1) { 1159 /* should not happen, but for sanity */ 1160 bus_dmamap_unload(sc->sc_dmat, dmamap); 1161 error = -1; 1162 } 1163 if (error != 0) { 1164 printf("%s: unable to load TX buffer, " 1165 "error = %d\n", 1166 device_xname(sc->sc_dev), error); 1167 m_freem(m); 1168 break; 1169 } 1170 /* 1171 * Only the first segment should be put into 1172 * the concatinate pointer in this case. 1173 */ 1174 pseg = 0; 1175 nptr = 1; 1176 1177 /* 1178 * Set lenght of unaligned part which will be 1179 * copied into txdesc buffer. 1180 */ 1181 buflen = MEC_TXD_ALIGN - MEC_ETHER_ALIGN; 1182 bufoff = MEC_TXD_BUFSTART(buflen); 1183 resid = buflen; 1184 #ifdef MEC_EVENT_COUNTERS 1185 MEC_EVCNT_INCR(&sc->sc_ev_txmbuf); 1186 if (len <= 160) 1187 MEC_EVCNT_INCR(&sc->sc_ev_txmbufa); 1188 else if (len <= 256) 1189 MEC_EVCNT_INCR(&sc->sc_ev_txmbufb); 1190 else if (len <= 512) 1191 MEC_EVCNT_INCR(&sc->sc_ev_txmbufc); 1192 else if (len <= 1024) 1193 MEC_EVCNT_INCR(&sc->sc_ev_txmbufd); 1194 else 1195 MEC_EVCNT_INCR(&sc->sc_ev_txmbufe); 1196 #endif 1197 } 1198 #ifdef MEC_EVENT_COUNTERS 1199 else { 1200 MEC_EVCNT_INCR(&sc->sc_ev_txptrs); 1201 if (nptr == 1) { 1202 MEC_EVCNT_INCR(&sc->sc_ev_txptr1); 1203 if (len <= 160) 1204 MEC_EVCNT_INCR( 1205 &sc->sc_ev_txptr1a); 1206 else if (len <= 256) 1207 MEC_EVCNT_INCR( 1208 &sc->sc_ev_txptr1b); 1209 else if (len <= 512) 1210 MEC_EVCNT_INCR( 1211 &sc->sc_ev_txptr1c); 1212 else if (len <= 1024) 1213 MEC_EVCNT_INCR( 1214 &sc->sc_ev_txptr1d); 1215 else 1216 MEC_EVCNT_INCR( 1217 &sc->sc_ev_txptr1e); 1218 } else if (nptr == 2) { 1219 MEC_EVCNT_INCR(&sc->sc_ev_txptr2); 1220 if (len <= 160) 1221 MEC_EVCNT_INCR( 1222 &sc->sc_ev_txptr2a); 1223 else if (len <= 256) 1224 MEC_EVCNT_INCR( 1225 &sc->sc_ev_txptr2b); 1226 else if (len <= 512) 1227 MEC_EVCNT_INCR( 1228 &sc->sc_ev_txptr2c); 1229 else if (len <= 1024) 1230 MEC_EVCNT_INCR( 1231 &sc->sc_ev_txptr2d); 1232 else 1233 MEC_EVCNT_INCR( 1234 &sc->sc_ev_txptr2e); 1235 } else if (nptr == 3) { 1236 MEC_EVCNT_INCR(&sc->sc_ev_txptr3); 1237 if (len <= 160) 1238 MEC_EVCNT_INCR( 1239 &sc->sc_ev_txptr3a); 1240 else if (len <= 256) 1241 MEC_EVCNT_INCR( 1242 &sc->sc_ev_txptr3b); 1243 else if (len <= 512) 1244 MEC_EVCNT_INCR( 1245 &sc->sc_ev_txptr3c); 1246 else if (len <= 1024) 1247 MEC_EVCNT_INCR( 1248 &sc->sc_ev_txptr3d); 1249 else 1250 MEC_EVCNT_INCR( 1251 &sc->sc_ev_txptr3e); 1252 } 1253 if (pseg == 0) 1254 MEC_EVCNT_INCR(&sc->sc_ev_txptrc0); 1255 else if (pseg == 1) 1256 MEC_EVCNT_INCR(&sc->sc_ev_txptrc1); 1257 else if (pseg == 2) 1258 MEC_EVCNT_INCR(&sc->sc_ev_txptrc2); 1259 else if (pseg == 3) 1260 MEC_EVCNT_INCR(&sc->sc_ev_txptrc3); 1261 else if (pseg == 4) 1262 MEC_EVCNT_INCR(&sc->sc_ev_txptrc4); 1263 else if (pseg == 5) 1264 MEC_EVCNT_INCR(&sc->sc_ev_txptrc5); 1265 else 1266 MEC_EVCNT_INCR(&sc->sc_ev_txptrc6); 1267 if (buflen <= 8) 1268 MEC_EVCNT_INCR(&sc->sc_ev_txptrh0); 1269 else if (buflen <= 16) 1270 MEC_EVCNT_INCR(&sc->sc_ev_txptrh1); 1271 else if (buflen <= 32) 1272 MEC_EVCNT_INCR(&sc->sc_ev_txptrh2); 1273 else if (buflen <= 64) 1274 MEC_EVCNT_INCR(&sc->sc_ev_txptrh3); 1275 else if (buflen <= 80) 1276 MEC_EVCNT_INCR(&sc->sc_ev_txptrh4); 1277 else 1278 MEC_EVCNT_INCR(&sc->sc_ev_txptrh5); 1279 } 1280 #endif 1281 m_copydata(m0, 0, buflen, txd->txd_buf + bufoff); 1282 1283 IFQ_DEQUEUE(&ifp->if_snd, m0); 1284 if (m != NULL) { 1285 m_freem(m0); 1286 m0 = m; 1287 } 1288 1289 /* 1290 * sync the DMA map for TX mbuf 1291 */ 1292 bus_dmamap_sync(sc->sc_dmat, dmamap, buflen, 1293 len - buflen, BUS_DMASYNC_PREWRITE); 1294 } 1295 1296 /* 1297 * Pass packet to bpf if there is a listener. 1298 */ 1299 bpf_mtap(ifp, m0, BPF_D_OUT); 1300 MEC_EVCNT_INCR(&sc->sc_ev_txpkts); 1301 1302 /* 1303 * setup the transmit descriptor. 1304 */ 1305 txdcmd = TXCMD_BUFSTART(MEC_TXDESCSIZE - buflen) | (len - 1); 1306 1307 /* 1308 * Set MEC_TXCMD_TXINT every MEC_NTXDESC_INTR packets 1309 * if more than half txdescs have been queued 1310 * because TX_EMPTY interrupts will rarely happen 1311 * if TX queue is so stacked. 1312 */ 1313 if (sc->sc_txpending > (MEC_NTXDESC / 2) && 1314 (nexttx & (MEC_NTXDESC_INTR - 1)) == 0) 1315 txdcmd |= MEC_TXCMD_TXINT; 1316 1317 if ((txs->txs_flags & MEC_TXS_TXDPTR) != 0) { 1318 bus_dma_segment_t *segs = dmamap->dm_segs; 1319 1320 DPRINTF(MEC_DEBUG_TXSEGS, 1321 ("%s: nsegs = %d, pseg = %d, nptr = %d\n", 1322 __func__, dmamap->dm_nsegs, pseg, nptr)); 1323 1324 switch (nptr) { 1325 case 3: 1326 KASSERT((segs[pseg + 2].ds_addr & 1327 MEC_TXD_ALIGNMASK) == 0); 1328 txdcmd |= MEC_TXCMD_PTR3; 1329 txd->txd_ptr[2] = 1330 TXPTR_LEN(segs[pseg + 2].ds_len - 1) | 1331 segs[pseg + 2].ds_addr; 1332 /* FALLTHROUGH */ 1333 case 2: 1334 KASSERT((segs[pseg + 1].ds_addr & 1335 MEC_TXD_ALIGNMASK) == 0); 1336 txdcmd |= MEC_TXCMD_PTR2; 1337 txd->txd_ptr[1] = 1338 TXPTR_LEN(segs[pseg + 1].ds_len - 1) | 1339 segs[pseg + 1].ds_addr; 1340 /* FALLTHROUGH */ 1341 case 1: 1342 txdcmd |= MEC_TXCMD_PTR1; 1343 txd->txd_ptr[0] = 1344 TXPTR_LEN(segs[pseg].ds_len - resid - 1) | 1345 (segs[pseg].ds_addr + resid); 1346 break; 1347 default: 1348 panic("%s: impossible nptr in %s", 1349 device_xname(sc->sc_dev), __func__); 1350 /* NOTREACHED */ 1351 } 1352 /* 1353 * Store a pointer to the packet so we can 1354 * free it later. 1355 */ 1356 txs->txs_mbuf = m0; 1357 } else { 1358 /* 1359 * In this case all data are copied to buffer in txdesc, 1360 * we can free TX mbuf here. 1361 */ 1362 m_freem(m0); 1363 } 1364 txd->txd_cmd = txdcmd; 1365 1366 DPRINTF(MEC_DEBUG_START, 1367 ("%s: txd_cmd = 0x%016llx\n", 1368 __func__, txd->txd_cmd)); 1369 DPRINTF(MEC_DEBUG_START, 1370 ("%s: txd_ptr[0] = 0x%016llx\n", 1371 __func__, txd->txd_ptr[0])); 1372 DPRINTF(MEC_DEBUG_START, 1373 ("%s: txd_ptr[1] = 0x%016llx\n", 1374 __func__, txd->txd_ptr[1])); 1375 DPRINTF(MEC_DEBUG_START, 1376 ("%s: txd_ptr[2] = 0x%016llx\n", 1377 __func__, txd->txd_ptr[2])); 1378 DPRINTF(MEC_DEBUG_START, 1379 ("%s: len = %d (0x%04x), buflen = %d (0x%02x)\n", 1380 __func__, len, len, buflen, buflen)); 1381 1382 /* sync TX descriptor */ 1383 MEC_TXDESCSYNC(sc, nexttx, 1384 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1385 1386 /* start TX */ 1387 bus_space_write_8(st, sh, MEC_TX_RING_PTR, MEC_NEXTTX(nexttx)); 1388 1389 /* advance the TX pointer. */ 1390 sc->sc_txpending++; 1391 sc->sc_txlast = nexttx; 1392 } 1393 1394 if (sc->sc_txpending == MEC_NTXDESC - 1) { 1395 /* No more slots; notify upper layer. */ 1396 MEC_EVCNT_INCR(&sc->sc_ev_txdstall); 1397 ifp->if_flags |= IFF_OACTIVE; 1398 } 1399 1400 if (sc->sc_txpending != opending) { 1401 /* 1402 * If the transmitter was idle, 1403 * reset the txdirty pointer and re-enable TX interrupt. 1404 */ 1405 if (opending == 0) { 1406 sc->sc_txdirty = firsttx; 1407 bus_space_write_8(st, sh, MEC_TX_ALIAS, 1408 MEC_TX_ALIAS_INT_ENABLE); 1409 } 1410 1411 /* Set a watchdog timer in case the chip flakes out. */ 1412 ifp->if_timer = 5; 1413 } 1414 } 1415 1416 static void 1417 mec_stop(struct ifnet *ifp, int disable) 1418 { 1419 struct mec_softc *sc = ifp->if_softc; 1420 struct mec_txsoft *txs; 1421 int i; 1422 1423 DPRINTF(MEC_DEBUG_STOP, ("%s\n", __func__)); 1424 1425 ifp->if_timer = 0; 1426 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1427 1428 callout_stop(&sc->sc_tick_ch); 1429 mii_down(&sc->sc_mii); 1430 1431 /* release any TX buffers */ 1432 for (i = 0; i < MEC_NTXDESC; i++) { 1433 txs = &sc->sc_txsoft[i]; 1434 if ((txs->txs_flags & MEC_TXS_TXDPTR) != 0) { 1435 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1436 m_freem(txs->txs_mbuf); 1437 txs->txs_mbuf = NULL; 1438 } 1439 } 1440 } 1441 1442 static int 1443 mec_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1444 { 1445 int s, error; 1446 1447 s = splnet(); 1448 1449 error = ether_ioctl(ifp, cmd, data); 1450 if (error == ENETRESET) { 1451 /* 1452 * Multicast list has changed; set the hardware filter 1453 * accordingly. 1454 */ 1455 if (ifp->if_flags & IFF_RUNNING) 1456 error = mec_init(ifp); 1457 else 1458 error = 0; 1459 } 1460 1461 /* Try to get more packets going. */ 1462 mec_start(ifp); 1463 1464 splx(s); 1465 return error; 1466 } 1467 1468 static void 1469 mec_watchdog(struct ifnet *ifp) 1470 { 1471 struct mec_softc *sc = ifp->if_softc; 1472 1473 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 1474 ifp->if_oerrors++; 1475 1476 mec_init(ifp); 1477 } 1478 1479 static void 1480 mec_tick(void *arg) 1481 { 1482 struct mec_softc *sc = arg; 1483 int s; 1484 1485 s = splnet(); 1486 mii_tick(&sc->sc_mii); 1487 splx(s); 1488 1489 callout_reset(&sc->sc_tick_ch, hz, mec_tick, sc); 1490 } 1491 1492 static void 1493 mec_setfilter(struct mec_softc *sc) 1494 { 1495 struct ethercom *ec = &sc->sc_ethercom; 1496 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1497 struct ether_multi *enm; 1498 struct ether_multistep step; 1499 bus_space_tag_t st = sc->sc_st; 1500 bus_space_handle_t sh = sc->sc_sh; 1501 uint64_t mchash; 1502 uint32_t control, hash; 1503 int mcnt; 1504 1505 control = bus_space_read_8(st, sh, MEC_MAC_CONTROL); 1506 control &= ~MEC_MAC_FILTER_MASK; 1507 1508 if (ifp->if_flags & IFF_PROMISC) { 1509 control |= MEC_MAC_FILTER_PROMISC; 1510 bus_space_write_8(st, sh, MEC_MULTICAST, 0xffffffffffffffffULL); 1511 bus_space_write_8(st, sh, MEC_MAC_CONTROL, control); 1512 return; 1513 } 1514 1515 mcnt = 0; 1516 mchash = 0; 1517 ETHER_FIRST_MULTI(step, ec, enm); 1518 while (enm != NULL) { 1519 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1520 /* set allmulti for a range of multicast addresses */ 1521 control |= MEC_MAC_FILTER_ALLMULTI; 1522 bus_space_write_8(st, sh, MEC_MULTICAST, 1523 0xffffffffffffffffULL); 1524 bus_space_write_8(st, sh, MEC_MAC_CONTROL, control); 1525 return; 1526 } 1527 1528 #define mec_calchash(addr) (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26) 1529 1530 hash = mec_calchash(enm->enm_addrlo); 1531 mchash |= 1 << hash; 1532 mcnt++; 1533 ETHER_NEXT_MULTI(step, enm); 1534 } 1535 1536 ifp->if_flags &= ~IFF_ALLMULTI; 1537 1538 if (mcnt > 0) 1539 control |= MEC_MAC_FILTER_MATCHMULTI; 1540 1541 bus_space_write_8(st, sh, MEC_MULTICAST, mchash); 1542 bus_space_write_8(st, sh, MEC_MAC_CONTROL, control); 1543 } 1544 1545 static int 1546 mec_intr(void *arg) 1547 { 1548 struct mec_softc *sc = arg; 1549 bus_space_tag_t st = sc->sc_st; 1550 bus_space_handle_t sh = sc->sc_sh; 1551 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1552 uint32_t statreg, statack, txptr; 1553 int handled, sent; 1554 1555 DPRINTF(MEC_DEBUG_INTR, ("%s: called\n", __func__)); 1556 1557 handled = sent = 0; 1558 1559 for (;;) { 1560 statreg = bus_space_read_8(st, sh, MEC_INT_STATUS); 1561 1562 DPRINTF(MEC_DEBUG_INTR, 1563 ("%s: INT_STAT = 0x%08x\n", __func__, statreg)); 1564 1565 statack = statreg & MEC_INT_STATUS_MASK; 1566 if (statack == 0) 1567 break; 1568 bus_space_write_8(st, sh, MEC_INT_STATUS, statack); 1569 1570 handled = 1; 1571 1572 if (statack & 1573 (MEC_INT_RX_THRESHOLD | 1574 MEC_INT_RX_FIFO_UNDERFLOW)) { 1575 mec_rxintr(sc); 1576 } 1577 1578 if (statack & 1579 (MEC_INT_TX_EMPTY | 1580 MEC_INT_TX_PACKET_SENT | 1581 MEC_INT_TX_ABORT)) { 1582 txptr = (statreg & MEC_INT_TX_RING_BUFFER_ALIAS) 1583 >> MEC_INT_TX_RING_BUFFER_SHIFT; 1584 mec_txintr(sc, txptr); 1585 sent = 1; 1586 if ((statack & MEC_INT_TX_EMPTY) != 0) { 1587 /* 1588 * disable TX interrupt to stop 1589 * TX empty interrupt 1590 */ 1591 bus_space_write_8(st, sh, MEC_TX_ALIAS, 0); 1592 DPRINTF(MEC_DEBUG_INTR, 1593 ("%s: disable TX_INT\n", __func__)); 1594 } 1595 #ifdef MEC_EVENT_COUNTERS 1596 if ((statack & MEC_INT_TX_EMPTY) != 0) 1597 MEC_EVCNT_INCR(&sc->sc_ev_txempty); 1598 if ((statack & MEC_INT_TX_PACKET_SENT) != 0) 1599 MEC_EVCNT_INCR(&sc->sc_ev_txsent); 1600 #endif 1601 } 1602 1603 if (statack & 1604 (MEC_INT_TX_LINK_FAIL | 1605 MEC_INT_TX_MEM_ERROR | 1606 MEC_INT_TX_ABORT | 1607 MEC_INT_RX_DMA_UNDERFLOW)) { 1608 printf("%s: %s: interrupt status = 0x%08x\n", 1609 device_xname(sc->sc_dev), __func__, statreg); 1610 mec_init(ifp); 1611 break; 1612 } 1613 } 1614 1615 if (sent) { 1616 /* try to get more packets going */ 1617 if_schedule_deferred_start(ifp); 1618 } 1619 1620 if (handled) 1621 rnd_add_uint32(&sc->sc_rnd_source, statreg); 1622 1623 return handled; 1624 } 1625 1626 static void 1627 mec_rxintr(struct mec_softc *sc) 1628 { 1629 bus_space_tag_t st = sc->sc_st; 1630 bus_space_handle_t sh = sc->sc_sh; 1631 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1632 struct mbuf *m; 1633 struct mec_rxdesc *rxd; 1634 uint64_t rxstat; 1635 u_int len; 1636 int i; 1637 uint32_t crc; 1638 1639 DPRINTF(MEC_DEBUG_RXINTR, ("%s: called\n", __func__)); 1640 1641 for (i = sc->sc_rxptr;; i = MEC_NEXTRX(i)) { 1642 rxd = &sc->sc_rxdesc[i]; 1643 1644 MEC_RXSTATSYNC(sc, i, BUS_DMASYNC_POSTREAD); 1645 rxstat = rxd->rxd_stat; 1646 1647 DPRINTF(MEC_DEBUG_RXINTR, 1648 ("%s: rxstat = 0x%016llx, rxptr = %d\n", 1649 __func__, rxstat, i)); 1650 DPRINTF(MEC_DEBUG_RXINTR, ("%s: rxfifo = 0x%08x\n", 1651 __func__, (u_int)bus_space_read_8(st, sh, MEC_RX_FIFO))); 1652 1653 if ((rxstat & MEC_RXSTAT_RECEIVED) == 0) { 1654 MEC_RXSTATSYNC(sc, i, BUS_DMASYNC_PREREAD); 1655 break; 1656 } 1657 1658 len = rxstat & MEC_RXSTAT_LEN; 1659 1660 if (len < ETHER_MIN_LEN || 1661 len > (MCLBYTES - MEC_ETHER_ALIGN)) { 1662 /* invalid length packet; drop it. */ 1663 DPRINTF(MEC_DEBUG_RXINTR, 1664 ("%s: wrong packet\n", __func__)); 1665 dropit: 1666 ifp->if_ierrors++; 1667 rxd->rxd_stat = 0; 1668 MEC_RXSTATSYNC(sc, i, BUS_DMASYNC_PREREAD); 1669 bus_space_write_8(st, sh, MEC_MCL_RX_FIFO, 1670 MEC_CDRXADDR(sc, i)); 1671 continue; 1672 } 1673 1674 /* 1675 * If 802.1Q VLAN MTU is enabled, ignore the bad packet error. 1676 */ 1677 if ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) != 0) 1678 rxstat &= ~MEC_RXSTAT_BADPACKET; 1679 1680 if (rxstat & 1681 (MEC_RXSTAT_BADPACKET | 1682 MEC_RXSTAT_LONGEVENT | 1683 MEC_RXSTAT_INVALID | 1684 MEC_RXSTAT_CRCERROR | 1685 MEC_RXSTAT_VIOLATION)) { 1686 printf("%s: mec_rxintr: status = 0x%016"PRIx64"\n", 1687 device_xname(sc->sc_dev), rxstat); 1688 goto dropit; 1689 } 1690 1691 /* 1692 * The MEC includes the CRC with every packet. Trim 1693 * it off here. 1694 */ 1695 len -= ETHER_CRC_LEN; 1696 1697 /* 1698 * now allocate an mbuf (and possibly a cluster) to hold 1699 * the received packet. 1700 */ 1701 MGETHDR(m, M_DONTWAIT, MT_DATA); 1702 if (m == NULL) { 1703 printf("%s: unable to allocate RX mbuf\n", 1704 device_xname(sc->sc_dev)); 1705 goto dropit; 1706 } 1707 if (len > (MHLEN - MEC_ETHER_ALIGN)) { 1708 MCLGET(m, M_DONTWAIT); 1709 if ((m->m_flags & M_EXT) == 0) { 1710 printf("%s: unable to allocate RX cluster\n", 1711 device_xname(sc->sc_dev)); 1712 m_freem(m); 1713 m = NULL; 1714 goto dropit; 1715 } 1716 } 1717 1718 /* 1719 * Note MEC chip seems to insert 2 byte padding at the top of 1720 * RX buffer, but we copy whole buffer to avoid unaligned copy. 1721 */ 1722 MEC_RXBUFSYNC(sc, i, len + ETHER_CRC_LEN, BUS_DMASYNC_POSTREAD); 1723 memcpy(mtod(m, void *), rxd->rxd_buf, MEC_ETHER_ALIGN + len); 1724 crc = be32dec(rxd->rxd_buf + MEC_ETHER_ALIGN + len); 1725 MEC_RXBUFSYNC(sc, i, ETHER_MAX_LEN, BUS_DMASYNC_PREREAD); 1726 m->m_data += MEC_ETHER_ALIGN; 1727 1728 /* put RX buffer into FIFO again */ 1729 rxd->rxd_stat = 0; 1730 MEC_RXSTATSYNC(sc, i, BUS_DMASYNC_PREREAD); 1731 bus_space_write_8(st, sh, MEC_MCL_RX_FIFO, MEC_CDRXADDR(sc, i)); 1732 1733 m_set_rcvif(m, ifp); 1734 m->m_pkthdr.len = m->m_len = len; 1735 if ((ifp->if_csum_flags_rx & (M_CSUM_TCPv4|M_CSUM_UDPv4)) != 0) 1736 mec_rxcsum(sc, m, RXSTAT_CKSUM(rxstat), crc); 1737 1738 /* Pass it on. */ 1739 if_percpuq_enqueue(ifp->if_percpuq, m); 1740 } 1741 1742 /* update RX pointer */ 1743 sc->sc_rxptr = i; 1744 } 1745 1746 static void 1747 mec_rxcsum(struct mec_softc *sc, struct mbuf *m, uint16_t rxcsum, uint32_t crc) 1748 { 1749 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1750 struct ether_header *eh; 1751 struct ip *ip; 1752 struct udphdr *uh; 1753 u_int len, pktlen, hlen; 1754 uint32_t csum_data, dsum; 1755 int csum_flags; 1756 const uint16_t *dp; 1757 1758 csum_data = 0; 1759 csum_flags = 0; 1760 1761 len = m->m_len; 1762 if (len < ETHER_HDR_LEN + sizeof(struct ip)) 1763 goto out; 1764 pktlen = len - ETHER_HDR_LEN; 1765 eh = mtod(m, struct ether_header *); 1766 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 1767 goto out; 1768 ip = (struct ip *)((uint8_t *)eh + ETHER_HDR_LEN); 1769 if (ip->ip_v != IPVERSION) 1770 goto out; 1771 1772 hlen = ip->ip_hl << 2; 1773 if (hlen < sizeof(struct ip)) 1774 goto out; 1775 1776 /* 1777 * Bail if too short, has random trailing garbage, truncated, 1778 * fragment, or has ethernet pad. 1779 */ 1780 if (ntohs(ip->ip_len) < hlen || 1781 ntohs(ip->ip_len) != pktlen || 1782 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK)) != 0) 1783 goto out; 1784 1785 switch (ip->ip_p) { 1786 case IPPROTO_TCP: 1787 if ((ifp->if_csum_flags_rx & M_CSUM_TCPv4) == 0 || 1788 pktlen < (hlen + sizeof(struct tcphdr))) 1789 goto out; 1790 csum_flags = M_CSUM_TCPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 1791 break; 1792 case IPPROTO_UDP: 1793 if ((ifp->if_csum_flags_rx & M_CSUM_UDPv4) == 0 || 1794 pktlen < (hlen + sizeof(struct udphdr))) 1795 goto out; 1796 uh = (struct udphdr *)((uint8_t *)ip + hlen); 1797 if (uh->uh_sum == 0) 1798 goto out; /* no checksum */ 1799 csum_flags = M_CSUM_UDPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 1800 break; 1801 default: 1802 goto out; 1803 } 1804 1805 /* 1806 * The computed checksum includes Ethernet header, IP headers, 1807 * and CRC, so we have to deduct them. 1808 * Note IP header cksum should be 0xffff so we don't have to 1809 * dedecut them. 1810 */ 1811 dsum = 0; 1812 1813 /* deduct Ethernet header */ 1814 dp = (const uint16_t *)eh; 1815 for (hlen = 0; hlen < (ETHER_HDR_LEN / sizeof(uint16_t)); hlen++) 1816 dsum += ntohs(*dp++); 1817 1818 /* deduct CRC */ 1819 if (len & 1) { 1820 dsum += (crc >> 24) & 0x00ff; 1821 dsum += (crc >> 8) & 0xffff; 1822 dsum += (crc << 8) & 0xff00; 1823 } else { 1824 dsum += (crc >> 16) & 0xffff; 1825 dsum += (crc >> 0) & 0xffff; 1826 } 1827 while (dsum >> 16) 1828 dsum = (dsum >> 16) + (dsum & 0xffff); 1829 1830 csum_data = rxcsum; 1831 csum_data += (uint16_t)~dsum; 1832 1833 while (csum_data >> 16) 1834 csum_data = (csum_data >> 16) + (csum_data & 0xffff); 1835 1836 out: 1837 m->m_pkthdr.csum_flags = csum_flags; 1838 m->m_pkthdr.csum_data = csum_data; 1839 } 1840 1841 static void 1842 mec_txintr(struct mec_softc *sc, uint32_t txptr) 1843 { 1844 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1845 struct mec_txdesc *txd; 1846 struct mec_txsoft *txs; 1847 bus_dmamap_t dmamap; 1848 uint64_t txstat; 1849 int i; 1850 u_int col; 1851 1852 DPRINTF(MEC_DEBUG_TXINTR, ("%s: called\n", __func__)); 1853 1854 for (i = sc->sc_txdirty; i != txptr && sc->sc_txpending != 0; 1855 i = MEC_NEXTTX(i), sc->sc_txpending--) { 1856 txd = &sc->sc_txdesc[i]; 1857 1858 MEC_TXCMDSYNC(sc, i, 1859 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1860 1861 txstat = txd->txd_stat; 1862 DPRINTF(MEC_DEBUG_TXINTR, 1863 ("%s: dirty = %d, txstat = 0x%016llx\n", 1864 __func__, i, txstat)); 1865 if ((txstat & MEC_TXSTAT_SENT) == 0) { 1866 MEC_TXCMDSYNC(sc, i, BUS_DMASYNC_PREREAD); 1867 break; 1868 } 1869 1870 txs = &sc->sc_txsoft[i]; 1871 if ((txs->txs_flags & MEC_TXS_TXDPTR) != 0) { 1872 dmamap = txs->txs_dmamap; 1873 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, 1874 dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1875 bus_dmamap_unload(sc->sc_dmat, dmamap); 1876 m_freem(txs->txs_mbuf); 1877 txs->txs_mbuf = NULL; 1878 } 1879 1880 col = (txstat & MEC_TXSTAT_COLCNT) >> MEC_TXSTAT_COLCNT_SHIFT; 1881 ifp->if_collisions += col; 1882 1883 if ((txstat & MEC_TXSTAT_SUCCESS) == 0) { 1884 printf("%s: TX error: txstat = 0x%016"PRIx64"\n", 1885 device_xname(sc->sc_dev), txstat); 1886 ifp->if_oerrors++; 1887 } else 1888 ifp->if_opackets++; 1889 } 1890 1891 /* update the dirty TX buffer pointer */ 1892 sc->sc_txdirty = i; 1893 DPRINTF(MEC_DEBUG_INTR, 1894 ("%s: sc_txdirty = %2d, sc_txpending = %2d\n", 1895 __func__, sc->sc_txdirty, sc->sc_txpending)); 1896 1897 /* cancel the watchdog timer if there are no pending TX packets */ 1898 if (sc->sc_txpending == 0) 1899 ifp->if_timer = 0; 1900 if (sc->sc_txpending < MEC_NTXDESC - MEC_NTXDESC_RSVD) 1901 ifp->if_flags &= ~IFF_OACTIVE; 1902 } 1903 1904 static bool 1905 mec_shutdown(device_t self, int howto) 1906 { 1907 struct mec_softc *sc = device_private(self); 1908 1909 mec_stop(&sc->sc_ethercom.ec_if, 1); 1910 /* make sure to stop DMA etc. */ 1911 mec_reset(sc); 1912 1913 return true; 1914 } 1915
Indexes created Tue Sep 30 11:09:46 GMT 2025