pci_mace.c revision 1.10
1 /* $NetBSD: pci_mace.c,v 1.10 2011/02/20 07:59:51 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2001,2003 Christopher Sekiya 5 * Copyright (c) 2000 Soren S. Jorvang 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed for the 19 * NetBSD Project. See http://www.NetBSD.org/ for 20 * information about NetBSD. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: pci_mace.c,v 1.10 2011/02/20 07:59:51 matt Exp $"); 38 39 #include "opt_pci.h" 40 #include "pci.h" 41 42 #include <sys/param.h> 43 #include <sys/device.h> 44 #include <sys/systm.h> 45 46 #include <machine/cpu.h> 47 #include <machine/locore.h> 48 #include <machine/autoconf.h> 49 #include <machine/vmparam.h> 50 #include <machine/bus.h> 51 #include <machine/machtype.h> 52 53 #include <mips/cache.h> 54 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcidevs.h> 58 59 #include <sys/extent.h> 60 #include <sys/malloc.h> 61 #include <dev/pci/pciconf.h> 62 63 #include <sgimips/mace/macereg.h> 64 #include <sgimips/mace/macevar.h> 65 66 #include <sgimips/mace/pcireg_mace.h> 67 68 struct macepci_softc { 69 struct device sc_dev; 70 71 struct sgimips_pci_chipset sc_pc; 72 }; 73 74 static int macepci_match(struct device *, struct cfdata *, void *); 75 static void macepci_attach(struct device *, struct device *, void *); 76 static int macepci_bus_maxdevs(pci_chipset_tag_t, int); 77 static pcireg_t macepci_conf_read(pci_chipset_tag_t, pcitag_t, int); 78 static void macepci_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 79 static int macepci_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 80 static const char * 81 macepci_intr_string(pci_chipset_tag_t, pci_intr_handle_t); 82 static int macepci_intr(void *); 83 84 CFATTACH_DECL(macepci, sizeof(struct macepci_softc), 85 macepci_match, macepci_attach, NULL, NULL); 86 87 static int 88 macepci_match(struct device *parent, struct cfdata *match, void *aux) 89 { 90 91 return (1); 92 } 93 94 static void 95 macepci_attach(struct device *parent, struct device *self, void *aux) 96 { 97 struct macepci_softc *sc = (struct macepci_softc *)self; 98 pci_chipset_tag_t pc = &sc->sc_pc; 99 struct mace_attach_args *maa = aux; 100 struct pcibus_attach_args pba; 101 u_int32_t control; 102 int rev; 103 104 if (bus_space_subregion(maa->maa_st, maa->maa_sh, 105 maa->maa_offset, 0, &pc->ioh) ) 106 panic("macepci_attach: couldn't map"); 107 108 pc->iot = maa->maa_st; 109 110 rev = bus_space_read_4(pc->iot, pc->ioh, MACEPCI_REVISION); 111 printf(": rev %d\n", rev); 112 113 pc->pc_bus_maxdevs = macepci_bus_maxdevs; 114 pc->pc_conf_read = macepci_conf_read; 115 pc->pc_conf_write = macepci_conf_write; 116 pc->pc_intr_map = macepci_intr_map; 117 pc->pc_intr_string = macepci_intr_string; 118 pc->intr_establish = mace_intr_establish; 119 pc->intr_disestablish = mace_intr_disestablish; 120 121 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_ERROR_ADDR, 0); 122 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_ERROR_FLAGS, 0); 123 124 /* Turn on PCI error interrupts */ 125 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONTROL, 126 MACE_PCI_CONTROL_SERR_ENA | 127 MACE_PCI_CONTROL_PARITY_ERR | 128 MACE_PCI_CONTROL_PARK_LIU | 129 MACE_PCI_CONTROL_OVERRUN_INT | 130 MACE_PCI_CONTROL_PARITY_INT | 131 MACE_PCI_CONTROL_SERR_INT | 132 MACE_PCI_CONTROL_IT_INT | 133 MACE_PCI_CONTROL_RE_INT | 134 MACE_PCI_CONTROL_DPED_INT | 135 MACE_PCI_CONTROL_TAR_INT | 136 MACE_PCI_CONTROL_MAR_INT); 137 138 /* 139 * Enable all MACE PCI interrupts. They will be masked by 140 * the CRIME code. 141 */ 142 control = bus_space_read_4(pc->iot, pc->ioh, MACEPCI_CONTROL); 143 control |= CONTROL_INT_MASK; 144 bus_space_write_4(pc->iot, pc->ioh, MACEPCI_CONTROL, control); 145 146 #if NPCI > 0 147 pc->pc_ioext = extent_create("macepciio", 0x00001000, 0x01ffffff, 148 M_DEVBUF, NULL, 0, EX_NOWAIT); 149 pc->pc_memext = extent_create("macepcimem", 0x80100000, 0x81ffffff, 150 M_DEVBUF, NULL, 0, EX_NOWAIT); 151 pci_configure_bus(pc, pc->pc_ioext, pc->pc_memext, NULL, 0, 152 mips_cache_info.mci_dcache_align); 153 memset(&pba, 0, sizeof pba); 154 /*XXX*/ pba.pba_iot = SGIMIPS_BUS_SPACE_IO; 155 /*XXX*/ pba.pba_memt = SGIMIPS_BUS_SPACE_MEM; 156 pba.pba_dmat = &pci_bus_dma_tag; 157 pba.pba_dmat64 = NULL; 158 pba.pba_bus = 0; 159 pba.pba_bridgetag = NULL; 160 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 161 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 162 pba.pba_pc = pc; 163 164 #ifdef MACEPCI_IO_WAS_BUGGY 165 if (rev == 0) 166 pba.pba_flags &= ~PCI_FLAGS_IO_ENABLED; /* Buggy? */ 167 #endif 168 169 cpu_intr_establish(maa->maa_intr, IPL_NONE, macepci_intr, sc); 170 171 config_found_ia(self, "pcibus", &pba, pcibusprint); 172 #endif 173 } 174 175 int 176 macepci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 177 { 178 179 if (busno == 0) 180 return 5; /* 2 on-board SCSI chips, slots 0, 1 and 2 */ 181 else 182 return 0; /* XXX */ 183 } 184 185 pcireg_t 186 macepci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 187 { 188 pcireg_t data; 189 190 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, (tag | reg)); 191 data = bus_space_read_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_DATA); 192 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, 0); 193 194 return data; 195 } 196 197 void 198 macepci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 199 { 200 /* XXX O2 soren */ 201 if (tag == 0) 202 return; 203 204 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, (tag | reg)); 205 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_DATA, data); 206 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, 0); 207 } 208 209 int 210 macepci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 211 { 212 pci_chipset_tag_t pc = pa->pa_pc; 213 pcitag_t intrtag = pa->pa_intrtag; 214 int pin = pa->pa_intrpin; 215 int bus, dev, func, start; 216 217 pci_decompose_tag(pc, intrtag, &bus, &dev, &func); 218 219 if (dev < 3 && pin != PCI_INTERRUPT_PIN_A) 220 panic("SCSI0 and SCSI1 must be hardwired!"); 221 222 switch (pin) { 223 default: 224 case PCI_INTERRUPT_PIN_NONE: 225 return -1; 226 227 case PCI_INTERRUPT_PIN_A: 228 /* 229 * Each of SCSI{0,1}, & slots 0 - 2 has dedicated interrupt 230 * for pin A? 231 */ 232 *ihp = dev + 7; 233 return 0; 234 235 case PCI_INTERRUPT_PIN_B: 236 start = 0; 237 break; 238 case PCI_INTERRUPT_PIN_C: 239 start = 1; 240 break; 241 case PCI_INTERRUPT_PIN_D: 242 start = 2; 243 break; 244 } 245 246 /* Pins B,C,D are mapped to PCI_SHARED0 - PCI_SHARED2 interrupts */ 247 *ihp = 13 /* PCI_SHARED0 */ + (start + dev - 3) % 3; 248 return 0; 249 } 250 251 const char * 252 macepci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih) 253 { 254 static char irqstr[32]; 255 256 sprintf(irqstr, "crime interrupt %d", ih); 257 return irqstr; 258 } 259 260 261 /* 262 * Handle PCI error interrupts. 263 */ 264 int 265 macepci_intr(void *arg) 266 { 267 struct macepci_softc *sc = (struct macepci_softc *)arg; 268 pci_chipset_tag_t pc = &sc->sc_pc; 269 u_int32_t error, address; 270 271 error = bus_space_read_4(pc->iot, pc->ioh, MACE_PCI_ERROR_FLAGS); 272 address = bus_space_read_4(pc->iot, pc->ioh, MACE_PCI_ERROR_ADDR); 273 while (error & 0xffc00000) { 274 if (error & MACE_PERR_MASTER_ABORT) { 275 /* 276 * this seems to be a more-or-less normal error 277 * condition (e.g., "pcictl pci0 list" generates 278 * a _lot_ of these errors, so no message for now 279 * while I figure out if I missed a trick somewhere. 280 */ 281 error &= ~MACE_PERR_MASTER_ABORT; 282 bus_space_write_4(pc->iot, pc->ioh, 283 MACE_PCI_ERROR_FLAGS, error); 284 } 285 286 if (error & MACE_PERR_TARGET_ABORT) { 287 printf("mace: target abort at %x\n", address); 288 error &= ~MACE_PERR_TARGET_ABORT; 289 bus_space_write_4(pc->iot, pc->ioh, 290 MACE_PCI_ERROR_FLAGS, error); 291 } 292 293 if (error & MACE_PERR_DATA_PARITY_ERR) { 294 printf("mace: parity error at %x\n", address); 295 error &= ~MACE_PERR_DATA_PARITY_ERR; 296 bus_space_write_4(pc->iot, pc->ioh, 297 MACE_PCI_ERROR_FLAGS, error); 298 } 299 300 if (error & MACE_PERR_RETRY_ERR) { 301 printf("mace: retry error at %x\n", address); 302 error &= ~MACE_PERR_RETRY_ERR; 303 bus_space_write_4(pc->iot, pc->ioh, 304 MACE_PCI_ERROR_FLAGS, error); 305 } 306 307 if (error & MACE_PERR_ILLEGAL_CMD) { 308 printf("mace: illegal command at %x\n", address); 309 error &= ~MACE_PERR_ILLEGAL_CMD; 310 bus_space_write_4(pc->iot, pc->ioh, 311 MACE_PCI_ERROR_FLAGS, error); 312 } 313 314 if (error & MACE_PERR_SYSTEM_ERR) { 315 printf("mace: system error at %x\n", address); 316 error &= ~MACE_PERR_SYSTEM_ERR; 317 bus_space_write_4(pc->iot, pc->ioh, 318 MACE_PCI_ERROR_FLAGS, error); 319 } 320 321 if (error & MACE_PERR_INTERRUPT_TEST) { 322 printf("mace: interrupt test at %x\n", address); 323 error &= ~MACE_PERR_INTERRUPT_TEST; 324 bus_space_write_4(pc->iot, pc->ioh, 325 MACE_PCI_ERROR_FLAGS, error); 326 } 327 328 if (error & MACE_PERR_PARITY_ERR) { 329 printf("mace: parity error at %x\n", address); 330 error &= ~MACE_PERR_PARITY_ERR; 331 bus_space_write_4(pc->iot, pc->ioh, 332 MACE_PCI_ERROR_FLAGS, error); 333 } 334 335 if (error & MACE_PERR_RSVD) { 336 printf("mace: reserved condition at %x\n", address); 337 error &= ~MACE_PERR_RSVD; 338 bus_space_write_4(pc->iot, pc->ioh, 339 MACE_PCI_ERROR_FLAGS, error); 340 } 341 342 if (error & MACE_PERR_OVERRUN) { 343 printf("mace: overrun at %x\n", address); 344 error &= ~MACE_PERR_OVERRUN; 345 bus_space_write_4(pc->iot, pc->ioh, 346 MACE_PCI_ERROR_FLAGS, error); 347 } 348 } 349 return 0; 350 } 351
Indexes created Tue Sep 30 20:09:53 GMT 2025