pci_mace.c revision 1.18
1 /* $NetBSD: pci_mace.c,v 1.18 2015/02/18 16:47:59 macallan Exp $ */ 2 3 /* 4 * Copyright (c) 2001,2003 Christopher Sekiya 5 * Copyright (c) 2000 Soren S. Jorvang 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed for the 19 * NetBSD Project. See http://www.NetBSD.org/ for 20 * information about NetBSD. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: pci_mace.c,v 1.18 2015/02/18 16:47:59 macallan Exp $"); 38 39 #include "opt_pci.h" 40 #include "pci.h" 41 42 #include <sys/param.h> 43 #include <sys/device.h> 44 #include <sys/systm.h> 45 46 #include <machine/cpu.h> 47 #include <machine/locore.h> 48 #include <machine/autoconf.h> 49 #include <machine/vmparam.h> 50 #include <sys/bus.h> 51 #include <machine/machtype.h> 52 53 #include <mips/cache.h> 54 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcidevs.h> 58 59 #include <sys/extent.h> 60 #include <sys/malloc.h> 61 #include <dev/pci/pciconf.h> 62 63 #include <sgimips/mace/macereg.h> 64 #include <sgimips/mace/macevar.h> 65 66 #include <sgimips/mace/pcireg_mace.h> 67 68 struct macepci_softc { 69 struct sgimips_pci_chipset sc_pc; 70 }; 71 72 static int macepci_match(device_t, cfdata_t, void *); 73 static void macepci_attach(device_t, device_t, void *); 74 static int macepci_bus_maxdevs(pci_chipset_tag_t, int); 75 static pcireg_t macepci_conf_read(pci_chipset_tag_t, pcitag_t, int); 76 static void macepci_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 77 static int macepci_intr_map(const struct pci_attach_args *, 78 pci_intr_handle_t *); 79 static const char * 80 macepci_intr_string(pci_chipset_tag_t, pci_intr_handle_t, 81 char *, size_t); 82 static int macepci_intr(void *); 83 84 CFATTACH_DECL_NEW(macepci, sizeof(struct macepci_softc), 85 macepci_match, macepci_attach, NULL, NULL); 86 87 static void pcimem_bus_mem_init(bus_space_tag_t, void *); 88 static void pciio_bus_mem_init(bus_space_tag_t, void *); 89 static struct mips_bus_space pcimem_mbst; 90 static struct mips_bus_space pciio_mbst; 91 bus_space_tag_t mace_pci_memt = NULL; 92 bus_space_tag_t mace_pci_iot = NULL; 93 94 static int 95 macepci_match(device_t parent, cfdata_t match, void *aux) 96 { 97 98 return (1); 99 } 100 101 static void 102 macepci_attach(device_t parent, device_t self, void *aux) 103 { 104 struct macepci_softc *sc = device_private(self); 105 pci_chipset_tag_t pc = &sc->sc_pc; 106 struct mace_attach_args *maa = aux; 107 struct pcibus_attach_args pba; 108 u_int32_t control; 109 int rev; 110 111 if (bus_space_subregion(maa->maa_st, maa->maa_sh, 112 maa->maa_offset, 0, &pc->ioh) ) 113 panic("macepci_attach: couldn't map"); 114 115 pc->iot = maa->maa_st; 116 117 rev = bus_space_read_4(pc->iot, pc->ioh, MACEPCI_REVISION); 118 printf(": rev %d\n", rev); 119 120 pcimem_bus_mem_init(&pcimem_mbst, NULL); 121 mace_pci_memt = &pcimem_mbst; 122 pciio_bus_mem_init(&pciio_mbst, NULL); 123 mace_pci_iot = &pciio_mbst; 124 125 pc->pc_bus_maxdevs = macepci_bus_maxdevs; 126 pc->pc_conf_read = macepci_conf_read; 127 pc->pc_conf_write = macepci_conf_write; 128 pc->pc_intr_map = macepci_intr_map; 129 pc->pc_intr_string = macepci_intr_string; 130 pc->intr_establish = mace_intr_establish; 131 pc->intr_disestablish = mace_intr_disestablish; 132 133 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_ERROR_ADDR, 0); 134 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_ERROR_FLAGS, 0); 135 136 /* Turn on PCI error interrupts */ 137 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONTROL, 138 MACE_PCI_CONTROL_SERR_ENA | 139 MACE_PCI_CONTROL_PARITY_ERR | 140 MACE_PCI_CONTROL_PARK_LIU | 141 MACE_PCI_CONTROL_OVERRUN_INT | 142 MACE_PCI_CONTROL_PARITY_INT | 143 MACE_PCI_CONTROL_SERR_INT | 144 MACE_PCI_CONTROL_IT_INT | 145 MACE_PCI_CONTROL_RE_INT | 146 MACE_PCI_CONTROL_DPED_INT | 147 MACE_PCI_CONTROL_TAR_INT | 148 MACE_PCI_CONTROL_MAR_INT); 149 150 /* 151 * Enable all MACE PCI interrupts. They will be masked by 152 * the CRIME code. 153 */ 154 control = bus_space_read_4(pc->iot, pc->ioh, MACEPCI_CONTROL); 155 control |= CONTROL_INT_MASK; 156 bus_space_write_4(pc->iot, pc->ioh, MACEPCI_CONTROL, control); 157 158 #if NPCI > 0 159 pc->pc_ioext = extent_create("macepciio", 0x00001000, 0x01ffffff, 160 NULL, 0, EX_NOWAIT); 161 pc->pc_memext = extent_create("macepcimem", 0x80100000, 0x81ffffff, 162 NULL, 0, EX_NOWAIT); 163 pci_configure_bus(pc, pc->pc_ioext, pc->pc_memext, NULL, 0, 164 mips_cache_info.mci_dcache_align); 165 memset(&pba, 0, sizeof pba); 166 /*XXX*/ pba.pba_iot = mace_pci_iot; 167 /*XXX*/ pba.pba_memt = mace_pci_memt; 168 pba.pba_dmat = &pci_bus_dma_tag; 169 pba.pba_dmat64 = NULL; 170 pba.pba_bus = 0; 171 pba.pba_bridgetag = NULL; 172 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY | 173 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 174 pba.pba_pc = pc; 175 176 #ifdef MACEPCI_IO_WAS_BUGGY 177 if (rev == 0) 178 pba.pba_flags &= ~PCI_FLAGS_IO_OKAY; /* Buggy? */ 179 #endif 180 181 cpu_intr_establish(maa->maa_intr, IPL_NONE, macepci_intr, sc); 182 183 config_found_ia(self, "pcibus", &pba, pcibusprint); 184 #endif 185 } 186 187 int 188 macepci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 189 { 190 191 if (busno == 0) 192 return 5; /* 2 on-board SCSI chips, slots 0, 1 and 2 */ 193 else 194 return 0; /* XXX */ 195 } 196 197 pcireg_t 198 macepci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 199 { 200 pcireg_t data; 201 202 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, (tag | reg)); 203 data = bus_space_read_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_DATA); 204 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, 0); 205 206 return data; 207 } 208 209 void 210 macepci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 211 { 212 /* XXX O2 soren */ 213 if (tag == 0) 214 return; 215 216 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, (tag | reg)); 217 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_DATA, data); 218 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, 0); 219 } 220 221 int 222 macepci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 223 { 224 pci_chipset_tag_t pc = pa->pa_pc; 225 pcitag_t intrtag = pa->pa_intrtag; 226 int pin = pa->pa_intrpin; 227 int bus, dev, func, start; 228 229 pci_decompose_tag(pc, intrtag, &bus, &dev, &func); 230 231 if (dev < 3 && pin != PCI_INTERRUPT_PIN_A) 232 panic("SCSI0 and SCSI1 must be hardwired!"); 233 234 switch (pin) { 235 default: 236 case PCI_INTERRUPT_PIN_NONE: 237 return -1; 238 239 case PCI_INTERRUPT_PIN_A: 240 /* 241 * Each of SCSI{0,1}, & slots 0 - 2 has dedicated interrupt 242 * for pin A? 243 */ 244 *ihp = dev + 7; 245 return 0; 246 247 case PCI_INTERRUPT_PIN_B: 248 start = 0; 249 break; 250 case PCI_INTERRUPT_PIN_C: 251 start = 1; 252 break; 253 case PCI_INTERRUPT_PIN_D: 254 start = 2; 255 break; 256 } 257 258 /* Pins B,C,D are mapped to PCI_SHARED0 - PCI_SHARED2 interrupts */ 259 *ihp = 13 /* PCI_SHARED0 */ + (start + dev - 3) % 3; 260 return 0; 261 } 262 263 const char * 264 macepci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih, char *buf, 265 size_t len) 266 { 267 snprintf(buf, len, "crime interrupt %d", ih); 268 return buf; 269 } 270 271 272 /* 273 * Handle PCI error interrupts. 274 */ 275 int 276 macepci_intr(void *arg) 277 { 278 struct macepci_softc *sc = (struct macepci_softc *)arg; 279 pci_chipset_tag_t pc = &sc->sc_pc; 280 u_int32_t error, address; 281 282 error = bus_space_read_4(pc->iot, pc->ioh, MACE_PCI_ERROR_FLAGS); 283 address = bus_space_read_4(pc->iot, pc->ioh, MACE_PCI_ERROR_ADDR); 284 while (error & 0xffc00000) { 285 if (error & MACE_PERR_MASTER_ABORT) { 286 /* 287 * this seems to be a more-or-less normal error 288 * condition (e.g., "pcictl pci0 list" generates 289 * a _lot_ of these errors, so no message for now 290 * while I figure out if I missed a trick somewhere. 291 */ 292 error &= ~MACE_PERR_MASTER_ABORT; 293 bus_space_write_4(pc->iot, pc->ioh, 294 MACE_PCI_ERROR_FLAGS, error); 295 } 296 297 if (error & MACE_PERR_TARGET_ABORT) { 298 printf("mace: target abort at %x\n", address); 299 error &= ~MACE_PERR_TARGET_ABORT; 300 bus_space_write_4(pc->iot, pc->ioh, 301 MACE_PCI_ERROR_FLAGS, error); 302 } 303 304 if (error & MACE_PERR_DATA_PARITY_ERR) { 305 printf("mace: parity error at %x\n", address); 306 error &= ~MACE_PERR_DATA_PARITY_ERR; 307 bus_space_write_4(pc->iot, pc->ioh, 308 MACE_PCI_ERROR_FLAGS, error); 309 } 310 311 if (error & MACE_PERR_RETRY_ERR) { 312 printf("mace: retry error at %x\n", address); 313 error &= ~MACE_PERR_RETRY_ERR; 314 bus_space_write_4(pc->iot, pc->ioh, 315 MACE_PCI_ERROR_FLAGS, error); 316 } 317 318 if (error & MACE_PERR_ILLEGAL_CMD) { 319 printf("mace: illegal command at %x\n", address); 320 error &= ~MACE_PERR_ILLEGAL_CMD; 321 bus_space_write_4(pc->iot, pc->ioh, 322 MACE_PCI_ERROR_FLAGS, error); 323 } 324 325 if (error & MACE_PERR_SYSTEM_ERR) { 326 printf("mace: system error at %x\n", address); 327 error &= ~MACE_PERR_SYSTEM_ERR; 328 bus_space_write_4(pc->iot, pc->ioh, 329 MACE_PCI_ERROR_FLAGS, error); 330 } 331 332 if (error & MACE_PERR_INTERRUPT_TEST) { 333 printf("mace: interrupt test at %x\n", address); 334 error &= ~MACE_PERR_INTERRUPT_TEST; 335 bus_space_write_4(pc->iot, pc->ioh, 336 MACE_PCI_ERROR_FLAGS, error); 337 } 338 339 if (error & MACE_PERR_PARITY_ERR) { 340 printf("mace: parity error at %x\n", address); 341 error &= ~MACE_PERR_PARITY_ERR; 342 bus_space_write_4(pc->iot, pc->ioh, 343 MACE_PCI_ERROR_FLAGS, error); 344 } 345 346 if (error & MACE_PERR_RSVD) { 347 printf("mace: reserved condition at %x\n", address); 348 error &= ~MACE_PERR_RSVD; 349 bus_space_write_4(pc->iot, pc->ioh, 350 MACE_PCI_ERROR_FLAGS, error); 351 } 352 353 if (error & MACE_PERR_OVERRUN) { 354 printf("mace: overrun at %x\n", address); 355 error &= ~MACE_PERR_OVERRUN; 356 bus_space_write_4(pc->iot, pc->ioh, 357 MACE_PCI_ERROR_FLAGS, error); 358 } 359 } 360 return 0; 361 } 362 363 /* 364 * use the 32MB windows to access PCI space when running a 32bit kernel, 365 * use full views at >4GB in LP64 366 * XXX access to PCI space is endian-twiddled which can't be turned off so we 367 * need to instruct bus_space to un-twiddle them for us so 8bit and 16bit 368 * accesses look little-endian 369 */ 370 #define CHIP pcimem 371 #define CHIP_MEM /* defined */ 372 #define CHIP_WRONG_ENDIAN 373 374 /* 375 * the lower 2GB of PCI space are two views of system memory, with and without 376 * endianness twiddling 377 */ 378 #define CHIP_W1_BUS_START(v) 0x80000000UL 379 #define CHIP_W1_BUS_END(v) 0xffffffffUL 380 #ifdef _LP64 381 #define CHIP_W1_SYS_START(v) MACE_PCI_HI_MEMORY 382 #define CHIP_W1_SYS_END(v) MACE_PCI_HI_MEMORY + 0x7fffffffUL 383 #else 384 #define CHIP_W1_SYS_START(v) MACE_PCI_LOW_MEMORY 385 #define CHIP_W1_SYS_END(v) MACE_PCI_LOW_MEMORY + 0x01ffffffUL 386 #endif 387 388 #include <mips/mips/bus_space_alignstride_chipdep.c> 389 390 #undef CHIP 391 #undef CHIP_W1_BUS_START 392 #undef CHIP_W1_BUS_END 393 #undef CHIP_W1_SYS_START 394 #undef CHIP_W1_SYS_END 395 396 #define CHIP pciio 397 /* 398 * Even though it's PCI IO space, it's memory mapped so there is no reason not 399 * to allow linear mappings or mmapings into userland. In fact we may need to 400 * do just that in order to use things like PCI graphics cards in X. 401 */ 402 #define CHIP_MEM /* defined */ 403 #define CHIP_W1_BUS_START(v) 0x00000000UL 404 #define CHIP_W1_BUS_END(v) 0xffffffffUL 405 #ifdef _LP64 406 #define CHIP_W1_SYS_START(v) MACE_PCI_HI_IO 407 #define CHIP_W1_SYS_END(v) MACE_PCI_HI_IO + 0xffffffffUL 408 #else 409 #define CHIP_W1_SYS_START(v) MACE_PCI_LOW_IO 410 #define CHIP_W1_SYS_END(v) MACE_PCI_LOW_IO + 0x01ffffffUL 411 #endif 412 413 #include <mips/mips/bus_space_alignstride_chipdep.c> 414
Indexes created Tue Sep 30 20:09:53 GMT 2025