pci_mace.c revision 1.2
1 /* $NetBSD: pci_mace.c,v 1.2 2004/01/19 10:28:28 sekiya Exp $ */ 2 3 /* 4 * Copyright (c) 2001,2003 Christopher Sekiya 5 * Copyright (c) 2000 Soren S. Jorvang 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed for the 19 * NetBSD Project. See http://www.NetBSD.org/ for 20 * information about NetBSD. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: pci_mace.c,v 1.2 2004/01/19 10:28:28 sekiya Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/device.h> 41 #include <sys/systm.h> 42 43 #include <machine/cpu.h> 44 #include <machine/locore.h> 45 #include <machine/autoconf.h> 46 #include <machine/vmparam.h> 47 #include <machine/bus.h> 48 #include <machine/machtype.h> 49 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcidevs.h> 53 54 #include <sgimips/mace/macereg.h> 55 #include <sgimips/mace/macevar.h> 56 57 #include <sgimips/mace/pcireg_mace.h> 58 #include <sgimips/pci/pci_addr_fixup.h> 59 60 #define PCIBIOS_PRINTV(arg) \ 61 do { \ 62 printf arg; \ 63 } while (0) 64 #define PCIBIOS_PRINTVN(n, arg) \ 65 do { \ 66 printf arg; \ 67 } while (0) 68 69 70 #define PAGE_ALIGN(x) (((x) + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1)) 71 #define MEG_ALIGN(x) (((x) + 0x100000 - 1) & ~(0x100000 - 1)) 72 73 #include "pci.h" 74 75 struct macepci_softc { 76 struct device sc_dev; 77 78 struct sgimips_pci_chipset sc_pc; 79 }; 80 81 static int macepci_match(struct device *, struct cfdata *, void *); 82 static void macepci_attach(struct device *, struct device *, void *); 83 static int macepci_print(void *, const char *); 84 pcireg_t macepci_conf_read(pci_chipset_tag_t, pcitag_t, int); 85 void macepci_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 86 int macepci_intr(void *); 87 88 struct pciaddr pciaddr; 89 90 bus_addr_t pciaddr_ioaddr(u_int32_t val); 91 92 int pciaddr_do_resource_allocate(pci_chipset_tag_t pc, pcitag_t tag, int mapreg, void *ctx, int type, bus_addr_t *addr, bus_size_t size); 93 94 unsigned int ioaddr_base = 0x1000; 95 unsigned int memaddr_base = 0x80100000; 96 97 CFATTACH_DECL(macepci, sizeof(struct macepci_softc), 98 macepci_match, macepci_attach, NULL, NULL); 99 100 static int 101 macepci_match(parent, match, aux) 102 struct device *parent; 103 struct cfdata *match; 104 void *aux; 105 { 106 107 return (1); 108 } 109 110 static void 111 macepci_attach(parent, self, aux) 112 struct device *parent; 113 struct device *self; 114 void *aux; 115 { 116 struct macepci_softc *sc = (struct macepci_softc *)self; 117 pci_chipset_tag_t pc = &sc->sc_pc; 118 struct mace_attach_args *maa = aux; 119 struct pcibus_attach_args pba; 120 u_int32_t control; 121 pcitag_t devtag; 122 int device, rev; 123 124 if (bus_space_subregion(maa->maa_st, maa->maa_sh, 125 maa->maa_offset, 0, &pc->ioh) ) 126 panic("macepci_attach: couldn't map"); 127 128 pc->iot = maa->maa_st; 129 130 rev = bus_space_read_4(pc->iot, pc->ioh, MACEPCI_REVISION); 131 printf(": rev %d\n", rev); 132 133 pc->pc_conf_read = macepci_conf_read; 134 pc->pc_conf_write = macepci_conf_write; 135 136 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_ERROR_ADDR, 0); 137 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_ERROR_FLAGS, 0); 138 139 /* Turn on PCI error interrupts */ 140 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONTROL, 141 MACE_PCI_CONTROL_SERR_ENA | 142 MACE_PCI_CONTROL_PARITY_ERR | 143 MACE_PCI_CONTROL_PARK_LIU | 144 MACE_PCI_CONTROL_OVERRUN_INT | 145 MACE_PCI_CONTROL_PARITY_INT | 146 MACE_PCI_CONTROL_SERR_INT | 147 MACE_PCI_CONTROL_IT_INT | 148 MACE_PCI_CONTROL_RE_INT | 149 MACE_PCI_CONTROL_DPED_INT | 150 MACE_PCI_CONTROL_TAR_INT | 151 MACE_PCI_CONTROL_MAR_INT); 152 153 /* Must fix up all PCI devices, ahc_pci expects proper i/o mapping */ 154 for (device = 1; device < 4; device++) { 155 const struct pci_quirkdata *qd; 156 int function, nfuncs; 157 pcireg_t bhlcr, id; 158 159 devtag = pci_make_tag(pc, 0, device, 0); 160 id = pci_conf_read(pc, devtag, PCI_ID_REG); 161 162 /* Invalid vendor ID value? */ 163 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 164 continue; 165 /* XXX Not invalid, but we've done this ~forever. */ 166 if (PCI_VENDOR(id) == 0) 167 continue; 168 169 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 170 bhlcr = pci_conf_read(pc, devtag, PCI_BHLC_REG); 171 172 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 173 (qd != NULL && 174 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 175 nfuncs = 8; 176 else 177 nfuncs = 1; 178 179 for (function = 0; function < nfuncs; function++) { 180 devtag = pci_make_tag(pc, 0, device, function); 181 id = pci_conf_read(pc, devtag, PCI_ID_REG); 182 183 /* Invalid vendor ID value? */ 184 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 185 continue; 186 /* Not invalid, but we've done this ~forever */ 187 if (PCI_VENDOR(id) == 0) 188 continue; 189 190 pciaddr_resource_manage(pc, devtag, NULL, NULL); 191 } 192 } 193 194 /* 195 * Enable all MACE PCI interrupts. They will be masked by 196 * the CRIME code. 197 */ 198 control = bus_space_read_4(pc->iot, pc->ioh, MACEPCI_CONTROL); 199 control |= CONTROL_INT_MASK; 200 bus_space_write_4(pc->iot, pc->ioh, MACEPCI_CONTROL, control); 201 202 #if NPCI > 0 203 memset(&pba, 0, sizeof pba); 204 pba.pba_busname = "pci"; 205 /*XXX*/ pba.pba_iot = SGIMIPS_BUS_SPACE_IO; 206 /*XXX*/ pba.pba_memt = SGIMIPS_BUS_SPACE_MEM; 207 pba.pba_dmat = &pci_bus_dma_tag; 208 pba.pba_dmat64 = NULL; 209 pba.pba_bus = 0; 210 pba.pba_bridgetag = NULL; 211 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 212 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 213 pba.pba_pc = pc; 214 215 #ifdef MACEPCI_IO_WAS_BUGGY 216 if (rev == 0) 217 pba.pba_flags &= ~PCI_FLAGS_IO_ENABLED; /* Buggy? */ 218 #endif 219 220 cpu_intr_establish(maa->maa_intr, IPL_NONE, macepci_intr, sc); 221 222 config_found(self, &pba, macepci_print); 223 #endif 224 } 225 226 227 static int 228 macepci_print(aux, pnp) 229 void *aux; 230 const char *pnp; 231 { 232 struct pcibus_attach_args *pba = aux; 233 234 if (pnp != 0) 235 aprint_normal("%s at %s", pba->pba_busname, pnp); 236 else 237 aprint_normal(" bus %d", pba->pba_bus); 238 239 return UNCONF; 240 } 241 242 pcireg_t 243 macepci_conf_read(pc, tag, reg) 244 pci_chipset_tag_t pc; 245 pcitag_t tag; 246 int reg; 247 { 248 pcireg_t data; 249 250 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, (tag | reg)); 251 data = bus_space_read_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_DATA); 252 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, 0); 253 254 return data; 255 } 256 257 void 258 macepci_conf_write(pc, tag, reg, data) 259 pci_chipset_tag_t pc; 260 pcitag_t tag; 261 int reg; 262 pcireg_t data; 263 { 264 /* XXX O2 soren */ 265 if (tag == 0) 266 return; 267 268 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, (tag | reg)); 269 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_DATA, data); 270 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, 0); 271 } 272 273 274 /* 275 * Handle PCI error interrupts. 276 */ 277 int 278 macepci_intr(arg) 279 void *arg; 280 { 281 struct macepci_softc *sc = (struct macepci_softc *)arg; 282 pci_chipset_tag_t pc = &sc->sc_pc; 283 u_int32_t error, address; 284 285 error = bus_space_read_4(pc->iot, pc->ioh, MACE_PCI_ERROR_FLAGS); 286 address = bus_space_read_4(pc->iot, pc->ioh, MACE_PCI_ERROR_ADDR); 287 while (error & 0xffc00000) { 288 if (error & MACE_PERR_MASTER_ABORT) { 289 /* 290 * this seems to be a more-or-less normal error 291 * condition (e.g., "pcictl pci0 list" generates 292 * a _lot_ of these errors, so no message for now 293 * while I figure out if I missed a trick somewhere. 294 */ 295 error &= ~MACE_PERR_MASTER_ABORT; 296 bus_space_write_4(pc->iot, pc->ioh, 297 MACE_PCI_ERROR_FLAGS, error); 298 } 299 300 if (error & MACE_PERR_TARGET_ABORT) { 301 printf("mace: target abort at %x\n", address); 302 error &= ~MACE_PERR_TARGET_ABORT; 303 bus_space_write_4(pc->iot, pc->ioh, 304 MACE_PCI_ERROR_FLAGS, error); 305 } 306 307 if (error & MACE_PERR_DATA_PARITY_ERR) { 308 printf("mace: parity error at %x\n", address); 309 error &= ~MACE_PERR_DATA_PARITY_ERR; 310 bus_space_write_4(pc->iot, pc->ioh, 311 MACE_PCI_ERROR_FLAGS, error); 312 } 313 314 if (error & MACE_PERR_RETRY_ERR) { 315 printf("mace: retry error at %x\n", address); 316 error &= ~MACE_PERR_RETRY_ERR; 317 bus_space_write_4(pc->iot, pc->ioh, 318 MACE_PCI_ERROR_FLAGS, error); 319 } 320 321 if (error & MACE_PERR_ILLEGAL_CMD) { 322 printf("mace: illegal command at %x\n", address); 323 error &= ~MACE_PERR_ILLEGAL_CMD; 324 bus_space_write_4(pc->iot, pc->ioh, 325 MACE_PCI_ERROR_FLAGS, error); 326 } 327 328 if (error & MACE_PERR_SYSTEM_ERR) { 329 printf("mace: system error at %x\n", address); 330 error &= ~MACE_PERR_SYSTEM_ERR; 331 bus_space_write_4(pc->iot, pc->ioh, 332 MACE_PCI_ERROR_FLAGS, error); 333 } 334 335 if (error & MACE_PERR_INTERRUPT_TEST) { 336 printf("mace: interrupt test at %x\n", address); 337 error &= ~MACE_PERR_INTERRUPT_TEST; 338 bus_space_write_4(pc->iot, pc->ioh, 339 MACE_PCI_ERROR_FLAGS, error); 340 } 341 342 if (error & MACE_PERR_PARITY_ERR) { 343 printf("mace: parity error at %x\n", address); 344 error &= ~MACE_PERR_PARITY_ERR; 345 bus_space_write_4(pc->iot, pc->ioh, 346 MACE_PCI_ERROR_FLAGS, error); 347 } 348 349 if (error & MACE_PERR_RSVD) { 350 printf("mace: reserved condition at %x\n", address); 351 error &= ~MACE_PERR_RSVD; 352 bus_space_write_4(pc->iot, pc->ioh, 353 MACE_PCI_ERROR_FLAGS, error); 354 } 355 356 if (error & MACE_PERR_OVERRUN) { 357 printf("mace: overrun at %x\n", address); 358 error &= ~MACE_PERR_OVERRUN; 359 bus_space_write_4(pc->iot, pc->ioh, 360 MACE_PCI_ERROR_FLAGS, error); 361 } 362 } 363 return 0; 364 } 365 366 /* PCI Address fixup routines */ 367 368 void 369 pciaddr_resource_manage(pc, tag, func, ctx) 370 pci_chipset_tag_t pc; 371 pcitag_t tag; 372 pciaddr_resource_manage_func_t func; 373 void *ctx; 374 { 375 pcireg_t val, mask; 376 bus_addr_t addr; 377 bus_size_t size; 378 int error, mapreg, type, reg_start, reg_end, width; 379 380 val = macepci_conf_read(pc, tag, PCI_BHLC_REG); 381 switch (PCI_HDRTYPE_TYPE(val)) { 382 default: 383 printf("WARNING: unknown PCI device header."); 384 pciaddr.nbogus++; 385 return; 386 case 0: 387 reg_start = PCI_MAPREG_START; 388 reg_end = PCI_MAPREG_END; 389 break; 390 case 1: /* PCI-PCI bridge */ 391 reg_start = PCI_MAPREG_START; 392 reg_end = PCI_MAPREG_PPB_END; 393 break; 394 case 2: /* PCI-CardBus bridge */ 395 reg_start = PCI_MAPREG_START; 396 reg_end = PCI_MAPREG_PCB_END; 397 break; 398 } 399 error = 0; 400 401 for (mapreg = reg_start; mapreg < reg_end; mapreg += width) { 402 /* inquire PCI device bus space requirement */ 403 val = macepci_conf_read(pc, tag, mapreg); 404 macepci_conf_write(pc, tag, mapreg, ~0); 405 406 mask = macepci_conf_read(pc, tag, mapreg); 407 macepci_conf_write(pc, tag, mapreg, val); 408 409 type = PCI_MAPREG_TYPE(val); 410 width = 4; 411 412 if (type == PCI_MAPREG_TYPE_MEM) { 413 size = PCI_MAPREG_MEM_SIZE(mask); 414 415 /* 416 * XXXrkb: for MEM64 BARs, to be totally kosher 417 * about the requested size, need to read mask 418 * from top 32bits of BAR and stir that into the 419 * size calculation, like so: 420 * 421 * case PCI_MAPREG_MEM_TYPE_64BIT: 422 * bar64 = pci_conf_read(pb->pc, tag, br + 4); 423 * pci_conf_write(pb->pc, tag, br + 4, 0xffffffff); 424 * mask64 = pci_conf_read(pb->pc, tag, br + 4); 425 * pci_conf_write(pb->pc, tag, br + 4, bar64); 426 * size = (u_int64_t) PCI_MAPREG_MEM64_SIZE( 427 * (((u_int64_t) mask64) << 32) | mask); 428 * width = 8; 429 * 430 * Fortunately, anything with all-zeros mask in the 431 * lower 32-bits will have size no less than 1 << 32, 432 * which we're not prepared to deal with, so I don't 433 * feel bad punting on it... 434 */ 435 if (PCI_MAPREG_MEM_TYPE(val) == 436 PCI_MAPREG_MEM_TYPE_64BIT) { 437 /* 438 * XXX We could examine the upper 32 bits 439 * XXX of the BAR here, but we are totally 440 * XXX unprepared to handle a non-zero value, 441 * XXX either here or anywhere else in the 442 * XXX sgimips code (not sure about MI code). 443 * XXX 444 * XXX So just arrange to skip the top 32 445 * XXX bits of the BAR and zero then out 446 * XXX if the BAR is in use. 447 */ 448 width = 8; 449 450 if (size != 0) 451 macepci_conf_write(pc, tag, 452 mapreg + 4, 0); 453 } 454 } else { 455 /* 456 * Upper 16 bits must be one. Devices may hardwire 457 * them to zero, though, per PCI 2.2, 6.2.5.1, p 203. 458 */ 459 mask |= 0xffff0000; 460 size = PCI_MAPREG_IO_SIZE(mask); 461 } 462 463 if (size == 0) /* unused register */ 464 continue; 465 466 addr = pciaddr_ioaddr(val); 467 468 /* reservation/allocation phase */ 469 error += pciaddr_do_resource_allocate(pc, tag, mapreg, 470 ctx, type, &addr, size); 471 472 #if 0 473 PCIBIOS_PRINTV(("\n\t%02xh %s 0x%08x 0x%08x", 474 mapreg, type ? "port" : "mem ", 475 (unsigned int)addr, (unsigned int)size)); 476 #endif 477 } 478 479 /* enable/disable PCI device */ 480 val = macepci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 481 482 if (error == 0) 483 val |= (PCI_COMMAND_IO_ENABLE | 484 PCI_COMMAND_MEM_ENABLE | 485 PCI_COMMAND_MASTER_ENABLE | 486 PCI_COMMAND_SPECIAL_ENABLE | 487 PCI_COMMAND_INVALIDATE_ENABLE | 488 PCI_COMMAND_PARITY_ENABLE); 489 else 490 val &= ~(PCI_COMMAND_IO_ENABLE | 491 PCI_COMMAND_MEM_ENABLE | 492 PCI_COMMAND_MASTER_ENABLE); 493 494 macepci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, val); 495 496 if (error) 497 pciaddr.nbogus++; 498 } 499 500 bus_addr_t 501 pciaddr_ioaddr(val) 502 u_int32_t val; 503 { 504 505 return ((PCI_MAPREG_TYPE(val) == PCI_MAPREG_TYPE_MEM) ? 506 PCI_MAPREG_MEM_ADDR(val) : PCI_MAPREG_IO_ADDR(val)); 507 } 508 509 int 510 pciaddr_do_resource_allocate(pc, tag, mapreg, ctx, type, addr, size) 511 pci_chipset_tag_t pc; 512 pcitag_t tag; 513 void *ctx; 514 int mapreg, type; 515 bus_addr_t *addr; 516 bus_size_t size; 517 { 518 519 switch (type) { 520 case PCI_MAPREG_TYPE_IO: 521 *addr = ioaddr_base; 522 ioaddr_base += PAGE_ALIGN(size); 523 break; 524 525 case PCI_MAPREG_TYPE_MEM: 526 *addr = memaddr_base; 527 memaddr_base += MEG_ALIGN(size); 528 break; 529 530 default: 531 PCIBIOS_PRINTV(("attempt to remap unknown region (addr 0x%lx, " 532 "size 0x%lx, type %d)\n", *addr, size, type)); 533 return 0; 534 } 535 536 537 /* write new address to PCI device configuration header */ 538 macepci_conf_write(pc, tag, mapreg, *addr); 539 540 /* check */ 541 #ifdef PCIBIOSVERBOSE 542 if (!pcibiosverbose) 543 #endif 544 { 545 printf("pci_addr_fixup: "); 546 pciaddr_print_devid(pc, tag); 547 } 548 if (pciaddr_ioaddr(macepci_conf_read(pc, tag, mapreg)) != *addr) { 549 macepci_conf_write(pc, tag, mapreg, 0); /* clear */ 550 printf("fixup failed. (new address=%#x)\n", (unsigned)*addr); 551 return (1); 552 } 553 #ifdef PCIBIOSVERBOSE 554 if (!pcibiosverbose) 555 #endif 556 printf("new address 0x%08x (size 0x%x)\n", (unsigned)*addr, 557 (unsigned)size); 558 559 return (0); 560 } 561 562 void 563 pciaddr_print_devid(pc, tag) 564 pci_chipset_tag_t pc; 565 pcitag_t tag; 566 { 567 int bus, device, function; 568 pcireg_t id; 569 570 id = macepci_conf_read(pc, tag, PCI_ID_REG); 571 pci_decompose_tag(pc, tag, &bus, &device, &function); 572 printf("%03d:%02d:%d 0x%04x 0x%04x ", bus, device, function, 573 PCI_VENDOR(id), PCI_PRODUCT(id)); 574 } 575 576
Indexes created Tue Sep 30 20:09:53 GMT 2025