pci_mace.c revision 1.25
1 /* $NetBSD: pci_mace.c,v 1.25 2021/08/07 16:19:04 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001,2003 Christopher Sekiya 5 * Copyright (c) 2000 Soren S. Jorvang 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed for the 19 * NetBSD Project. See http://www.NetBSD.org/ for 20 * information about NetBSD. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: pci_mace.c,v 1.25 2021/08/07 16:19:04 thorpej Exp $"); 38 39 #include "opt_pci.h" 40 #include "pci.h" 41 42 #include <sys/param.h> 43 #include <sys/device.h> 44 #include <sys/systm.h> 45 46 #include <machine/cpu.h> 47 #include <machine/locore.h> 48 #include <machine/autoconf.h> 49 #include <machine/vmparam.h> 50 #include <sys/bus.h> 51 #include <machine/machtype.h> 52 53 #include <mips/cache.h> 54 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcidevs.h> 58 59 #include <sys/malloc.h> 60 #include <dev/pci/pciconf.h> 61 62 #include <sgimips/mace/macereg.h> 63 #include <sgimips/mace/macevar.h> 64 65 #include <sgimips/mace/pcireg_mace.h> 66 67 #ifndef __mips_o32 68 #define USE_HIGH_PCI 69 #endif 70 71 72 struct macepci_softc { 73 struct sgimips_pci_chipset sc_pc; 74 }; 75 76 static int macepci_match(device_t, cfdata_t, void *); 77 static void macepci_attach(device_t, device_t, void *); 78 static int macepci_bus_maxdevs(pci_chipset_tag_t, int); 79 static pcireg_t macepci_conf_read(pci_chipset_tag_t, pcitag_t, int); 80 static void macepci_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 81 static int macepci_intr_map(const struct pci_attach_args *, 82 pci_intr_handle_t *); 83 static const char * 84 macepci_intr_string(pci_chipset_tag_t, pci_intr_handle_t, 85 char *, size_t); 86 static int macepci_intr(void *); 87 88 CFATTACH_DECL_NEW(macepci, sizeof(struct macepci_softc), 89 macepci_match, macepci_attach, NULL, NULL); 90 91 static void pcimem_bus_mem_init(bus_space_tag_t, void *); 92 static void pciio_bus_mem_init(bus_space_tag_t, void *); 93 static struct mips_bus_space pcimem_mbst; 94 static struct mips_bus_space pciio_mbst; 95 bus_space_tag_t mace_pci_memt = NULL; 96 bus_space_tag_t mace_pci_iot = NULL; 97 98 #define PCI_IO_START 0x00001000 99 #define PCI_IO_END 0x01ffffff 100 #define PCI_IO_SIZE ((PCI_IO_END - PCI_IO_START) + 1) 101 102 #ifdef USE_HIGH_PCI 103 #define PCI_MEM_START 0x80000000 104 #define PCI_MEM_END 0xffffffff 105 #else /* ! USE_HIGH_PCI */ 106 /* XXX no idea why we limit ourselves to only half of the 32MB window */ 107 #define PCI_MEM_START 0x80100000 108 #define PCI_MEM_END 0x81ffffff 109 #endif /* USE_HIGH_PCI */ 110 111 #define PCI_MEM_SIZE ((PCI_MEM_END - PCI_MEM_START) + 1) 112 113 static int 114 macepci_match(device_t parent, cfdata_t match, void *aux) 115 { 116 117 return (1); 118 } 119 120 static void 121 macepci_attach(device_t parent, device_t self, void *aux) 122 { 123 struct macepci_softc *sc = device_private(self); 124 pci_chipset_tag_t pc = &sc->sc_pc; 125 struct mace_attach_args *maa = aux; 126 struct pcibus_attach_args pba; 127 u_int32_t control; 128 int rev; 129 130 if (bus_space_subregion(maa->maa_st, maa->maa_sh, 131 maa->maa_offset, 0, &pc->ioh) ) 132 panic("macepci_attach: couldn't map"); 133 134 pc->iot = maa->maa_st; 135 136 rev = bus_space_read_4(pc->iot, pc->ioh, MACEPCI_REVISION); 137 printf(": rev %d\n", rev); 138 139 pcimem_bus_mem_init(&pcimem_mbst, NULL); 140 mace_pci_memt = &pcimem_mbst; 141 pciio_bus_mem_init(&pciio_mbst, NULL); 142 mace_pci_iot = &pciio_mbst; 143 144 pc->pc_bus_maxdevs = macepci_bus_maxdevs; 145 pc->pc_conf_read = macepci_conf_read; 146 pc->pc_conf_write = macepci_conf_write; 147 pc->pc_intr_map = macepci_intr_map; 148 pc->pc_intr_string = macepci_intr_string; 149 pc->intr_establish = mace_intr_establish; 150 pc->intr_disestablish = mace_intr_disestablish; 151 152 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_ERROR_ADDR, 0); 153 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_ERROR_FLAGS, 0); 154 155 /* Turn on PCI error interrupts */ 156 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONTROL, 157 MACE_PCI_CONTROL_SERR_ENA | 158 MACE_PCI_CONTROL_PARITY_ERR | 159 MACE_PCI_CONTROL_PARK_LIU | 160 MACE_PCI_CONTROL_OVERRUN_INT | 161 MACE_PCI_CONTROL_PARITY_INT | 162 MACE_PCI_CONTROL_SERR_INT | 163 MACE_PCI_CONTROL_IT_INT | 164 MACE_PCI_CONTROL_RE_INT | 165 MACE_PCI_CONTROL_DPED_INT | 166 MACE_PCI_CONTROL_TAR_INT | 167 MACE_PCI_CONTROL_MAR_INT); 168 169 /* 170 * Enable all MACE PCI interrupts. They will be masked by 171 * the CRIME code. 172 */ 173 control = bus_space_read_4(pc->iot, pc->ioh, MACEPCI_CONTROL); 174 control |= CONTROL_INT_MASK; 175 bus_space_write_4(pc->iot, pc->ioh, MACEPCI_CONTROL, control); 176 177 #if NPCI > 0 178 struct pciconf_resources *pcires = pciconf_resource_init(); 179 180 pciconf_resource_add(pcires, PCICONF_RESOURCE_IO, 181 PCI_IO_START, PCI_IO_SIZE); 182 pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM, 183 PCI_MEM_START, PCI_MEM_SIZE); 184 185 pci_configure_bus(pc, pcires, 0, 186 mips_cache_info.mci_dcache_align); 187 188 pciconf_resource_fini(pcires); 189 190 memset(&pba, 0, sizeof pba); 191 pba.pba_iot = mace_pci_iot; 192 pba.pba_memt = mace_pci_memt; 193 pba.pba_dmat = &pci_bus_dma_tag; 194 pba.pba_dmat64 = NULL; 195 pba.pba_bus = 0; 196 pba.pba_bridgetag = NULL; 197 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY | 198 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 199 pba.pba_pc = pc; 200 201 #ifdef MACEPCI_IO_WAS_BUGGY 202 if (rev == 0) 203 pba.pba_flags &= ~PCI_FLAGS_IO_OKAY; /* Buggy? */ 204 #endif 205 206 cpu_intr_establish(maa->maa_intr, IPL_NONE, macepci_intr, sc); 207 208 config_found(self, &pba, pcibusprint, CFARGS_NONE); 209 #endif 210 } 211 212 int 213 macepci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 214 { 215 216 if (busno == 0) 217 return 5; /* 2 on-board SCSI chips, slots 0, 1 and 2 */ 218 else 219 return 0; /* XXX */ 220 } 221 222 pcireg_t 223 macepci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 224 { 225 pcireg_t data; 226 227 if ((unsigned int)reg >= PCI_CONF_SIZE) 228 return (pcireg_t) -1; 229 230 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, (tag | reg)); 231 data = bus_space_read_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_DATA); 232 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, 0); 233 234 return data; 235 } 236 237 void 238 macepci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 239 { 240 241 if ((unsigned int)reg >= PCI_CONF_SIZE) 242 return; 243 244 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, (tag | reg)); 245 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_DATA, data); 246 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, 0); 247 } 248 249 int 250 macepci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 251 { 252 pci_chipset_tag_t pc = pa->pa_pc; 253 pcitag_t intrtag = pa->pa_intrtag; 254 int pin = pa->pa_intrpin; 255 int bus, dev, func, start; 256 257 pci_decompose_tag(pc, intrtag, &bus, &dev, &func); 258 259 if (dev < 3 && pin != PCI_INTERRUPT_PIN_A) 260 panic("SCSI0 and SCSI1 must be hardwired!"); 261 262 switch (pin) { 263 default: 264 case PCI_INTERRUPT_PIN_NONE: 265 return -1; 266 267 case PCI_INTERRUPT_PIN_A: 268 /* 269 * Each of SCSI{0,1}, & slots 0 - 2 has dedicated interrupt 270 * for pin A? 271 */ 272 *ihp = dev + 7; 273 return 0; 274 275 case PCI_INTERRUPT_PIN_B: 276 start = 0; 277 break; 278 case PCI_INTERRUPT_PIN_C: 279 start = 1; 280 break; 281 case PCI_INTERRUPT_PIN_D: 282 start = 2; 283 break; 284 } 285 286 /* Pins B,C,D are mapped to PCI_SHARED0 - PCI_SHARED2 interrupts */ 287 *ihp = 13 /* PCI_SHARED0 */ + (start + dev - 3) % 3; 288 return 0; 289 } 290 291 const char * 292 macepci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih, char *buf, 293 size_t len) 294 { 295 snprintf(buf, len, "crime interrupt %d", ih); 296 return buf; 297 } 298 299 300 /* 301 * Handle PCI error interrupts. 302 */ 303 int 304 macepci_intr(void *arg) 305 { 306 struct macepci_softc *sc = (struct macepci_softc *)arg; 307 pci_chipset_tag_t pc = &sc->sc_pc; 308 uint32_t error, address; 309 310 error = bus_space_read_4(pc->iot, pc->ioh, MACE_PCI_ERROR_FLAGS); 311 address = bus_space_read_4(pc->iot, pc->ioh, MACE_PCI_ERROR_ADDR); 312 if (error & 0xffc00000) { 313 if (error & MACE_PERR_MASTER_ABORT) { 314 /* 315 * this seems to be a more-or-less normal error 316 * condition (e.g., "pcictl pci0 list" generates 317 * a _lot_ of these errors, so no message for now 318 * while I figure out if I missed a trick somewhere. 319 */ 320 } 321 322 if (error & MACE_PERR_TARGET_ABORT) { 323 printf("mace: target abort at %x\n", address); 324 } 325 326 if (error & MACE_PERR_DATA_PARITY_ERR) { 327 printf("mace: parity error at %x\n", address); 328 } 329 330 if (error & MACE_PERR_RETRY_ERR) { 331 printf("mace: retry error at %x\n", address); 332 } 333 334 if (error & MACE_PERR_ILLEGAL_CMD) { 335 printf("mace: illegal command at %x\n", address); 336 } 337 338 if (error & MACE_PERR_SYSTEM_ERR) { 339 printf("mace: system error at %x\n", address); 340 } 341 342 if (error & MACE_PERR_INTERRUPT_TEST) { 343 printf("mace: interrupt test at %x\n", address); 344 } 345 346 if (error & MACE_PERR_PARITY_ERR) { 347 printf("mace: parity error at %x\n", address); 348 } 349 350 if (error & MACE_PERR_RSVD) { 351 printf("mace: reserved condition at %x\n", address); 352 } 353 354 if (error & MACE_PERR_OVERRUN) { 355 printf("mace: overrun at %x\n", address); 356 } 357 358 /* clear all */ 359 bus_space_write_4(pc->iot, pc->ioh, 360 MACE_PCI_ERROR_FLAGS, error & ~0xffc00000); 361 } 362 return 0; 363 } 364 365 /* 366 * use the 32MB windows to access PCI space when running a 32bit kernel, 367 * use full views at >4GB in LP64 368 * XXX access to PCI space is endian-twiddled which can't be turned off so we 369 * need to instruct bus_space to un-twiddle them for us so 8bit and 16bit 370 * accesses look little-endian 371 */ 372 #define CHIP pcimem 373 #define CHIP_MEM /* defined */ 374 #define CHIP_WRONG_ENDIAN 375 376 /* 377 * the lower 2GB of PCI space are two views of system memory, with and without 378 * endianness twiddling 379 */ 380 #define CHIP_W1_BUS_START(v) 0x80000000UL 381 #define CHIP_W1_BUS_END(v) 0xffffffffUL 382 #ifdef USE_HIGH_PCI 383 #define CHIP_W1_SYS_START(v) MACE_PCI_HI_MEMORY 384 #define CHIP_W1_SYS_END(v) MACE_PCI_HI_MEMORY + 0x7fffffffUL 385 #else 386 #define CHIP_W1_SYS_START(v) MACE_PCI_LOW_MEMORY 387 #define CHIP_W1_SYS_END(v) MACE_PCI_LOW_MEMORY + 0x01ffffffUL 388 #endif 389 390 #include <mips/mips/bus_space_alignstride_chipdep.c> 391 392 #undef CHIP 393 #undef CHIP_W1_BUS_START 394 #undef CHIP_W1_BUS_END 395 #undef CHIP_W1_SYS_START 396 #undef CHIP_W1_SYS_END 397 398 #define CHIP pciio 399 /* 400 * Even though it's PCI IO space, it's memory mapped so there is no reason not 401 * to allow linear mappings or mmapings into userland. In fact we may need to 402 * do just that in order to use things like PCI graphics cards in X. 403 */ 404 #define CHIP_MEM /* defined */ 405 #define CHIP_W1_BUS_START(v) 0x00000000UL 406 #define CHIP_W1_BUS_END(v) 0xffffffffUL 407 #ifdef USE_HIGH_PCI 408 #define CHIP_W1_SYS_START(v) MACE_PCI_HI_IO 409 #define CHIP_W1_SYS_END(v) MACE_PCI_HI_IO + 0xffffffffUL 410 #else 411 #define CHIP_W1_SYS_START(v) MACE_PCI_LOW_IO 412 #define CHIP_W1_SYS_END(v) MACE_PCI_LOW_IO + 0x01ffffffUL 413 #endif 414 415 #include <mips/mips/bus_space_alignstride_chipdep.c> 416
Indexes created Tue Sep 30 20:09:53 GMT 2025