pci_mace.c revision 1.7
1 /* $NetBSD: pci_mace.c,v 1.7 2006/04/17 14:01:08 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 2001,2003 Christopher Sekiya 5 * Copyright (c) 2000 Soren S. Jorvang 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed for the 19 * NetBSD Project. See http://www.NetBSD.org/ for 20 * information about NetBSD. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: pci_mace.c,v 1.7 2006/04/17 14:01:08 tsutsui Exp $"); 38 39 #include "opt_pci.h" 40 #include "pci.h" 41 42 #include <sys/param.h> 43 #include <sys/device.h> 44 #include <sys/systm.h> 45 46 #include <machine/cpu.h> 47 #include <machine/locore.h> 48 #include <machine/autoconf.h> 49 #include <machine/vmparam.h> 50 #include <machine/bus.h> 51 #include <machine/machtype.h> 52 53 #include <mips/cache.h> 54 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcidevs.h> 58 59 #ifdef PCI_NETBSD_CONFIGURE 60 #include <sys/extent.h> 61 #include <sys/malloc.h> 62 #include <dev/pci/pciconf.h> 63 #endif 64 65 #include <sgimips/mace/macereg.h> 66 #include <sgimips/mace/macevar.h> 67 68 #include <sgimips/mace/pcireg_mace.h> 69 #ifndef PCI_NETBSD_CONFIGURE 70 #include <sgimips/pci/pci_addr_fixup.h> 71 72 #define PCIBIOS_PRINTV(arg) \ 73 do { \ 74 printf arg; \ 75 } while (0) 76 #define PCIBIOS_PRINTVN(n, arg) \ 77 do { \ 78 printf arg; \ 79 } while (0) 80 81 82 #define PAGE_ALIGN(x) (((x) + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1)) 83 #define MEG_ALIGN(x) (((x) + 0x100000 - 1) & ~(0x100000 - 1)) 84 #endif 85 86 struct macepci_softc { 87 struct device sc_dev; 88 89 struct sgimips_pci_chipset sc_pc; 90 }; 91 92 static int macepci_match(struct device *, struct cfdata *, void *); 93 static void macepci_attach(struct device *, struct device *, void *); 94 pcireg_t macepci_conf_read(pci_chipset_tag_t, pcitag_t, int); 95 void macepci_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 96 int macepci_intr(void *); 97 98 #ifndef PCI_NETBSD_CONFIGURE 99 struct pciaddr pciaddr; 100 101 int pciaddr_do_resource_allocate(pci_chipset_tag_t pc, pcitag_t tag, int mapreg, void *ctx, int type, bus_addr_t *addr, bus_size_t size); 102 103 unsigned int ioaddr_base = 0x1000; 104 unsigned int memaddr_base = 0x80100000; 105 #endif 106 107 CFATTACH_DECL(macepci, sizeof(struct macepci_softc), 108 macepci_match, macepci_attach, NULL, NULL); 109 110 static int 111 macepci_match(struct device *parent, struct cfdata *match, void *aux) 112 { 113 114 return (1); 115 } 116 117 static void 118 macepci_attach(struct device *parent, struct device *self, void *aux) 119 { 120 struct macepci_softc *sc = (struct macepci_softc *)self; 121 pci_chipset_tag_t pc = &sc->sc_pc; 122 struct mace_attach_args *maa = aux; 123 struct pcibus_attach_args pba; 124 u_int32_t control; 125 int rev; 126 #ifndef PCI_NETBSD_CONFIGURE 127 pcitag_t devtag; 128 int device; 129 #endif 130 131 if (bus_space_subregion(maa->maa_st, maa->maa_sh, 132 maa->maa_offset, 0, &pc->ioh) ) 133 panic("macepci_attach: couldn't map"); 134 135 pc->iot = maa->maa_st; 136 137 rev = bus_space_read_4(pc->iot, pc->ioh, MACEPCI_REVISION); 138 printf(": rev %d\n", rev); 139 140 pc->pc_conf_read = macepci_conf_read; 141 pc->pc_conf_write = macepci_conf_write; 142 pc->intr_establish = mace_intr_establish; 143 pc->intr_disestablish = mace_intr_disestablish; 144 145 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_ERROR_ADDR, 0); 146 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_ERROR_FLAGS, 0); 147 148 /* Turn on PCI error interrupts */ 149 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONTROL, 150 MACE_PCI_CONTROL_SERR_ENA | 151 MACE_PCI_CONTROL_PARITY_ERR | 152 MACE_PCI_CONTROL_PARK_LIU | 153 MACE_PCI_CONTROL_OVERRUN_INT | 154 MACE_PCI_CONTROL_PARITY_INT | 155 MACE_PCI_CONTROL_SERR_INT | 156 MACE_PCI_CONTROL_IT_INT | 157 MACE_PCI_CONTROL_RE_INT | 158 MACE_PCI_CONTROL_DPED_INT | 159 MACE_PCI_CONTROL_TAR_INT | 160 MACE_PCI_CONTROL_MAR_INT); 161 162 #ifndef PCI_NETBSD_CONFIGURE 163 /* Must fix up all PCI devices, ahc_pci expects proper i/o mapping */ 164 for (device = 1; device < 4; device++) { 165 const struct pci_quirkdata *qd; 166 int function, nfuncs; 167 pcireg_t bhlcr, id; 168 169 devtag = pci_make_tag(pc, 0, device, 0); 170 id = pci_conf_read(pc, devtag, PCI_ID_REG); 171 172 /* Invalid vendor ID value? */ 173 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 174 continue; 175 /* XXX Not invalid, but we've done this ~forever. */ 176 if (PCI_VENDOR(id) == 0) 177 continue; 178 179 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 180 bhlcr = pci_conf_read(pc, devtag, PCI_BHLC_REG); 181 182 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 183 (qd != NULL && 184 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 185 nfuncs = 8; 186 else 187 nfuncs = 1; 188 189 for (function = 0; function < nfuncs; function++) { 190 devtag = pci_make_tag(pc, 0, device, function); 191 id = pci_conf_read(pc, devtag, PCI_ID_REG); 192 193 /* Invalid vendor ID value? */ 194 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 195 continue; 196 /* Not invalid, but we've done this ~forever */ 197 if (PCI_VENDOR(id) == 0) 198 continue; 199 200 pciaddr_resource_manage(pc, devtag, NULL, NULL); 201 } 202 } 203 #endif 204 205 /* 206 * Enable all MACE PCI interrupts. They will be masked by 207 * the CRIME code. 208 */ 209 control = bus_space_read_4(pc->iot, pc->ioh, MACEPCI_CONTROL); 210 control |= CONTROL_INT_MASK; 211 bus_space_write_4(pc->iot, pc->ioh, MACEPCI_CONTROL, control); 212 213 #if NPCI > 0 214 #ifdef PCI_NETBSD_CONFIGURE 215 pc->pc_ioext = extent_create("macepciio", 0x00001000, 0x01ffffff, 216 M_DEVBUF, NULL, 0, EX_NOWAIT); 217 pc->pc_memext = extent_create("macepcimem", 0x80100000, 0x81ffffff, 218 M_DEVBUF, NULL, 0, EX_NOWAIT); 219 pci_configure_bus(pc, pc->pc_ioext, pc->pc_memext, NULL, 0, 220 mips_dcache_align); 221 #endif 222 memset(&pba, 0, sizeof pba); 223 /*XXX*/ pba.pba_iot = SGIMIPS_BUS_SPACE_IO; 224 /*XXX*/ pba.pba_memt = SGIMIPS_BUS_SPACE_MEM; 225 pba.pba_dmat = &pci_bus_dma_tag; 226 pba.pba_dmat64 = NULL; 227 pba.pba_bus = 0; 228 pba.pba_bridgetag = NULL; 229 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 230 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 231 pba.pba_pc = pc; 232 233 #ifdef MACEPCI_IO_WAS_BUGGY 234 if (rev == 0) 235 pba.pba_flags &= ~PCI_FLAGS_IO_ENABLED; /* Buggy? */ 236 #endif 237 238 cpu_intr_establish(maa->maa_intr, IPL_NONE, macepci_intr, sc); 239 240 config_found_ia(self, "pcibus", &pba, pcibusprint); 241 #endif 242 } 243 244 pcireg_t 245 macepci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 246 { 247 pcireg_t data; 248 249 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, (tag | reg)); 250 data = bus_space_read_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_DATA); 251 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, 0); 252 253 return data; 254 } 255 256 void 257 macepci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 258 { 259 /* XXX O2 soren */ 260 if (tag == 0) 261 return; 262 263 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, (tag | reg)); 264 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_DATA, data); 265 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, 0); 266 } 267 268 269 /* 270 * Handle PCI error interrupts. 271 */ 272 int 273 macepci_intr(void *arg) 274 { 275 struct macepci_softc *sc = (struct macepci_softc *)arg; 276 pci_chipset_tag_t pc = &sc->sc_pc; 277 u_int32_t error, address; 278 279 error = bus_space_read_4(pc->iot, pc->ioh, MACE_PCI_ERROR_FLAGS); 280 address = bus_space_read_4(pc->iot, pc->ioh, MACE_PCI_ERROR_ADDR); 281 while (error & 0xffc00000) { 282 if (error & MACE_PERR_MASTER_ABORT) { 283 /* 284 * this seems to be a more-or-less normal error 285 * condition (e.g., "pcictl pci0 list" generates 286 * a _lot_ of these errors, so no message for now 287 * while I figure out if I missed a trick somewhere. 288 */ 289 error &= ~MACE_PERR_MASTER_ABORT; 290 bus_space_write_4(pc->iot, pc->ioh, 291 MACE_PCI_ERROR_FLAGS, error); 292 } 293 294 if (error & MACE_PERR_TARGET_ABORT) { 295 printf("mace: target abort at %x\n", address); 296 error &= ~MACE_PERR_TARGET_ABORT; 297 bus_space_write_4(pc->iot, pc->ioh, 298 MACE_PCI_ERROR_FLAGS, error); 299 } 300 301 if (error & MACE_PERR_DATA_PARITY_ERR) { 302 printf("mace: parity error at %x\n", address); 303 error &= ~MACE_PERR_DATA_PARITY_ERR; 304 bus_space_write_4(pc->iot, pc->ioh, 305 MACE_PCI_ERROR_FLAGS, error); 306 } 307 308 if (error & MACE_PERR_RETRY_ERR) { 309 printf("mace: retry error at %x\n", address); 310 error &= ~MACE_PERR_RETRY_ERR; 311 bus_space_write_4(pc->iot, pc->ioh, 312 MACE_PCI_ERROR_FLAGS, error); 313 } 314 315 if (error & MACE_PERR_ILLEGAL_CMD) { 316 printf("mace: illegal command at %x\n", address); 317 error &= ~MACE_PERR_ILLEGAL_CMD; 318 bus_space_write_4(pc->iot, pc->ioh, 319 MACE_PCI_ERROR_FLAGS, error); 320 } 321 322 if (error & MACE_PERR_SYSTEM_ERR) { 323 printf("mace: system error at %x\n", address); 324 error &= ~MACE_PERR_SYSTEM_ERR; 325 bus_space_write_4(pc->iot, pc->ioh, 326 MACE_PCI_ERROR_FLAGS, error); 327 } 328 329 if (error & MACE_PERR_INTERRUPT_TEST) { 330 printf("mace: interrupt test at %x\n", address); 331 error &= ~MACE_PERR_INTERRUPT_TEST; 332 bus_space_write_4(pc->iot, pc->ioh, 333 MACE_PCI_ERROR_FLAGS, error); 334 } 335 336 if (error & MACE_PERR_PARITY_ERR) { 337 printf("mace: parity error at %x\n", address); 338 error &= ~MACE_PERR_PARITY_ERR; 339 bus_space_write_4(pc->iot, pc->ioh, 340 MACE_PCI_ERROR_FLAGS, error); 341 } 342 343 if (error & MACE_PERR_RSVD) { 344 printf("mace: reserved condition at %x\n", address); 345 error &= ~MACE_PERR_RSVD; 346 bus_space_write_4(pc->iot, pc->ioh, 347 MACE_PCI_ERROR_FLAGS, error); 348 } 349 350 if (error & MACE_PERR_OVERRUN) { 351 printf("mace: overrun at %x\n", address); 352 error &= ~MACE_PERR_OVERRUN; 353 bus_space_write_4(pc->iot, pc->ioh, 354 MACE_PCI_ERROR_FLAGS, error); 355 } 356 } 357 return 0; 358 } 359 360 #ifndef PCI_NETBSD_CONFIGURE 361 /* PCI Address fixup routines */ 362 363 void 364 pciaddr_resource_manage(pci_chipset_tag_t pc, pcitag_t tag, 365 pciaddr_resource_manage_func_t func, void *ctx) 366 { 367 pcireg_t val, mask; 368 bus_addr_t addr; 369 bus_size_t size; 370 int error, mapreg, type, reg_start, reg_end, width; 371 372 val = macepci_conf_read(pc, tag, PCI_BHLC_REG); 373 switch (PCI_HDRTYPE_TYPE(val)) { 374 default: 375 printf("WARNING: unknown PCI device header."); 376 pciaddr.nbogus++; 377 return; 378 case 0: 379 reg_start = PCI_MAPREG_START; 380 reg_end = PCI_MAPREG_END; 381 break; 382 case 1: /* PCI-PCI bridge */ 383 reg_start = PCI_MAPREG_START; 384 reg_end = PCI_MAPREG_PPB_END; 385 break; 386 case 2: /* PCI-CardBus bridge */ 387 reg_start = PCI_MAPREG_START; 388 reg_end = PCI_MAPREG_PCB_END; 389 break; 390 } 391 error = 0; 392 393 for (mapreg = reg_start; mapreg < reg_end; mapreg += width) { 394 /* inquire PCI device bus space requirement */ 395 val = macepci_conf_read(pc, tag, mapreg); 396 macepci_conf_write(pc, tag, mapreg, ~0); 397 398 mask = macepci_conf_read(pc, tag, mapreg); 399 macepci_conf_write(pc, tag, mapreg, val); 400 401 type = PCI_MAPREG_TYPE(val); 402 width = 4; 403 404 if (type == PCI_MAPREG_TYPE_MEM) { 405 size = PCI_MAPREG_MEM_SIZE(mask); 406 407 /* 408 * XXXrkb: for MEM64 BARs, to be totally kosher 409 * about the requested size, need to read mask 410 * from top 32bits of BAR and stir that into the 411 * size calculation, like so: 412 * 413 * case PCI_MAPREG_MEM_TYPE_64BIT: 414 * bar64 = pci_conf_read(pb->pc, tag, br + 4); 415 * pci_conf_write(pb->pc, tag, br + 4, 0xffffffff); 416 * mask64 = pci_conf_read(pb->pc, tag, br + 4); 417 * pci_conf_write(pb->pc, tag, br + 4, bar64); 418 * size = (u_int64_t) PCI_MAPREG_MEM64_SIZE( 419 * (((u_int64_t) mask64) << 32) | mask); 420 * width = 8; 421 * 422 * Fortunately, anything with all-zeros mask in the 423 * lower 32-bits will have size no less than 1 << 32, 424 * which we're not prepared to deal with, so I don't 425 * feel bad punting on it... 426 */ 427 if (PCI_MAPREG_MEM_TYPE(val) == 428 PCI_MAPREG_MEM_TYPE_64BIT) { 429 /* 430 * XXX We could examine the upper 32 bits 431 * XXX of the BAR here, but we are totally 432 * XXX unprepared to handle a non-zero value, 433 * XXX either here or anywhere else in the 434 * XXX sgimips code (not sure about MI code). 435 * XXX 436 * XXX So just arrange to skip the top 32 437 * XXX bits of the BAR and zero then out 438 * XXX if the BAR is in use. 439 */ 440 width = 8; 441 442 if (size != 0) 443 macepci_conf_write(pc, tag, 444 mapreg + 4, 0); 445 } 446 } else { 447 /* 448 * Upper 16 bits must be one. Devices may hardwire 449 * them to zero, though, per PCI 2.2, 6.2.5.1, p 203. 450 */ 451 mask |= 0xffff0000; 452 size = PCI_MAPREG_IO_SIZE(mask); 453 } 454 455 if (size == 0) /* unused register */ 456 continue; 457 458 addr = pciaddr_ioaddr(val); 459 460 /* reservation/allocation phase */ 461 error += pciaddr_do_resource_allocate(pc, tag, mapreg, 462 ctx, type, &addr, size); 463 464 #if 0 465 PCIBIOS_PRINTV(("\n\t%02xh %s 0x%08x 0x%08x", 466 mapreg, type ? "port" : "mem ", 467 (unsigned int)addr, (unsigned int)size)); 468 #endif 469 } 470 471 /* enable/disable PCI device */ 472 val = macepci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 473 474 if (error == 0) 475 val |= (PCI_COMMAND_IO_ENABLE | 476 PCI_COMMAND_MEM_ENABLE | 477 PCI_COMMAND_MASTER_ENABLE | 478 PCI_COMMAND_SPECIAL_ENABLE | 479 PCI_COMMAND_INVALIDATE_ENABLE | 480 PCI_COMMAND_PARITY_ENABLE); 481 else 482 val &= ~(PCI_COMMAND_IO_ENABLE | 483 PCI_COMMAND_MEM_ENABLE | 484 PCI_COMMAND_MASTER_ENABLE); 485 486 macepci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, val); 487 488 if (error) 489 pciaddr.nbogus++; 490 } 491 492 bus_addr_t 493 pciaddr_ioaddr(u_int32_t val) 494 { 495 496 return ((PCI_MAPREG_TYPE(val) == PCI_MAPREG_TYPE_MEM) ? 497 PCI_MAPREG_MEM_ADDR(val) : PCI_MAPREG_IO_ADDR(val)); 498 } 499 500 int 501 pciaddr_do_resource_allocate(pci_chipset_tag_t pc, pcitag_t tag, int mapreg, 502 void *ctx, int type, bus_addr_t *addr, bus_size_t size) 503 { 504 505 switch (type) { 506 case PCI_MAPREG_TYPE_IO: 507 *addr = ioaddr_base; 508 ioaddr_base += PAGE_ALIGN(size); 509 break; 510 511 case PCI_MAPREG_TYPE_MEM: 512 *addr = memaddr_base; 513 memaddr_base += MEG_ALIGN(size); 514 break; 515 516 default: 517 PCIBIOS_PRINTV(("attempt to remap unknown region (addr 0x%lx, " 518 "size 0x%lx, type %d)\n", *addr, size, type)); 519 return 0; 520 } 521 522 523 /* write new address to PCI device configuration header */ 524 macepci_conf_write(pc, tag, mapreg, *addr); 525 526 /* check */ 527 #ifdef PCIBIOSVERBOSE 528 if (!pcibiosverbose) 529 #endif 530 { 531 printf("pci_addr_fixup: "); 532 pciaddr_print_devid(pc, tag); 533 } 534 if (pciaddr_ioaddr(macepci_conf_read(pc, tag, mapreg)) != *addr) { 535 macepci_conf_write(pc, tag, mapreg, 0); /* clear */ 536 printf("fixup failed. (new address=%#x)\n", (unsigned)*addr); 537 return (1); 538 } 539 #ifdef PCIBIOSVERBOSE 540 if (!pcibiosverbose) 541 #endif 542 printf("new address 0x%08x (size 0x%x)\n", (unsigned)*addr, 543 (unsigned)size); 544 545 return (0); 546 } 547 548 void 549 pciaddr_print_devid(pci_chipset_tag_t pc, pcitag_t tag) 550 { 551 int bus, device, function; 552 pcireg_t id; 553 554 id = macepci_conf_read(pc, tag, PCI_ID_REG); 555 pci_decompose_tag(pc, tag, &bus, &device, &function); 556 printf("%03d:%02d:%d 0x%04x 0x%04x ", bus, device, function, 557 PCI_VENDOR(id), PCI_PRODUCT(id)); 558 } 559 #endif 560
Indexes created Tue Sep 30 20:09:53 GMT 2025