iris_scsireg.h revision 1.1
1 /* $NetBSD: iris_scsireg.h,v 1.1 2019/01/12 16:44:47 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 2018 Naruaki Etomi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* 29 * Copyright (c) 1990 The Regents of the University of California. 30 * All rights reserved. 31 * 32 * This code is derived from software contributed to Berkeley by 33 * Van Jacobson of Lawrence Berkeley Laboratory. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. Neither the name of the University nor the names of its contributors 44 * may be used to endorse or promote products derived from this software 45 * without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 48 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 49 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 50 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 51 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 52 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 53 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 54 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 55 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 56 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 57 * SUCH DAMAGE. 58 * 59 * @(#)scsireg.h 7.3 (Berkeley) 2/5/91 60 */ 61 62 /* 63 * Copyright (c) 2001 Wayne Knowles 64 * 65 * This code is derived from software contributed to Berkeley by 66 * Van Jacobson of Lawrence Berkeley Laboratory. 67 * 68 * Redistribution and use in source and binary forms, with or without 69 * modification, are permitted provided that the following conditions 70 * are met: 71 * 1. Redistributions of source code must retain the above copyright 72 * notice, this list of conditions and the following disclaimer. 73 * 2. Redistributions in binary form must reproduce the above copyright 74 * notice, this list of conditions and the following disclaimer in the 75 * documentation and/or other materials provided with the distribution. 76 * 3. All advertising materials mentioning features or use of this software 77 * must display the following acknowledgement: 78 * This product includes software developed by the University of 79 * California, Berkeley and its contributors. 80 * 4. Neither the name of the University nor the names of its contributors 81 * may be used to endorse or promote products derived from this software 82 * without specific prior written permission. 83 * 84 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 85 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 86 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 87 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 88 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 89 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 90 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 91 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 92 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 93 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 94 * SUCH DAMAGE. 95 * 96 * @(#)scsireg.h 7.3 (Berkeley) 2/5/91 97 */ 98 99 /* 100 * Silicon Graphics "IRIS" series MIPS processors machine bootloader. 101 * WD33C93 SCSI interface hardware description. 102 * Most of the following was adapted from sys/dev/ic/wd33c93reg.h. 103 * NetBSD: wd33c93reg.h,v 1.4 2009/02/12 06:24:45 rumble Exp 104 */ 105 106 #define SBIC_myid 0 107 #define SBIC_cdbsize 0 108 #define SBIC_control 1 109 #define SBIC_timeo 2 110 #define SBIC_cdb1 3 111 #define SBIC_tsecs 3 112 #define SBIC_cdb2 4 113 #define SBIC_theads 4 114 #define SBIC_cdb3 5 115 #define SBIC_tcyl_hi 5 116 #define SBIC_cdb4 6 117 #define SBIC_tcyl_lo 6 118 #define SBIC_cdb5 7 119 #define SBIC_addr_hi 7 120 #define SBIC_cdb6 8 121 #define SBIC_addr_2 8 122 #define SBIC_cdb7 9 123 #define SBIC_addr_3 9 124 #define SBIC_cdb8 10 125 #define SBIC_addr_lo 10 126 #define SBIC_cdb9 11 127 #define SBIC_secno 11 128 #define SBIC_cdb10 12 129 #define SBIC_headno 12 130 #define SBIC_cdb11 13 131 #define SBIC_cylno_hi 13 132 #define SBIC_cdb12 14 133 #define SBIC_cylno_lo 14 134 #define SBIC_tlun 15 135 #define SBIC_cmd_phase 16 136 #define SBIC_syn 17 137 #define SBIC_count_hi 18 138 #define SBIC_count_med 19 139 #define SBIC_count_lo 20 140 #define SBIC_selid 21 141 #define SBIC_rselid 22 142 #define SBIC_csr 23 143 #define SBIC_cmd 24 144 #define SBIC_data 25 145 #define SBIC_queue_tag 26 146 #define SBIC_aux_status 27 147 148 /* wd33c93_asr is addressed directly */ 149 150 /* 151 * Register defines 152 */ 153 154 /* 155 * Auxiliary Status Register 156 */ 157 158 #define SBIC_ASR_INT 0x80 /* Interrupt pending */ 159 #define SBIC_ASR_LCI 0x40 /* Last command ignored */ 160 #define SBIC_ASR_BSY 0x20 /* Busy, only cmd/data/asr readable */ 161 #define SBIC_ASR_CIP 0x10 /* Busy, cmd unavail also */ 162 #define SBIC_ASR_xxx 0x0c 163 #define SBIC_ASR_PE 0x02 /* Parity error (even) */ 164 #define SBIC_ASR_DBR 0x01 /* Data Buffer Ready */ 165 166 /* 167 * My ID register, and/or CDB Size 168 */ 169 170 #define SBIC_ID_FS_8_10 0x00 /* Input clock is 8-10 MHz */ 171 /* 11 MHz is invalid */ 172 #define SBIC_ID_FS_12_15 0x40 /* Input clock is 12-15 MHz */ 173 #define SBIC_ID_FS_16_20 0x80 /* Input clock is 16-20 MHz */ 174 #define SBIC_ID_RAF 0x20 /* Enable Really Advanced Features */ 175 #define SBIC_ID_EHP 0x10 /* Enable host parity */ 176 #define SBIC_ID_EAF 0x08 /* Enable Advanced Features */ 177 #define SBIC_ID_MASK 0x07 178 #define SBIC_ID_CBDSIZE_MASK 0x0f /* if unk SCSI cmd group */ 179 180 /* 181 * Control register 182 */ 183 184 #define SBIC_CTL_DMA 0x80 /* Single byte dma */ 185 #define SBIC_CTL_DBA_DMA 0x40 /* direct buffer access (bus master) */ 186 #define SBIC_CTL_BURST_DMA 0x20 /* continuous mode (8237) */ 187 #define SBIC_CTL_NO_DMA 0x00 /* Programmed I/O */ 188 #define SBIC_CTL_HHP 0x10 /* Halt on host parity error */ 189 #define SBIC_CTL_EDI 0x08 /* Ending disconnect interrupt */ 190 #define SBIC_CTL_IDI 0x04 /* Intermediate disconnect interrupt*/ 191 #define SBIC_CTL_HA 0x02 /* Halt on ATN */ 192 #define SBIC_CTL_scP 0x01 /* Halt on SCSI parity error */ 193 194 /* 195 * Timeout period register 196 * [val in msecs, input clk in 0.1 MHz] 197 */ 198 199 #define SBIC_TIMEOUT(val,clk) ((((val) * (clk)) / 800) + 1) 200 201 /* 202 * CDBn registers, note that 203 * cdb11 is used for status byte in target mode (send-status-and-cc) 204 * cdb12 sez if linked command complete, and w/flag if so 205 */ 206 207 /* 208 * Target LUN register 209 * [holds target status when select-and-xfer] 210 */ 211 212 #define SBIC_TLUN_VALID 0x80 /* did we receive an Identify msg */ 213 #define SBIC_TLUN_DOK 0x40 /* Disconnect OK */ 214 #define SBIC_TLUN_xxx 0x38 215 #define SBIC_TLUN_MASK 0x07 216 217 /* 218 * Command Phase register 219 */ 220 221 #define SBIC_CPH_MASK 0x7f /* values/restarts are cmd specific */ 222 #define SBIC_CPH(p) ((p) & SBIC_CPH_MASK) 223 224 /* 225 * FIFO register 226 */ 227 228 #define SBIC_FIFO_93_DEPTH 5 229 #define SBIC_FIFO_93AB_DEPTH 12 230 231 /* 232 * maximum possible size in TC registers. Since this is 24 bit, it's easy 233 */ 234 #define SBIC_TC_MAX ((1 << 24) - 1) 235 236 /* 237 * Synchronous xfer register 238 * 239 * NB: SBIC_SYN_FSS only valid on WD33C93B with 16-20MHz clock. 240 */ 241 242 #define SBIC_SYN_OFF_MASK 0x0f 243 #define SBIC_SYN_93_MAX_OFFSET (SBIC_FIFO_93_DEPTH - 1) /* 4 is recommended */ 244 #define SBIC_SYN_93AB_MAX_OFFSET SBIC_FIFO_93AB_DEPTH 245 #define SBIC_SYN_PER_MASK 0x70 246 #define SBIC_SYN_MIN_PERIOD 2 /* upto 8, encoded as 0 */ 247 #define SBIC_SYN_FSS 0x80 /* Enable Fast SCSI Transfers (10MB/s)*/ 248 249 #define SBIC_SYN(o, p, f) \ 250 (((o) & SBIC_SYN_OFF_MASK) | (((p) << 4) & SBIC_SYN_PER_MASK) | \ 251 ((f) ? SBIC_SYN_FSS : 0)) 252 253 /* 254 * Transfer count register 255 * optimal access macros depend on addressing 256 */ 257 258 /* 259 * Destination ID (selid) register 260 */ 261 262 #define SBIC_SID_SCC 0x80 /* Select command chaining (tgt) */ 263 #define SBIC_SID_DPD 0x40 /* Data phase direction (inittor) */ 264 #define SBIC_SID_FROM_SCSI 0x40 265 #define SBIC_SID_TO_SCSI 0x00 266 #define SBIC_SID_xxx 0x38 267 #define SBIC_SID_IDMASK 0x07 268 269 /* 270 * Source ID (rselid) register 271 */ 272 273 #define SBIC_RID_ER 0x80 /* Enable reselection */ 274 #define SBIC_RID_ES 0x40 /* Enable selection */ 275 #define SBIC_RID_DSP 0x20 /* Disable select parity */ 276 #define SBIC_RID_SIV 0x08 /* Source ID valid */ 277 #define SBIC_RID_MASK 0x07 278 279 /* 280 * Status register 281 */ 282 283 #define SBIC_CSR_CAUSE 0xf0 284 #define SBIC_CSR_RESET 0x00 /* chip was reset */ 285 #define SBIC_CSR_CMD_DONE 0x10 /* cmd completed */ 286 #define SBIC_CSR_CMD_STOPPED 0x20 /* interrupted or abrted*/ 287 #define SBIC_CSR_CMD_ERR 0x40 /* end with error */ 288 #define SBIC_CSR_BUS_SERVICE 0x80 /* REQ pending on the bus */ 289 290 291 #define SBIC_CSR_QUALIFIER 0x0f 292 /* Reset State Interrupts */ 293 #define SBIC_CSR_RESET 0x00 /* reset w/advanced features*/ 294 #define SBIC_CSR_RESET_AM 0x01 /* reset w/advanced features*/ 295 /* Successful Completion Interrupts */ 296 #define SBIC_CSR_TARGET 0x10 /* reselect complete */ 297 #define SBIC_CSR_INITIATOR 0x11 /* select complete */ 298 #define SBIC_CSR_WO_ATN 0x13 /* tgt mode completion */ 299 #define SBIC_CSR_W_ATN 0x14 /* ditto */ 300 #define SBIC_CSR_XLATED 0x15 /* translate address cmd */ 301 #define SBIC_CSR_S_XFERRED 0x16 /* initiator mode completion*/ 302 #define SBIC_CSR_XFERRED 0x18 /* phase in low bits */ 303 /* Paused or Aborted Interrupts */ 304 #define SBIC_CSR_MSGIN_W_ACK 0x20 /* (I) msgin, ACK asserted*/ 305 #define SBIC_CSR_SDP 0x21 /* (I) SDP msg received */ 306 #define SBIC_CSR_SEL_ABRT 0x22 /* sel/resel aborted */ 307 #define SBIC_CSR_XFR_PAUSED 0x23 /* (T) no ATN */ 308 #define SBIC_CSR_XFR_PAUSED_ATN 0x24 /* (T) ATN is asserted */ 309 #define SBIC_CSR_RSLT_AM 0x27 /* (I) lost selection (AM) */ 310 #define SBIC_CSR_MIS 0x28 /* (I) xfer aborted, ph mis */ 311 /* Terminated Interrupts */ 312 #define SBIC_CSR_CMD_INVALID 0x40 313 #define SBIC_CSR_DISC 0x41 /* (I) tgt disconnected */ 314 #define SBIC_CSR_SEL_TIMEO 0x42 315 #define SBIC_CSR_PE 0x43 /* parity error */ 316 #define SBIC_CSR_PE_ATN 0x44 /* ditto, ATN is asserted */ 317 #define SBIC_CSR_XLATE_TOOBIG 0x45 318 #define SBIC_CSR_RSLT_NOAM 0x46 /* (I) lost sel, no AM mode */ 319 #define SBIC_CSR_BAD_STATUS 0x47 /* status byte was nok */ 320 #define SBIC_CSR_MIS_1 0x48 /* ph mis, see low bits */ 321 /* Service Required Interrupts */ 322 #define SBIC_CSR_RSLT_NI 0x80 /* reselected, no ify msg */ 323 #define SBIC_CSR_RSLT_IFY 0x81 /* ditto, AM mode, got ify */ 324 #define SBIC_CSR_SLT 0x82 /* selected, no ATN */ 325 #define SBIC_CSR_SLT_ATN 0x83 /* selected with ATN */ 326 #define SBIC_CSR_ATN 0x84 /* (T) ATN asserted */ 327 #define SBIC_CSR_DISC_1 0x85 /* (I) bus is free */ 328 #define SBIC_CSR_UNK_GROUP 0x87 /* strange CDB1 */ 329 #define SBIC_CSR_MIS_2 0x88 /* (I) ph mis, see low bits */ 330 331 #define SBIC_PHASE(csr) SCSI_PHASE(csr) 332 333 /* 334 * Command register (command codes) 335 */ 336 #define SBIC_CMD_SBT 0x80 /* Single byte xfer qualifier */ 337 #define SBIC_CMD_MASK 0x7f 338 339 /* Miscellaneous */ 340 #define SBIC_CMD_RESET 0x00 /* (DTI) lev I */ 341 #define SBIC_CMD_ABORT 0x01 /* (DTI) lev I */ 342 #define SBIC_CMD_DISC 0x04 /* ( TI) lev I */ 343 #define SBIC_CMD_SSCC 0x0d /* ( TI) lev I */ 344 #define SBIC_CMD_SET_IDI 0x0f /* (DTI) lev I */ 345 #define SBIC_CMD_XLATE 0x18 /* (DT ) lev II */ 346 347 /* Initiator state */ 348 #define SBIC_CMD_SET_ATN 0x02 /* ( I) lev I */ 349 #define SBIC_CMD_CLR_ACK 0x03 /* ( I) lev I */ 350 #define SBIC_CMD_XFER_PAD 0x19 /* ( I) lev II */ 351 #define SBIC_CMD_XFER_INFO 0x20 /* ( I) lev II */ 352 353 /* Target state */ 354 #define SBIC_CMD_SND_DISC 0x0e /* ( T ) lev II */ 355 #define SBIC_CMD_RCV_CMD 0x10 /* ( T ) lev II */ 356 #define SBIC_CMD_RCV_DATA 0x11 /* ( T ) lev II */ 357 #define SBIC_CMD_RCV_MSG_OUT 0x12 /* ( T ) lev II */ 358 #define SBIC_CMD_RCV 0x13 /* ( T ) lev II */ 359 #define SBIC_CMD_SND_STATUS 0x14 /* ( T ) lev II */ 360 #define SBIC_CMD_SND_DATA 0x15 /* ( T ) lev II */ 361 #define SBIC_CMD_SND_MSG_IN 0x16 /* ( T ) lev II */ 362 #define SBIC_CMD_SND 0x17 /* ( T ) lev II */ 363 364 /* Disconnected state */ 365 #define SBIC_CMD_RESELECT 0x05 /* (D ) lev II */ 366 #define SBIC_CMD_SEL_ATN 0x06 /* (D ) lev II */ 367 #define SBIC_CMD_SEL 0x07 /* (D ) lev II */ 368 #define SBIC_CMD_SEL_ATN_XFER 0x08 /* (D I) lev II */ 369 #define SBIC_CMD_SEL_XFER 0x09 /* (D I) lev II */ 370 #define SBIC_CMD_RESELECT_RECV 0x0a /* (DT ) lev II */ 371 #define SBIC_CMD_RESELECT_SEND 0x0b /* (DT ) lev II */ 372 #define SBIC_CMD_WAIT_SEL_RECV 0x0c /* (DT ) lev II */ 373 374 375 #define PHASE_MASK 0x07 /* mask for psns/pctl phase */ 376 #define DATA_OUT_PHASE 0x00 377 #define DATA_IN_PHASE 0x01 378 #define CMD_PHASE 0x02 379 #define STATUS_PHASE 0x03 380 #define BUS_FREE_PHASE 0x04 381 #define ARB_SEL_PHASE 0x05 /* Fuji chip combines bus arb with sel. */ 382 #define MESG_OUT_PHASE 0x06 383 #define MESG_IN_PHASE 0x07 384 385 #define SCSI_PHASE(reg) ((reg) & PHASE_MASK) 386 387 #define SCSI_STATUS_MASK 0x3e /* Mask unused bits in status byte */ 388 389 /* 390 * WD33C93 has two registers: 391 * ASR - r : Aux Status Register, w : desired register no 392 * DATA - rw: register value 393 * 394 * We access them via separate handles because some people *cough*SGI*cough* 395 * like to keep them apart. 396 */ 397 398 #define wd33c93_read_reg(sc, regno, val) \ 399 do { \ 400 *(volatile uint8_t *)(sc)->sc_asr_regh = (regno); \ 401 (val) = *(volatile uint8_t *)(sc)->sc_data_regh; \ 402 } while (/* CONSTCOND */0) 403 404 #define wd33c93_write_reg(sc, regno, val) \ 405 do { \ 406 *(volatile uint8_t *)(sc)->sc_asr_regh = (regno); \ 407 *(volatile uint8_t *)(sc)->sc_data_regh = (val); \ 408 } while (/* CONSTCOND */0) 409 410 #define SET_SBIC_myid(sc,val) wd33c93_write_reg(sc,SBIC_myid,val) 411 #define GET_SBIC_myid(sc,val) wd33c93_read_reg(sc,SBIC_myid,val) 412 #define SET_SBIC_cdbsize(sc,val) wd33c93_write_reg(sc,SBIC_cdbsize,val) 413 #define GET_SBIC_cdbsize(sc,val) wd33c93_read_reg(sc,SBIC_cdbsize,val) 414 #define SET_SBIC_control(sc,val) wd33c93_write_reg(sc,SBIC_control,val) 415 #define GET_SBIC_control(sc,val) wd33c93_read_reg(sc,SBIC_control,val) 416 #define SET_SBIC_timeo(sc,val) wd33c93_write_reg(sc,SBIC_timeo,val) 417 #define GET_SBIC_timeo(sc,val) wd33c93_read_reg(sc,SBIC_timeo,val) 418 #define SET_SBIC_cdb1(sc,val) wd33c93_write_reg(sc,SBIC_cdb1,val) 419 #define GET_SBIC_cdb1(sc,val) wd33c93_read_reg(sc,SBIC_cdb1,val) 420 #define SET_SBIC_cdb2(sc,val) wd33c93_write_reg(sc,SBIC_cdb2,val) 421 #define GET_SBIC_cdb2(sc,val) wd33c93_read_reg(sc,SBIC_cdb2,val) 422 #define SET_SBIC_cdb3(sc,val) wd33c93_write_reg(sc,SBIC_cdb3,val) 423 #define GET_SBIC_cdb3(sc,val) wd33c93_read_reg(sc,SBIC_cdb3,val) 424 #define SET_SBIC_cdb4(sc,val) wd33c93_write_reg(sc,SBIC_cdb4,val) 425 #define GET_SBIC_cdb4(sc,val) wd33c93_read_reg(sc,SBIC_cdb4,val) 426 #define SET_SBIC_cdb5(sc,val) wd33c93_write_reg(sc,SBIC_cdb5,val) 427 #define GET_SBIC_cdb5(sc,val) wd33c93_read_reg(sc,SBIC_cdb5,val) 428 #define SET_SBIC_cdb6(sc,val) wd33c93_write_reg(sc,SBIC_cdb6,val) 429 #define GET_SBIC_cdb6(sc,val) wd33c93_read_reg(sc,SBIC_cdb6,val) 430 #define SET_SBIC_cdb7(sc,val) wd33c93_write_reg(sc,SBIC_cdb7,val) 431 #define GET_SBIC_cdb7(sc,val) wd33c93_read_reg(sc,SBIC_cdb7,val) 432 #define SET_SBIC_cdb8(sc,val) wd33c93_write_reg(sc,SBIC_cdb8,val) 433 #define GET_SBIC_cdb8(sc,val) wd33c93_read_reg(sc,SBIC_cdb8,val) 434 #define SET_SBIC_cdb9(sc,val) wd33c93_write_reg(sc,SBIC_cdb9,val) 435 #define GET_SBIC_cdb9(sc,val) wd33c93_read_reg(sc,SBIC_cdb9,val) 436 #define SET_SBIC_cdb10(sc,val) wd33c93_write_reg(sc,SBIC_cdb10,val) 437 #define GET_SBIC_cdb10(sc,val) wd33c93_read_reg(sc,SBIC_cdb10,val) 438 #define SET_SBIC_cdb11(sc,val) wd33c93_write_reg(sc,SBIC_cdb11,val) 439 #define GET_SBIC_cdb11(sc,val) wd33c93_read_reg(sc,SBIC_cdb11,val) 440 #define SET_SBIC_cdb12(sc,val) wd33c93_write_reg(sc,SBIC_cdb12,val) 441 #define GET_SBIC_cdb12(sc,val) wd33c93_read_reg(sc,SBIC_cdb12,val) 442 #define SET_SBIC_tlun(sc,val) wd33c93_write_reg(sc,SBIC_tlun,val) 443 #define GET_SBIC_tlun(sc,val) wd33c93_read_reg(sc,SBIC_tlun,val) 444 #define SET_SBIC_cmd_phase(sc,val) wd33c93_write_reg(sc,SBIC_cmd_phase,val) 445 #define GET_SBIC_cmd_phase(sc,val) wd33c93_read_reg(sc,SBIC_cmd_phase,val) 446 #define SET_SBIC_syn(sc,val) wd33c93_write_reg(sc,SBIC_syn,val) 447 #define GET_SBIC_syn(sc,val) wd33c93_read_reg(sc,SBIC_syn,val) 448 #define SET_SBIC_count_hi(sc,val) wd33c93_write_reg(sc,SBIC_count_hi,val) 449 #define GET_SBIC_count_hi(sc,val) wd33c93_read_reg(sc,SBIC_count_hi,val) 450 #define SET_SBIC_count_med(sc,val) wd33c93_write_reg(sc,SBIC_count_med,val) 451 #define GET_SBIC_count_med(sc,val) wd33c93_read_reg(sc,SBIC_count_med,val) 452 #define SET_SBIC_count_lo(sc,val) wd33c93_write_reg(sc,SBIC_count_lo,val) 453 #define GET_SBIC_count_lo(sc,val) wd33c93_read_reg(sc,SBIC_count_lo,val) 454 #define SET_SBIC_selid(sc,val) wd33c93_write_reg(sc,SBIC_selid,val) 455 #define GET_SBIC_selid(sc,val) wd33c93_read_reg(sc,SBIC_selid,val) 456 #define SET_SBIC_rselid(sc,val) wd33c93_write_reg(sc,SBIC_rselid,val) 457 #define GET_SBIC_rselid(sc,val) wd33c93_read_reg(sc,SBIC_rselid,val) 458 #define SET_SBIC_csr(sc,val) wd33c93_write_reg(sc,SBIC_csr,val) 459 #define GET_SBIC_csr(sc,val) wd33c93_read_reg(sc,SBIC_csr,val) 460 #define SET_SBIC_cmd(sc,val) wd33c93_write_reg(sc,SBIC_cmd,val) 461 #define GET_SBIC_cmd(sc,val) wd33c93_read_reg(sc,SBIC_cmd,val) 462 #define SET_SBIC_data(sc,val) wd33c93_write_reg(sc,SBIC_data,val) 463 #define GET_SBIC_data(sc,val) wd33c93_read_reg(sc,SBIC_data,val) 464 #define SET_SBIC_queue_tag(sc,val) wd33c93_write_reg(sc,SBIC_queue_tag,val) 465 #define GET_SBIC_queue_tag(sc,val) wd33c93_read_reg(sc,SBIC_queue_tag,val) 466 467 #define SBIC_TC_PUT(sc, val) \ 468 do { \ 469 wd33c93_write_reg(sc, SBIC_count_hi, ((val) >> 16)); \ 470 *(volatile uint8_t *)(sc)->sc_data_regh = (val) >> 8; \ 471 *(volatile uint8_t *)(sc)->sc_data_regh = (val); \ 472 } while (/* CONSTCOND */0) 473 474 #define GET_SBIC_asr(sc, val) \ 475 do { \ 476 (val) = *(volatile uint8_t *)(sc)->sc_asr_regh; \ 477 } while (/* CONSTCOND */0) 478 479 #define WAIT_CIP(sc) \ 480 do { \ 481 while (*(volatile uint8_t *)(sc)->sc_asr_regh & SBIC_ASR_CIP) \ 482 continue; \ 483 } while (/* CONSTCOND */0) 484 485 /* 486 * transmit a byte in programmed I/O mode 487 */ 488 #define SEND_BYTE(sc, ch) \ 489 do { \ 490 WAIT_CIP(sc); \ 491 SET_SBIC_cmd(sc, SBIC_CMD_SBT | SBIC_CMD_XFER_INFO); \ 492 SBIC_WAIT(sc, SBIC_ASR_DBR, 0); \ 493 SET_SBIC_data(sc, ch); \ 494 } while (/* CONSTCOND */0) 495 496 /* 497 * receive a byte in programmed I/O mode 498 */ 499 #define RECV_BYTE(sc, ch) \ 500 do { \ 501 WAIT_CIP(sc); \ 502 SET_SBIC_cmd(sc, SBIC_CMD_SBT | SBIC_CMD_XFER_INFO); \ 503 SBIC_WAIT(sc, SBIC_ASR_DBR, 0); \ 504 GET_SBIC_data(sc, ch); \ 505 } while (/* CONSTCOND */0) 506
Indexes created Tue Oct 07 21:09:53 GMT 2025