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shpcicvar.h revision 1.2 
      1 /*	$NetBSD: shpcicvar.h,v 1.2 2001/12/15 13:23:21 soren Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1997 Marc Horowitz.  All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  * 3. All advertising materials mentioning features or use of this software
     15  *    must display the following acknowledgement:
     16  *	This product includes software developed by Marc Horowitz.
     17  * 4. The name of the author may not be used to endorse or promote products
     18  *    derived from this software without specific prior written permission.
     19  *
     20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     21  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     22  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     23  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     26  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     27  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     29  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 struct proc;
     33 
     34 struct shpcic_event {
     35 	SIMPLEQ_ENTRY(shpcic_event) pe_q;
     36 	int pe_type;
     37 };
     38 
     39 /* pe_type */
     40 #define SHPCIC_EVENT_INSERTION	0
     41 #define SHPCIC_EVENT_REMOVAL	1
     42 
     43 struct shpcic_handle {
     44 	struct shpcic_softc *sc;
     45 	int	vendor;
     46 	int	sock;
     47 	int	flags;
     48 	int	laststate;
     49 	int	memalloc;
     50 	struct {
     51 		bus_addr_t	addr;
     52 		bus_size_t	size;
     53 		long		offset;
     54 		int		kind;
     55 	} mem[SHPCIC_MEM_WINS];
     56 	int	ioalloc;
     57 	struct {
     58 		bus_addr_t	addr;
     59 		bus_size_t	size;
     60 		int		width;
     61 	} io[SHPCIC_IO_WINS];
     62 	int	ih_irq;
     63 	struct device *pcmcia;
     64 
     65 	int	shutdown;
     66 	struct proc *event_thread;
     67 	SIMPLEQ_HEAD(, shpcic_event) events;
     68 };
     69 
     70 /* These four lines are MMTA specific */
     71 #define SHPCIC_IRQ1 10
     72 #define SHPCIC_IRQ2 9
     73 #define SHPCIC_SLOT1_ADDR 0xb8000000
     74 #define SHPCIC_SLOT2_ADDR 0xb9000000
     75 
     76 #define	SHPCIC_FLAG_SOCKETP	0x0001
     77 #define	SHPCIC_FLAG_CARDP		0x0002
     78 
     79 #define SHPCIC_LASTSTATE_PRESENT	0x0002
     80 #define SHPCIC_LASTSTATE_HALF		0x0001
     81 #define SHPCIC_LASTSTATE_EMPTY		0x0000
     82 
     83 #define	C0SA SHPCIC_CHIP0_BASE+SHPCIC_SOCKETA_INDEX
     84 #define	C0SB SHPCIC_CHIP0_BASE+SHPCIC_SOCKETB_INDEX
     85 #define	C1SA SHPCIC_CHIP1_BASE+SHPCIC_SOCKETA_INDEX
     86 #define	C1SB SHPCIC_CHIP1_BASE+SHPCIC_SOCKETB_INDEX
     87 
     88 /*
     89  * This is sort of arbitrary.  It merely needs to be "enough". It can be
     90  * overridden in the conf file, anyway.
     91  */
     92 
     93 #define	SHPCIC_MEM_PAGES	4
     94 #define	SHPCIC_MEMSIZE	SHPCIC_MEM_PAGES*SHPCIC_MEM_PAGESIZE
     95 
     96 #define	SHPCIC_NSLOTS	4
     97 
     98 #define SHPCIC_WINS     5
     99 #define SHPCIC_IOWINS     2
    100 
    101 struct shpcic_softc {
    102 	struct device dev;
    103 
    104 	bus_space_tag_t memt;
    105 	bus_space_handle_t memh;
    106 	bus_space_tag_t iot;
    107 	bus_space_handle_t ioh;
    108 
    109 	/* XXX isa_chipset_tag_t, pci_chipset_tag_t, etc. */
    110 	void	*intr_est;
    111 
    112 	pcmcia_chipset_tag_t pct;
    113 
    114 	/* this needs to be large enough to hold PCIC_MEM_PAGES bits */
    115 	int	subregionmask;
    116 #define SHPCIC_MAX_MEM_PAGES (8 * sizeof(int))
    117 
    118 	/* used by memory window mapping functions */
    119 	bus_addr_t membase;
    120 
    121 	/*
    122 	 * used by io window mapping functions.  These can actually overlap
    123 	 * with another pcic, since the underlying extent mapper will deal
    124 	 * with individual allocations.  This is here to deal with the fact
    125 	 * that different busses have different real widths (different pc
    126 	 * hardware seems to use 10 or 12 bits for the I/O bus).
    127 	 */
    128 	bus_addr_t iobase;
    129 	bus_addr_t iosize;
    130 
    131 	int	irq;
    132 	void	*ih;
    133 
    134 	struct shpcic_handle handle[SHPCIC_NSLOTS];
    135 };
    136 
    137 
    138 int	shpcic_ident_ok __P((int));
    139 int	shpcic_vendor __P((struct shpcic_handle *));
    140 char	*shpcic_vendor_to_string __P((int));
    141 
    142 void	shpcic_attach __P((struct shpcic_softc *));
    143 void	shpcic_attach_sockets __P((struct shpcic_softc *));
    144 int	shpcic_intr __P((void *arg));
    145 
    146 static inline int shpcic_read __P((struct shpcic_handle *, int));
    147 static inline void shpcic_write __P((struct shpcic_handle *, int, int));
    148 
    149 int	shpcic_chip_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t,
    150 	    struct pcmcia_mem_handle *));
    151 void	shpcic_chip_mem_free __P((pcmcia_chipset_handle_t,
    152 	    struct pcmcia_mem_handle *));
    153 int	shpcic_chip_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t,
    154 	    bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *));
    155 void	shpcic_chip_mem_unmap __P((pcmcia_chipset_handle_t, int));
    156 
    157 int	shpcic_chip_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t,
    158 	    bus_size_t, bus_size_t, struct pcmcia_io_handle *));
    159 void	shpcic_chip_io_free __P((pcmcia_chipset_handle_t,
    160 	    struct pcmcia_io_handle *));
    161 int	shpcic_chip_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t,
    162 	    bus_size_t, struct pcmcia_io_handle *, int *));
    163 void	shpcic_chip_io_unmap __P((pcmcia_chipset_handle_t, int));
    164 
    165 void	shpcic_chip_socket_enable __P((pcmcia_chipset_handle_t));
    166 void	shpcic_chip_socket_disable __P((pcmcia_chipset_handle_t));
    167 
    168 static __inline int shpcic_read __P((struct shpcic_handle *, int));
    169 static __inline int
    170 shpcic_read(h, idx)
    171 	struct shpcic_handle *h;
    172 	int idx;
    173 {
    174 	static int prev_idx = 0;
    175 
    176 	if (idx == -1){
    177 		idx = prev_idx;
    178 	}
    179 	prev_idx = idx;
    180 	return (bus_space_read_stream_2(h->sc->iot, h->sc->ioh, idx));
    181 }
    182 
    183 static __inline void shpcic_write __P((struct shpcic_handle *, int, int));
    184 static __inline void
    185 shpcic_write(h, idx, data)
    186 	struct shpcic_handle *h;
    187 	int idx;
    188 	int data;
    189 {
    190 	static int prev_idx;
    191 	if (idx == -1){
    192 		idx = prev_idx;
    193 	}
    194 	prev_idx = idx;
    195 	bus_space_write_stream_2(h->sc->iot, h->sc->ioh, idx, (data));
    196 }
    197 
    198 void	*pcic_shb_chip_intr_establish __P((pcmcia_chipset_handle_t,
    199 	    struct pcmcia_function *, int, int (*) (void *), void *));
    200 void	pcic_shb_chip_intr_disestablish __P((pcmcia_chipset_handle_t, void *));
    201 void pcic_shb_bus_width_probe __P((struct shpcic_softc *, bus_space_tag_t,
    202 				   bus_space_handle_t, bus_addr_t, u_int32_t));
    203