shpcicvar.h revision 1.5
1 /* $NetBSD: shpcicvar.h,v 1.5 2005/08/16 11:32:26 nonaka Exp $ */ 2 3 /*- 4 * Copyright (c) 2005 NONAKA Kimihiro 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _SH3_SHPCICVAR_H_ 30 #define _SH3_SHPCICVAR_H_ 31 32 #include <machine/bus.h> 33 34 bus_space_tag_t shpcic_get_bus_io_tag(void); 35 bus_space_tag_t shpcic_get_bus_mem_tag(void); 36 bus_dma_tag_t shpcic_get_bus_dma_tag(void); 37 38 int shpcic_bus_maxdevs(void *v, int busno); 39 pcitag_t shpcic_make_tag(void *v, int bus, int device, int function); 40 void shpcic_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp); 41 pcireg_t shpcic_conf_read(void *v, pcitag_t tag, int reg); 42 void shpcic_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data); 43 44 int shpcic_set_intr_priority(int intr, int level); 45 void *shpcic_intr_establish(int evtcode, int (*ih_func)(void *), void *ih_arg); 46 void shpcic_intr_disestablish(void *ih); 47 48 /* 49 * shpcic io/mem bus space 50 */ 51 int shpcic_iomem_map(void *v, bus_addr_t bpa, bus_size_t size, int flags, 52 bus_space_handle_t *bshp); 53 void shpcic_iomem_unmap(void *v, bus_space_handle_t bsh, bus_size_t size); 54 int shpcic_iomem_subregion(void *v, bus_space_handle_t bsh, bus_size_t offset, 55 bus_size_t size, bus_space_handle_t *nbshp); 56 int shpcic_iomem_alloc(void *v, bus_addr_t rstart, bus_addr_t rend, 57 bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags, 58 bus_addr_t *bpap, bus_space_handle_t *bshp); 59 void shpcic_iomem_free(void *v, bus_space_handle_t bsh, bus_size_t size); 60 61 /* read single */ 62 uint8_t shpcic_io_read_1(void *v, bus_space_handle_t bsh, bus_size_t offset); 63 uint16_t shpcic_io_read_2(void *v, bus_space_handle_t bsh, bus_size_t offset); 64 uint32_t shpcic_io_read_4(void *v, bus_space_handle_t bsh, bus_size_t offset); 65 uint8_t shpcic_mem_read_1(void *v, bus_space_handle_t bsh, bus_size_t offset); 66 uint16_t shpcic_mem_read_2(void *v, bus_space_handle_t bsh, bus_size_t offset); 67 uint32_t shpcic_mem_read_4(void *v, bus_space_handle_t bsh, bus_size_t offset); 68 69 /* read multi */ 70 void shpcic_io_read_multi_1(void *v, bus_space_handle_t bsh, 71 bus_size_t offset, uint8_t *addr, bus_size_t count); 72 void shpcic_io_read_multi_2(void *v, bus_space_handle_t bsh, 73 bus_size_t offset, uint16_t *addr, bus_size_t count); 74 void shpcic_io_read_multi_4(void *v, bus_space_handle_t bsh, 75 bus_size_t offset, uint32_t *addr, bus_size_t count); 76 void shpcic_mem_read_multi_1(void *v, bus_space_handle_t bsh, 77 bus_size_t offset, uint8_t *addr, bus_size_t count); 78 void shpcic_mem_read_multi_2(void *v, bus_space_handle_t bsh, 79 bus_size_t offset, uint16_t *addr, bus_size_t count); 80 void shpcic_mem_read_multi_4(void *v, bus_space_handle_t bsh, 81 bus_size_t offset, uint32_t *addr, bus_size_t count); 82 83 /* read region */ 84 void shpcic_io_read_region_1(void *v, bus_space_handle_t bsh, 85 bus_size_t offset, uint8_t *addr, bus_size_t count); 86 void shpcic_io_read_region_2(void *v, bus_space_handle_t bsh, 87 bus_size_t offset, uint16_t *addr, bus_size_t count); 88 void shpcic_io_read_region_4(void *v, bus_space_handle_t bsh, 89 bus_size_t offset, uint32_t *addr, bus_size_t count); 90 void shpcic_mem_read_region_1(void *v, bus_space_handle_t bsh, 91 bus_size_t offset, uint8_t *addr, bus_size_t count); 92 void shpcic_mem_read_region_2(void *v, bus_space_handle_t bsh, 93 bus_size_t offset, uint16_t *addr, bus_size_t count); 94 void shpcic_mem_read_region_4(void *v, bus_space_handle_t bsh, 95 bus_size_t offset, uint32_t *addr, bus_size_t count); 96 97 /* write single */ 98 void shpcic_io_write_1(void *v, bus_space_handle_t bsh, 99 bus_size_t offset, uint8_t data); 100 void shpcic_io_write_2(void *v, bus_space_handle_t bsh, 101 bus_size_t offset, uint16_t data); 102 void shpcic_io_write_4(void *v, bus_space_handle_t bsh, 103 bus_size_t offset, uint32_t data); 104 void shpcic_mem_write_1(void *v, bus_space_handle_t bsh, 105 bus_size_t offset, uint8_t data); 106 void shpcic_mem_write_2(void *v, bus_space_handle_t bsh, 107 bus_size_t offset, uint16_t data); 108 void shpcic_mem_write_4(void *v, bus_space_handle_t bsh, 109 bus_size_t offset, uint32_t data); 110 111 /* write multi */ 112 void shpcic_io_write_multi_1(void *v, bus_space_handle_t bsh, 113 bus_size_t offset, const uint8_t *addr, bus_size_t count); 114 void shpcic_io_write_multi_2(void *v, bus_space_handle_t bsh, 115 bus_size_t offset, const uint16_t *addr, bus_size_t count); 116 void shpcic_io_write_multi_4(void *v, bus_space_handle_t bsh, 117 bus_size_t offset, const uint32_t *addr, bus_size_t count); 118 void shpcic_mem_write_multi_1(void *v, bus_space_handle_t bsh, 119 bus_size_t offset, const uint8_t *addr, bus_size_t count); 120 void shpcic_mem_write_multi_2(void *v, bus_space_handle_t bsh, 121 bus_size_t offset, const uint16_t *addr, bus_size_t count); 122 void shpcic_mem_write_multi_4(void *v, bus_space_handle_t bsh, 123 bus_size_t offset, const uint32_t *addr, bus_size_t count); 124 125 /* write region */ 126 void shpcic_io_write_region_1(void *v, bus_space_handle_t bsh, 127 bus_size_t offset, const uint8_t *addr, bus_size_t count); 128 void shpcic_io_write_region_2(void *v, bus_space_handle_t bsh, 129 bus_size_t offset, const uint16_t *addr, bus_size_t count); 130 void shpcic_io_write_region_4(void *v, bus_space_handle_t bsh, 131 bus_size_t offset, const uint32_t *addr, bus_size_t count); 132 void shpcic_mem_write_region_1(void *v, bus_space_handle_t bsh, 133 bus_size_t offset, const uint8_t *addr, bus_size_t count); 134 void shpcic_mem_write_region_2(void *v, bus_space_handle_t bsh, 135 bus_size_t offset, const uint16_t *addr, bus_size_t count); 136 void shpcic_mem_write_region_4(void *v, bus_space_handle_t bsh, 137 bus_size_t offset, const uint32_t *addr, bus_size_t count); 138 139 /* set multi */ 140 void shpcic_io_set_multi_1(void *v, bus_space_handle_t bsh, 141 bus_size_t offset, uint8_t val, bus_size_t count); 142 void shpcic_io_set_multi_2(void *v, bus_space_handle_t bsh, 143 bus_size_t offset, uint16_t val, bus_size_t count); 144 void shpcic_io_set_multi_4(void *v, bus_space_handle_t bsh, 145 bus_size_t offset, uint32_t val, bus_size_t count); 146 void shpcic_mem_set_multi_1(void *v, bus_space_handle_t bsh, 147 bus_size_t offset, uint8_t val, bus_size_t count); 148 void shpcic_mem_set_multi_2(void *v, bus_space_handle_t bsh, 149 bus_size_t offset, uint16_t val, bus_size_t count); 150 void shpcic_mem_set_multi_4(void *v, bus_space_handle_t bsh, 151 bus_size_t offset, uint32_t val, bus_size_t count); 152 153 /* set region */ 154 void shpcic_io_set_region_1(void *v, bus_space_handle_t bsh, 155 bus_size_t offset, uint8_t val, bus_size_t count); 156 void shpcic_io_set_region_2(void *v, bus_space_handle_t bsh, 157 bus_size_t offset, uint16_t val, bus_size_t count); 158 void shpcic_io_set_region_4(void *v, bus_space_handle_t bsh, 159 bus_size_t offset, uint32_t val, bus_size_t count); 160 void shpcic_mem_set_region_1(void *v, bus_space_handle_t bsh, 161 bus_size_t offset, uint8_t val, bus_size_t count); 162 void shpcic_mem_set_region_2(void *v, bus_space_handle_t bsh, 163 bus_size_t offset, uint16_t val, bus_size_t count); 164 void shpcic_mem_set_region_4(void *v, bus_space_handle_t bsh, 165 bus_size_t offset, uint32_t val, bus_size_t count); 166 167 /* copy region */ 168 void shpcic_io_copy_region_1(void *v, bus_space_handle_t bsh1, 169 bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, 170 bus_size_t count); 171 void shpcic_io_copy_region_2(void *v, bus_space_handle_t bsh1, 172 bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, 173 bus_size_t count); 174 void shpcic_io_copy_region_4(void *v, bus_space_handle_t bsh1, 175 bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, 176 bus_size_t count); 177 void shpcic_mem_copy_region_1(void *v, bus_space_handle_t bsh1, 178 bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, 179 bus_size_t count); 180 void shpcic_mem_copy_region_2(void *v, bus_space_handle_t bsh1, 181 bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, 182 bus_size_t count); 183 void shpcic_mem_copy_region_4(void *v, bus_space_handle_t bsh1, 184 bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, 185 bus_size_t count); 186 187 #endif /* _SH3_SHPCICVAR_H_ */ 188
Indexes created Mon Oct 13 08:09:50 GMT 2025