sh3/include/bscreg.h

1.1   itojun /* $NetBSD: bscreg.h,v 1.2 1999/09/16 21:15:36 msaitoh Exp $ */
1.1   itojun
1.1   itojun /*-
1.1   itojun  * Copyright (C) 1999 SAITOH Masanobu.  All rights reserved.
1.1   itojun  *
1.1   itojun  * Redistribution and use in source and binary forms, with or without
1.1   itojun  * modification, are permitted provided that the following conditions
1.1   itojun  * are met:
1.1   itojun  * 1. Redistributions of source code must retain the above copyright
1.1   itojun  *    notice, this list of conditions and the following disclaimer.
1.1   itojun  * 2. Redistributions in binary form must reproduce the above copyright
1.1   itojun  *    notice, this list of conditions and the following disclaimer in the
1.1   itojun  *    documentation and/or other materials provided with the distribution.
1.1   itojun  * 3. The name of the author may not be used to endorse or promote products
1.1   itojun  *    derived from this software without specific prior written permission.
1.1   itojun  *
1.1   itojun  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
1.1   itojun  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
1.1   itojun  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
1.1   itojun  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1.1   itojun  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1.1   itojun  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
1.1   itojun  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
1.1   itojun  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1.1   itojun  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
1.1   itojun  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1.1   itojun  */
1.1   itojun
1.1   itojun #ifndef _SH3_BSCREG_H_
1.1   itojun #define _SH3_BSCREG_H_
1.1   itojun
1.1   itojun /*
1.1   itojun  * Bus State Controller
1.1   itojun  */
1.1   itojun
1.1   itojun #if !defined(SH4)
1.1   itojun
1.1   itojun /* SH3 definitions */
1.1   itojun
1.2  msaitoh #define SHREG_BCR1	(*(volatile unsigned short *)	0xffffff60)
1.2  msaitoh #define SHREG_BCR2	(*(volatile unsigned short *)	0xffffff62)
1.2  msaitoh #define SHREG_WCR1	(*(volatile unsigned short *)	0xffffff64)
1.2  msaitoh #define SHREG_WCR2	(*(volatile unsigned short *)	0xffffff66)
1.2  msaitoh #define SHREG_MCR	(*(volatile unsigned short *)	0xffffff68)
1.2  msaitoh #define SHREG_DCR	(*(volatile unsigned short *)	0xffffff6a)
1.2  msaitoh #define SHREG_PCR	(*(volatile unsigned short *)	0xffffff6c)
1.2  msaitoh #define SHREG_RTCSR	(*(volatile unsigned short *)	0xffffff6e)
1.2  msaitoh #define SHREG_RTCNT	(*(volatile unsigned short *)	0xffffff70)
1.2  msaitoh #define SHREG_RTCOR	(*(volatile unsigned short *)	0xffffff72)
1.2  msaitoh #define SHREG_RFCR	(*(volatile unsigned short *)	0xffffff74)
1.2  msaitoh #define SHREG_BCR3	(*(volatile unsigned short *)	0xffffff7e)
1.1   itojun
1.1   itojun #else
1.1   itojun
1.1   itojun /* SH4 definitions */
1.1   itojun
1.2  msaitoh #define SHREG_BCR1	(*(volatile unsigned int *)	0xff800000)
1.2  msaitoh #define SHREG_BCR2	(*(volatile unsigned short *)	0xff800004)
1.2  msaitoh #define SHREG_WCR1	(*(volatile unsigned int *)	0xff800008)
1.2  msaitoh #define SHREG_WCR2	(*(volatile unsigned int *)	0xff80000c)
1.2  msaitoh #define SHREG_WCR3	(*(volatile unsigned int *)	0xff800010)
1.2  msaitoh #define SHREG_MCR	(*(volatile unsigned int *)	0xff800014)
1.2  msaitoh #define SHREG_PCR	(*(volatile unsigned short *)	0xff800018)
1.2  msaitoh #define SHREG_RTCSR	(*(volatile unsigned short *)	0xff80001c)
1.2  msaitoh #define SHREG_RTCNT	(*(volatile unsigned short *)	0xff800020)
1.2  msaitoh #define SHREG_RTCOR	(*(volatile unsigned short *)	0xff800024)
1.2  msaitoh #define SHREG_RFCR	(*(volatile unsigned short *)	0xff800028)
1.1   itojun
1.1   itojun #endif
1.1   itojun #endif	/* !_SH3_BSCREG_H_ */