bscreg.h revision 1.1
1 /* $NetBSD: bscreg.h,v 1.1 1999/09/13 10:31:14 itojun Exp $ */ 2 3 /*- 4 * Copyright (C) 1999 SAITOH Masanobu. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef _SH3_BSCREG_H_ 30 #define _SH3_BSCREG_H_ 31 32 #ifndef BYTE_ORDER 33 #error Define BYTE_ORDER! 34 #endif 35 36 /* 37 * Bus State Controller 38 */ 39 40 #if !defined(SH4) 41 42 /* SH3 definitions */ 43 44 struct sh3_bsc { 45 /* Bus Control Register 1 (0xffffff60) */ 46 union { 47 unsigned short WORD; /* Word Access */ 48 struct { /* Bit Access */ 49 #if BYTE_ORDER == BIG_ENDIAN 50 /* Bit 15..0 */ 51 unsigned short :3; 52 unsigned short HIZCNT :1; 53 unsigned short ENDIAN :1; 54 unsigned short A0BST1 :1; 55 unsigned short A0BST0 :1; 56 unsigned short A5BST1 :1; 57 unsigned short A5BST0 :1; 58 unsigned short A6BST1 :1; 59 unsigned short A6BST0 :1; 60 unsigned short DRAMTP2:1; 61 unsigned short DRAMTP1:1; 62 unsigned short DRAMTP0:1; 63 unsigned short A5PCM :1; 64 unsigned short A6PCM :1; 65 #else /* BYTE_ORDER == LITTLE_ENDIAN */ 66 /* Bit 0..15 */ 67 unsigned short A6PCM :1; 68 unsigned short A5PCM :1; 69 unsigned short DRAMTP0:1; 70 unsigned short DRAMTP1:1; 71 unsigned short DRAMTP2:1; 72 unsigned short A6BST0 :1; 73 unsigned short A6BST1 :1; 74 unsigned short A5BST0 :1; 75 unsigned short A5BST1 :1; 76 unsigned short A0BST0 :1; 77 unsigned short A0BST1 :1; 78 unsigned short ENDIAN :1; 79 unsigned short HIZCNT :1; 80 unsigned short :3; 81 #endif 82 } BIT; 83 } BCR1; 84 85 /* Bus Control Register 2 (0xffffff62) */ 86 union { /* BCR */ 87 unsigned short WORD; /* Word Access */ 88 struct { /* Bit Access */ 89 #if BYTE_ORDER == BIG_ENDIAN 90 /* Bit 15..0 */ 91 unsigned short :2; 92 unsigned short A6SZ1 :1; 93 unsigned short A6SZ0 :1; 94 unsigned short A5SZ1 :1; 95 unsigned short A5SZ0 :1; 96 unsigned short A4SZ1 :1; 97 unsigned short A4SZ0 :1; 98 unsigned short A3SZ1 :1; 99 unsigned short A3SZ0 :1; 100 unsigned short A2SZ1 :1; 101 unsigned short A2SZ0 :1; 102 unsigned short A1SZ1 :1; 103 unsigned short A1SZ0 :1; 104 unsigned short :1; 105 unsigned short PORTBN :1; 106 #else /* BYTE_ORDER == LITTLE_ENDIAN */ 107 /* Bit 0..15 */ 108 unsigned short PORTBN :1; 109 unsigned short :1; 110 unsigned short A1SZ0 :1; 111 unsigned short A1SZ1 :1; 112 unsigned short A2SZ0 :1; 113 unsigned short A2SZ1 :1; 114 unsigned short A3SZ0 :1; 115 unsigned short A3SZ1 :1; 116 unsigned short A4SZ0 :1; 117 unsigned short A4SZ1 :1; 118 unsigned short A5SZ0 :1; 119 unsigned short A5SZ1 :1; 120 unsigned short A6SZ0 :1; 121 unsigned short A6SZ1 :1; 122 unsigned short :2; 123 #endif 124 } BIT; 125 } BCR2; 126 127 /* Wait state Control Register 1 (0xffffff64) */ 128 union { 129 unsigned short WORD; /* Word Access */ 130 struct { /* Bit Access */ 131 #if BYTE_ORDER == BIG_ENDIAN 132 /* Bit 15..0 */ 133 unsigned short :2; 134 unsigned short A6IW1 :1; 135 unsigned short A6IW0 :1; 136 unsigned short A5IW1 :1; 137 unsigned short A5IW0 :1; 138 unsigned short A4IW1 :1; 139 unsigned short A4IW0 :1; 140 unsigned short A3IW1 :1; 141 unsigned short A3IW0 :1; 142 unsigned short A2IW1 :1; 143 unsigned short A2IW0 :1; 144 unsigned short A1IW1 :1; 145 unsigned short A1IW0 :1; 146 unsigned short A0IW1 :1; 147 unsigned short A0IW0 :1; 148 #else /* BYTE_ORDER == LITTLE_ENDIAN */ 149 /* Bit 0..15 */ 150 unsigned short A0IW0 :1; 151 unsigned short A0IW1 :1; 152 unsigned short A1IW0 :1; 153 unsigned short A1IW1 :1; 154 unsigned short A2IW0 :1; 155 unsigned short A2IW1 :1; 156 unsigned short A3IW0 :1; 157 unsigned short A3IW1 :1; 158 unsigned short A4IW0 :1; 159 unsigned short A4IW1 :1; 160 unsigned short A5IW0 :1; 161 unsigned short A5IW1 :1; 162 unsigned short A6IW0 :1; 163 unsigned short A6IW1 :1; 164 unsigned short :2; 165 #endif 166 } BIT; 167 } WCR1; 168 169 /* Wait state Control Register 2 (0xffffff66) */ 170 union { 171 unsigned short WORD; /* Word Access */ 172 struct { /* Bit Access */ 173 #if BYTE_ORDER == BIG_ENDIAN 174 /* Bit 15..0 */ 175 unsigned short A6W2 :1; 176 unsigned short A6W1 :1; 177 unsigned short A6W0 :1; 178 unsigned short A5W2 :1; 179 unsigned short A5W1 :1; 180 unsigned short A5W0 :1; 181 unsigned short A4W2 :1; 182 unsigned short A4W1 :1; 183 unsigned short A4W0 :1; 184 unsigned short A3W1 :1; 185 unsigned short A3W0 :1; 186 unsigned short A21W1 :1; 187 unsigned short A21W0 :1; 188 unsigned short A0W2 :1; 189 unsigned short A0W1 :1; 190 unsigned short A0W0 :1; 191 #else /* BYTE_ORDER == LITTLE_ENDIAN */ 192 /* Bit 0..15 */ 193 unsigned short A0W0 :1; 194 unsigned short A0W1 :1; 195 unsigned short A0W2 :1; 196 unsigned short A21W0 :1; 197 unsigned short A21W1 :1; 198 unsigned short A3W0 :1; 199 unsigned short A3W1 :1; 200 unsigned short A4W0 :1; 201 unsigned short A4W1 :1; 202 unsigned short A4W2 :1; 203 unsigned short A5W0 :1; 204 unsigned short A5W1 :1; 205 unsigned short A5W2 :1; 206 unsigned short A6W0 :1; 207 unsigned short A6W1 :1; 208 unsigned short A6W2 :1; 209 #endif 210 } BIT; 211 } WCR2; 212 213 /* Memory Control Register (0xffffff68) */ 214 union { 215 unsigned short WORD; /* Word Access */ 216 struct { /* Bit Access */ 217 #if BYTE_ORDER == BIG_ENDIAN 218 /* Bit 15..0 */ 219 unsigned short TPC1 :1; 220 unsigned short TPC0 :1; 221 unsigned short RCD1 :1; 222 unsigned short RCD0 :1; 223 unsigned short TRWL1 :1; 224 unsigned short TRWL0 :1; 225 unsigned short TRAS1 :1; 226 unsigned short TRAS0 :1; 227 unsigned short :1; 228 unsigned short BE :1; 229 unsigned short SZ :1; 230 unsigned short AMX1 :1; 231 unsigned short AMX0 :1; 232 unsigned short RFSH :1; 233 unsigned short RMODE :1; 234 unsigned short EDOMD :1; 235 #else /* BYTE_ORDER == LITTLE_ENDIAN */ 236 /* Bit 0..15 */ 237 unsigned short EDOMD :1; 238 unsigned short RMODE :1; 239 unsigned short RFSH :1; 240 unsigned short AMX0 :1; 241 unsigned short AMX1 :1; 242 unsigned short SZ :1; 243 unsigned short BE :1; 244 unsigned short :1; 245 unsigned short TRAS0 :1; 246 unsigned short TRAS1 :1; 247 unsigned short TRWL0 :1; 248 unsigned short TRWL1 :1; 249 unsigned short RCD0 :1; 250 unsigned short RCD1 :1; 251 unsigned short TPC0 :1; 252 unsigned short TPC1 :1; 253 #endif 254 } BIT; 255 } MCR; 256 257 /* Dram Control Register (0xffffff6a) */ 258 union { 259 unsigned short WORD; /* Word Access */ 260 struct { /* Bit Access */ 261 #if BYTE_ORDER == BIG_ENDIAN 262 /* Bit 15..0 */ 263 unsigned short TPC1 :1; 264 unsigned short TPC0 :1; 265 unsigned short RCD1 :1; 266 unsigned short RCD0 :1; 267 unsigned short :2; 268 unsigned short TRAS1 :1; 269 unsigned short TRAS0 :1; 270 unsigned short :1; 271 unsigned short BE :1; 272 unsigned short :1; 273 unsigned short AMX1 :1; 274 unsigned short AMX0 :1; 275 unsigned short RFSH :1; 276 unsigned short RMODE :1; 277 unsigned short :1; 278 #else /* BYTE_ORDER == LITTLE_ENDIAN */ 279 /* Bit 0..15 */ 280 unsigned short :1; 281 unsigned short RMODE :1; 282 unsigned short RFSH :1; 283 unsigned short AMX0 :1; 284 unsigned short AMX1 :1; 285 unsigned short :1; 286 unsigned short BE :1; 287 unsigned short :1; 288 unsigned short TRAS0 :1; 289 unsigned short TRAS1 :1; 290 unsigned short :2; 291 unsigned short RCD0 :1; 292 unsigned short RCD1 :1; 293 unsigned short TPC0 :1; 294 unsigned short TPC1 :1; 295 #endif 296 } BIT; 297 } DCR; 298 299 /* PCMCIA Control Register (0xffffff6c) */ 300 union { 301 unsigned short WORD; /* Word Access */ 302 struct { /* Bit Access */ 303 #if BYTE_ORDER == BIG_ENDIAN 304 /* Bit 15..0 */ 305 unsigned short :8; 306 unsigned short A5TED1 :1; 307 unsigned short A5TED0 :1; 308 unsigned short A6TED1 :1; 309 unsigned short A6TED0 :1; 310 unsigned short A5TEH1 :1; 311 unsigned short A5TEH0 :1; 312 unsigned short A6TEH1 :1; 313 unsigned short A6TEH0 :1; 314 #else /* BYTE_ORDER == LITTLE_ENDIAN */ 315 /* Bit 0..15 */ 316 unsigned short A6TEH0 :1; 317 unsigned short A6TEH1 :1; 318 unsigned short A5TEH0 :1; 319 unsigned short A5TEH1 :1; 320 unsigned short A6TED0 :1; 321 unsigned short A6TED1 :1; 322 unsigned short A5TED0 :1; 323 unsigned short A5TED1 :1; 324 unsigned short :8; 325 #endif 326 } BIT; 327 } PCR; 328 329 /* Refresh Timer Control/Status Register (0xffffff6e) */ 330 union { 331 unsigned short WORD; /* Word Access */ 332 struct { /* Bit Access */ 333 #if BYTE_ORDER == BIG_ENDIAN 334 /* Bit 15..0 */ 335 unsigned short :8; 336 unsigned short CMF :1; 337 unsigned short CMIE :1; 338 unsigned short CKS2 :1; 339 unsigned short CKS1 :1; 340 unsigned short CKS0 :1; 341 unsigned short OVF :1; 342 unsigned short OVIE :1; 343 unsigned short LMTS :1; 344 #else /* BYTE_ORDER == LITTLE_ENDIAN */ 345 /* Bit 0..15 */ 346 unsigned short LMTS :1; 347 unsigned short OVIE :1; 348 unsigned short OVF :1; 349 unsigned short CKS0 :1; 350 unsigned short CKS1 :1; 351 unsigned short CKS2 :1; 352 unsigned short CMIE :1; 353 unsigned short CMF :1; 354 unsigned short :8; 355 #endif 356 } BIT; 357 } RTCSR; 358 359 /* Refresh Timer CouNTer (0xffffff70) */ 360 unsigned short RTCNT; 361 362 /* Refresh Time Constant cOunteR (0xffffff72) */ 363 unsigned short RTCOR; 364 365 /* Refresh Count Register (0xffffff74) */ 366 unsigned short RFCR; 367 }; 368 369 /* BSC Address */ 370 #define SHREG_BSC (*(volatile struct sh3_bsc *) 0xFFFFFF60) 371 372 #else 373 374 /* SH4 definitions */ 375 376 struct sh3_bsc { 377 /* Bus Control Register 1 0xff800000) */ 378 union { 379 unsigned int WORD; /* Word Access */ 380 struct { /* Bit Access */ 381 #if BYTE_ORDER == BIG_ENDIAN 382 /* Bit 31..0 */ 383 unsigned int ENDIAN :1; 384 unsigned int MASTER :1; 385 unsigned int A0MPX :1; 386 unsigned int :3; 387 unsigned int IPUP :1; 388 unsigned int OPUP :1; 389 unsigned int :2; 390 unsigned int A1MBC :1; 391 unsigned int A4MBC :1; 392 unsigned int BREQEN :1; 393 unsigned int PSHR :1; 394 unsigned int MEMMPX :1; 395 unsigned int :1; 396 unsigned int HIZMEM :1; 397 unsigned int HIZCNT :1; 398 unsigned int A0BST2 :1; 399 unsigned int A0BST1 :1; 400 unsigned int A0BST0 :1; 401 unsigned int A5BST2 :1; 402 unsigned int A5BST1 :1; 403 unsigned int A5BST0 :1; 404 unsigned int A6BST2 :1; 405 unsigned int A6BST1 :1; 406 unsigned int A6BST0 :1; 407 unsigned int DRAMTP2 :1; 408 unsigned int DRAMTP1 :1; 409 unsigned int DRAMTP0 :1; 410 unsigned int :1; 411 unsigned int A56PCM :1; 412 #else /* BYTE_ORDER == LITTLE_ENDIAN */ 413 /* Bit 0..31 */ 414 unsigned int A56PCM :1; 415 unsigned int :1; 416 unsigned int DRAMTP0 :1; 417 unsigned int DRAMTP1 :1; 418 unsigned int DRAMTP2 :1; 419 unsigned int A6BST0 :1; 420 unsigned int A6BST1 :1; 421 unsigned int A6BST2 :1; 422 unsigned int A5BST0 :1; 423 unsigned int A5BST1 :1; 424 unsigned int A5BST2 :1; 425 unsigned int A0BST0 :1; 426 unsigned int A0BST1 :1; 427 unsigned int A0BST2 :1; 428 unsigned int HIZCNT :1; 429 unsigned int HIZMEM :1; 430 unsigned int :1; 431 unsigned int MEMMPX :1; 432 unsigned int PSHR :1; 433 unsigned int BREQEN :1; 434 unsigned int A4MBC :1; 435 unsigned int A1MBC :1; 436 unsigned int :2; 437 unsigned int OPUP :1; 438 unsigned int IPUP :1; 439 unsigned int :3; 440 unsigned int A0MPX :1; 441 unsigned int MASTER :1; 442 unsigned int ENDIAN :1; 443 #endif 444 } BIT; 445 } BCR1; 446 447 /* Bus Control Register 2 0xff800004) */ 448 union { 449 unsigned short WORD; /* Word Access */ 450 struct { /* Bit Access */ 451 #if BYTE_ORDER == BIG_ENDIAN 452 /* Bit 15..0 */ 453 unsigned short A0SZ1 :1; 454 unsigned short A0SZ0 :1; 455 unsigned short A6SZ1 :1; 456 unsigned short A6SZ0 :1; 457 unsigned short A5SZ1 :1; 458 unsigned short A5SZ0 :1; 459 unsigned short A4SZ1 :1; 460 unsigned short A4SZ0 :1; 461 unsigned short A3SZ1 :1; 462 unsigned short A3SZ0 :1; 463 unsigned short A2SZ1 :1; 464 unsigned short A2SZ0 :1; 465 unsigned short A1SZ1 :1; 466 unsigned short A1SZ0 :1; 467 unsigned short :1; 468 unsigned short PORTBN :1; 469 #else /* BYTE_ORDER == LITTLE_ENDIAN */ 470 /* Bit 0..15 */ 471 unsigned short PORTBN :1; 472 unsigned short :1; 473 unsigned short A1SZ0 :1; 474 unsigned short A1SZ1 :1; 475 unsigned short A2SZ0 :1; 476 unsigned short A2SZ1 :1; 477 unsigned short A3SZ0 :1; 478 unsigned short A3SZ1 :1; 479 unsigned short A4SZ0 :1; 480 unsigned short A4SZ1 :1; 481 unsigned short A5SZ0 :1; 482 unsigned short A5SZ1 :1; 483 unsigned short A6SZ0 :1; 484 unsigned short A6SZ1 :1; 485 unsigned short A0SZ0 :1; 486 unsigned short A0SZ1 :1; 487 #endif 488 } BIT; 489 } BCR2; 490 491 /* Wait state Control Register 1 0xff800008) */ 492 union { 493 unsigned int WORD; /* Word Access */ 494 struct { /* Bit Access */ 495 #if BYTE_ORDER == BIG_ENDIAN 496 /* Bit 31..0 */ 497 unsigned int :1; 498 unsigned int DMAIW2 :1; 499 unsigned int DMAIW1 :1; 500 unsigned int DMAIW0 :1; 501 unsigned int :1; 502 unsigned int A6IW2 :1; 503 unsigned int A6IW1 :1; 504 unsigned int A6IW0 :1; 505 unsigned int :1; 506 unsigned int A5IW2 :1; 507 unsigned int A5IW1 :1; 508 unsigned int A5IW0 :1; 509 unsigned int :1; 510 unsigned int A4IW2 :1; 511 unsigned int A4IW1 :1; 512 unsigned int A4IW0 :1; 513 unsigned int :1; 514 unsigned int A3IW2 :1; 515 unsigned int A3IW1 :1; 516 unsigned int A3IW0 :1; 517 unsigned int :1; 518 unsigned int A2IW2 :1; 519 unsigned int A2IW1 :1; 520 unsigned int A2IW0 :1; 521 unsigned int :1; 522 unsigned int A1IW2 :1; 523 unsigned int A1IW1 :1; 524 unsigned int A1IW0 :1; 525 unsigned int :1; 526 unsigned int A0IW2 :1; 527 unsigned int A0IW1 :1; 528 unsigned int A0IW0 :1; 529 #else /* BYTE_ORDER == LITTLE_ENDIAN */ 530 /* Bit 0..31 */ 531 unsigned int A0IW0 :1; 532 unsigned int A0IW1 :1; 533 unsigned int A0IW2 :1; 534 unsigned int :1; 535 unsigned int A1IW0 :1; 536 unsigned int A1IW1 :1; 537 unsigned int A1IW2 :1; 538 unsigned int :1; 539 unsigned int A2IW0 :1; 540 unsigned int A2IW1 :1; 541 unsigned int A2IW2 :1; 542 unsigned int :1; 543 unsigned int A3IW0 :1; 544 unsigned int A3IW1 :1; 545 unsigned int A3IW2 :1; 546 unsigned int :1; 547 unsigned int A4IW0 :1; 548 unsigned int A4IW1 :1; 549 unsigned int A4IW2 :1; 550 unsigned int :1; 551 unsigned int A5IW0 :1; 552 unsigned int A5IW1 :1; 553 unsigned int A5IW2 :1; 554 unsigned int :1; 555 unsigned int A6IW0 :1; 556 unsigned int A6IW1 :1; 557 unsigned int A6IW2 :1; 558 unsigned int :1; 559 unsigned int DMAIW0 :1; 560 unsigned int DMAIW1 :1; 561 unsigned int DMAIW2 :1; 562 unsigned int :1; 563 #endif 564 } BIT; 565 } WCR1; 566 567 /* Wait state Control Register 2 0xff80000c) */ 568 union { 569 unsigned int WORD; /* Word Access */ 570 struct { /* Bit Access */ 571 #if BYTE_ORDER == BIG_ENDIAN 572 /* Bit 31..0 */ 573 unsigned int A6W2 :1; 574 unsigned int A6W1 :1; 575 unsigned int A6W0 :1; 576 unsigned int A6B2 :1; 577 unsigned int A6B1 :1; 578 unsigned int A6B0 :1; 579 unsigned int A5W2 :1; 580 unsigned int A5W1 :1; 581 unsigned int A5W0 :1; 582 unsigned int A5B2 :1; 583 unsigned int A5B1 :1; 584 unsigned int A5B0 :1; 585 unsigned int A4W2 :1; 586 unsigned int A4W1 :1; 587 unsigned int A4W0 :1; 588 unsigned int :1; 589 unsigned int A3W2 :1; 590 unsigned int A3W1 :1; 591 unsigned int A3W0 :1; 592 unsigned int :1; 593 unsigned int A2W2 :1; 594 unsigned int A2W1 :1; 595 unsigned int A2W0 :1; 596 unsigned int A1W2 :1; 597 unsigned int A1W1 :1; 598 unsigned int A1W0 :1; 599 unsigned int A0W2 :1; 600 unsigned int A0W1 :1; 601 unsigned int A0W0 :1; 602 unsigned int A0B2 :1; 603 unsigned int A0B1 :1; 604 unsigned int A0B0 :1; 605 #else /* BYTE_ORDER == LITTLE_ENDIAN */ 606 /* Bit 0..31 */ 607 unsigned int A0B0 :1; 608 unsigned int A0B1 :1; 609 unsigned int A0B2 :1; 610 unsigned int A0W0 :1; 611 unsigned int A0W1 :1; 612 unsigned int A0W2 :1; 613 unsigned int A1W0 :1; 614 unsigned int A1W1 :1; 615 unsigned int A1W2 :1; 616 unsigned int A2W0 :1; 617 unsigned int A2W1 :1; 618 unsigned int A2W2 :1; 619 unsigned int :1; 620 unsigned int A3W0 :1; 621 unsigned int A3W1 :1; 622 unsigned int A3W2 :1; 623 unsigned int :1; 624 unsigned int A4W0 :1; 625 unsigned int A4W1 :1; 626 unsigned int A4W2 :1; 627 unsigned int A5B0 :1; 628 unsigned int A5B1 :1; 629 unsigned int A5B2 :1; 630 unsigned int A5W0 :1; 631 unsigned int A5W1 :1; 632 unsigned int A5W2 :1; 633 unsigned int A6B0 :1; 634 unsigned int A6B1 :1; 635 unsigned int A6B2 :1; 636 unsigned int A6W0 :1; 637 unsigned int A6W1 :1; 638 unsigned int A6W2 :1; 639 #endif 640 } BIT; 641 } WCR2; 642 643 644 /* Wait state Control Register 3 (0xff800010) */ 645 union { 646 unsigned int WORD; /* Word Access */ 647 struct { /* Bit Access */ 648 #if BYTE_ORDER == BIG_ENDIAN 649 /* Bit 31..0 */ 650 unsigned int :5; 651 unsigned int A6S0 :1; 652 unsigned int A6H1 :1; 653 unsigned int A6H0 :1; 654 unsigned int :1; 655 unsigned int A5S0 :1; 656 unsigned int A5H1 :1; 657 unsigned int A5H0 :1; 658 unsigned int :1; 659 unsigned int A4S0 :1; 660 unsigned int A4H1 :1; 661 unsigned int A4H0 :1; 662 unsigned int :1; 663 unsigned int A3S0 :1; 664 unsigned int A3H1 :1; 665 unsigned int A3H0 :1; 666 unsigned int :1; 667 unsigned int A2S0 :1; 668 unsigned int A2H1 :1; 669 unsigned int A2H0 :1; 670 unsigned int :1; 671 unsigned int A1S0 :1; 672 unsigned int A1H1 :1; 673 unsigned int A1H0 :1; 674 unsigned int :1; 675 unsigned int A0S0 :1; 676 unsigned int A0H1 :1; 677 unsigned int A0H0 :1; 678 #else /* BYTE_ORDER == LITTLE_ENDIAN */ 679 /* Bit 0..31 */ 680 unsigned int A0H0 :1; 681 unsigned int A0H1 :1; 682 unsigned int A0S0 :1; 683 unsigned int :1; 684 unsigned int A1H0 :1; 685 unsigned int A1H1 :1; 686 unsigned int A1S0 :1; 687 unsigned int :1; 688 unsigned int A2H0 :1; 689 unsigned int A2H1 :1; 690 unsigned int A2S0 :1; 691 unsigned int :1; 692 unsigned int A3H0 :1; 693 unsigned int A3H1 :1; 694 unsigned int A3S0 :1; 695 unsigned int :1; 696 unsigned int A4H0 :1; 697 unsigned int A4H1 :1; 698 unsigned int A4S0 :1; 699 unsigned int :1; 700 unsigned int A5H0 :1; 701 unsigned int A5H1 :1; 702 unsigned int A5S0 :1; 703 unsigned int :1; 704 unsigned int A6H0 :1; 705 unsigned int A6H1 :1; 706 unsigned int A6S0 :1; 707 unsigned int :5; 708 #endif 709 } BIT; 710 } WCR3; 711 712 /* Memory Control Register 0xff800014) */ 713 union { 714 unsigned int WORD; /* Word Access */ 715 struct { /* Bit Access */ 716 #if BYTE_ORDER == BIG_ENDIAN 717 /* Bit 31..0 */ 718 unsigned int RASD :1; 719 unsigned int MRSET :1; 720 unsigned int TRC2 :1; 721 unsigned int TRC1 :1; 722 unsigned int TRC0 :1; 723 unsigned int :3; 724 unsigned int TCAS :1; 725 unsigned int :1; 726 unsigned int TPC2 :1; 727 unsigned int TPC1 :1; 728 unsigned int TPC0 :1; 729 unsigned int :1; 730 unsigned int RCD1 :1; 731 unsigned int RCD0 :1; 732 unsigned int TRWL2 :1; 733 unsigned int TRWL1 :1; 734 unsigned int TRWL0 :1; 735 unsigned int TRAS2 :1; 736 unsigned int TRAS1 :1; 737 unsigned int TRAS0 :1; 738 unsigned int BE :1; 739 unsigned int SZ1 :1; 740 unsigned int SZ0 :1; 741 unsigned int AMXEXT :1; 742 unsigned int AMX2 :1; 743 unsigned int AMX1 :1; 744 unsigned int AMX0 :1; 745 unsigned int RFSH :1; 746 unsigned int RMODE :1; 747 unsigned int EDOMODE :1; 748 #else /* BYTE_ORDER == LITTLE_ENDIAN */ 749 /* Bit 0..31 */ 750 unsigned int EDOMODE :1; 751 unsigned int RMODE :1; 752 unsigned int RFSH :1; 753 unsigned int AMX0 :1; 754 unsigned int AMX1 :1; 755 unsigned int AMX2 :1; 756 unsigned int AMXEXT :1; 757 unsigned int SZ0 :1; 758 unsigned int SZ1 :1; 759 unsigned int BE :1; 760 unsigned int TRAS0 :1; 761 unsigned int TRAS1 :1; 762 unsigned int TRAS2 :1; 763 unsigned int TRWL0 :1; 764 unsigned int TRWL1 :1; 765 unsigned int TRWL2 :1; 766 unsigned int RCD0 :1; 767 unsigned int RCD1 :1; 768 unsigned int :1; 769 unsigned int TPC0 :1; 770 unsigned int TPC1 :1; 771 unsigned int TPC2 :1; 772 unsigned int :1; 773 unsigned int TCAS :1; 774 unsigned int :3; 775 unsigned int TRC0 :1; 776 unsigned int TRC1 :1; 777 unsigned int TRC2 :1; 778 unsigned int MRSET :1; 779 unsigned int RASD :1; 780 #endif 781 } BIT; 782 } MCR; 783 784 /* PCMCIA Control Register 0xff800018) */ 785 union { 786 unsigned short WORD; /* Word Access */ 787 struct { /* Bit Access */ 788 #if BYTE_ORDER == BIG_ENDIAN 789 /* Bit 15..0 */ 790 unsigned short A5PCW1 :1; 791 unsigned short A5PCW0 :1; 792 unsigned short A6PCW1 :1; 793 unsigned short A6PCW0 :1; 794 unsigned short A5TED2 :1; 795 unsigned short A5TED1 :1; 796 unsigned short A5TED0 :1; 797 unsigned short A6TED2 :1; 798 unsigned short A6TED1 :1; 799 unsigned short A6TED0 :1; 800 unsigned short A5TEH2 :1; 801 unsigned short A5TEH1 :1; 802 unsigned short A5TEH0 :1; 803 unsigned short A6TEH2 :1; 804 unsigned short A6TEH1 :1; 805 unsigned short A6TEH0 :1; 806 #else /* BYTE_ORDER == LITTLE_ENDIAN */ 807 /* Bit 0..15 */ 808 unsigned short A6TEH0 :1; 809 unsigned short A6TEH1 :1; 810 unsigned short A6TEH2 :1; 811 unsigned short A5TEH0 :1; 812 unsigned short A5TEH1 :1; 813 unsigned short A5TEH2 :1; 814 unsigned short A6TED0 :1; 815 unsigned short A6TED1 :1; 816 unsigned short A6TED2 :1; 817 unsigned short A5TED0 :1; 818 unsigned short A5TED1 :1; 819 unsigned short A5TED2 :1; 820 unsigned short A6PCW0 :1; 821 unsigned short A6PCW1 :1; 822 unsigned short A5PCW0 :1; 823 unsigned short A5PCW1 :1; 824 #endif 825 } BIT; 826 } PCR; 827 828 /* Refresh Timer Control/Status Register 0xff80001c) */ 829 union { 830 unsigned short WORD; /* Word Access */ 831 struct { /* Bit Access */ 832 #if BYTE_ORDER == BIG_ENDIAN 833 /* Bit 15..0 */ 834 unsigned short :8; 835 unsigned short CMF :1; 836 unsigned short CMIE :1; 837 unsigned short CKS2 :1; 838 unsigned short CKS1 :1; 839 unsigned short CKS0 :1; 840 unsigned short OVF :1; 841 unsigned short OVIE :1; 842 unsigned short LMTS :1; 843 #else /* BYTE_ORDER == LITTLE_ENDIAN */ 844 /* Bit 0..15 */ 845 unsigned short LMTS :1; 846 unsigned short OVIE :1; 847 unsigned short OVF :1; 848 unsigned short CKS0 :1; 849 unsigned short CKS1 :1; 850 unsigned short CKS2 :1; 851 unsigned short CMIE :1; 852 unsigned short CMF :1; 853 unsigned short :8; 854 #endif 855 } BIT; 856 } RTCSR; 857 858 /* Refresh Timer CouNTer 0xff800020) */ 859 unsigned short RTCNT; 860 861 /* Refresh Time Constant cOunteR 0xff800024) */ 862 unsigned short RTCOR; 863 864 /* Refresh Count Register 0xff800028) */ 865 unsigned short RFCR; 866 }; 867 868 /* BSC Address */ 869 #define SHREG_BSC (*(volatile struct sh3_bsc *) 0xff800000) 870 871 #endif 872 #endif /* !_SH3_BSCREG_H_ */ 873
Indexes created Mon Sep 29 21:09:56 GMT 2025