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      1  1.9    martin /*	$NetBSD: cache.h,v 1.9 2008/04/28 20:23:35 martin Exp $	*/
      2  1.1       uch 
      3  1.1       uch /*-
      4  1.1       uch  * Copyright (c) 2002 The NetBSD Foundation, Inc.
      5  1.1       uch  * All rights reserved.
      6  1.1       uch  *
      7  1.1       uch  * This code is derived from software contributed to The NetBSD Foundation
      8  1.1       uch  * by UCHIYAMA Yasushi.
      9  1.1       uch  *
     10  1.1       uch  * Redistribution and use in source and binary forms, with or without
     11  1.1       uch  * modification, are permitted provided that the following conditions
     12  1.1       uch  * are met:
     13  1.1       uch  * 1. Redistributions of source code must retain the above copyright
     14  1.1       uch  *    notice, this list of conditions and the following disclaimer.
     15  1.1       uch  * 2. Redistributions in binary form must reproduce the above copyright
     16  1.1       uch  *    notice, this list of conditions and the following disclaimer in the
     17  1.1       uch  *    documentation and/or other materials provided with the distribution.
     18  1.1       uch  *
     19  1.1       uch  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  1.1       uch  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  1.1       uch  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  1.1       uch  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  1.1       uch  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  1.1       uch  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  1.1       uch  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  1.1       uch  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  1.1       uch  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  1.1       uch  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  1.1       uch  * POSSIBILITY OF SUCH DAMAGE.
     30  1.1       uch  */
     31  1.1       uch 
     32  1.1       uch /*
     33  1.1       uch  * Cache configurations.
     34  1.1       uch  *
     35  1.1       uch  * SH3 I/D unified virtual-index physical-tag cache.
     36  1.1       uch  * SH4 I/D separated virtual-index physical-tag cache.
     37  1.1       uch  *
     38  1.1       uch  *
     39  1.5  christos  *         size       line-size entry way type
     40  1.5  christos  * SH7708  4/8K       16B       128   2/4 P0,P2,U0 [1]
     41  1.5  christos  *                                        P1 [2]
     42  1.5  christos  * SH7709  4/8K       16B       128   2/4 [1]
     43  1.5  christos  * SH7709A 16K        16B       256   4   [1]
     44  1.5  christos  *
     45  1.5  christos  * SH7750  I$  D$     line-size entry way
     46  1.5  christos  *         8K  8/16K  32B       256   1   [1]
     47  1.5  christos  * SH7750
     48  1.5  christos  * SH7750S
     49  1.5  christos  * SH7751  I$  D$     line-size entry way
     50  1.5  christos  *         8K  8/16K  32B       256   1   [1]
     51  1.5  christos  *
     52  1.5  christos  * SH7750R
     53  1.5  christos  * SH7751R I$  D$     line-size entry way
     54  1.5  christos  *         16K 16/32K 32B       512   2   [1]
     55  1.1       uch  *
     56  1.5  christos  * [1]	write-through/back selectable
     57  1.5  christos  * [2]	write-through only
     58  1.3       uch  *
     59  1.1       uch  * Cache operations.
     60  1.3       uch  *
     61  1.1       uch  * There are some rules that must be followed:
     62  1.1       uch  *
     63  1.1       uch  *	I-cache Synch (all or range):
     64  1.1       uch  *		The goal is to synchronize the instruction stream,
     65  1.1       uch  *		so you may need to write-back dirty data cache
     66  1.1       uch  *		blocks first.  If a range is requested, and you
     67  1.1       uch  *		can't synchronize just a range, you have to hit
     68  1.1       uch  *		the whole thing.
     69  1.1       uch  *
     70  1.1       uch  *	D-cache Write-back Invalidate range:
     71  1.1       uch  *		If you can't WB-Inv a range, you must WB-Inv the
     72  1.1       uch  *		entire D-cache.
     73  1.1       uch  *
     74  1.1       uch  *	D-cache Invalidate:
     75  1.1       uch  *		If you can't Inv the D-cache without doing a
     76  1.1       uch  *		Write-back, YOU MUST PANIC.  This is to catch
     77  1.1       uch  *		errors in calling code.  Callers must be aware
     78  1.1       uch  *		of this scenario, and must handle it appropriately
     79  1.1       uch  *		(consider the bus_dma(9) operations).
     80  1.1       uch  *
     81  1.1       uch  *	D-cache Write-back:
     82  1.1       uch  *		If you can't Write-back without doing an invalidate,
     83  1.1       uch  *		that's fine.  Then treat this as a WB-Inv.  Skipping
     84  1.1       uch  *		the invalidate is merely an optimization.
     85  1.1       uch  *
     86  1.1       uch  *	All operations:
     87  1.1       uch  *		Valid virtual addresses must be passed to the
     88  1.1       uch  *		cache operation.
     89  1.1       uch  *
     90  1.1       uch  *
     91  1.1       uch  *	sh_icache_sync_all	Synchronize I-cache
     92  1.1       uch  *
     93  1.1       uch  *	sh_icache_sync_range	Synchronize I-cache range
     94  1.1       uch  *
     95  1.1       uch  *	sh_icache_sync_range_index (index ops)
     96  1.1       uch  *
     97  1.1       uch  *	sh_dcache_wbinv_all	Write-back Invalidate D-cache
     98  1.1       uch  *
     99  1.1       uch  *	sh_dcache_wbinv_range	Write-back Invalidate D-cache range
    100  1.1       uch  *
    101  1.1       uch  *	sh_dcache_wbinv_range_index (index ops)
    102  1.1       uch  *
    103  1.1       uch  *	sh_dcache_inv_range	Invalidate D-cache range
    104  1.1       uch  *
    105  1.1       uch  *	sh_dcache_wb_range	Write-back D-cache range
    106  1.3       uch  *
    107  1.3       uch  *	If I/D unified cache (SH3), I-cache ops are writeback invalidate
    108  1.1       uch  *	operation.
    109  1.1       uch  *	If write-through mode, sh_dcache_wb_range is no-operation.
    110  1.1       uch  *
    111  1.1       uch  */
    112  1.1       uch 
    113  1.1       uch #ifndef _SH3_CACHE_H_
    114  1.3       uch #define	_SH3_CACHE_H_
    115  1.1       uch 
    116  1.1       uch #ifdef _KERNEL
    117  1.1       uch struct sh_cache_ops {
    118  1.1       uch 	void (*_icache_sync_all)(void);
    119  1.1       uch 	void (*_icache_sync_range)(vaddr_t, vsize_t);
    120  1.1       uch 	void (*_icache_sync_range_index)(vaddr_t, vsize_t);
    121  1.3       uch 
    122  1.1       uch 	void (*_dcache_wbinv_all)(void);
    123  1.1       uch 	void (*_dcache_wbinv_range)(vaddr_t, vsize_t);
    124  1.1       uch 	void (*_dcache_wbinv_range_index)(vaddr_t, vsize_t);
    125  1.1       uch 	void (*_dcache_inv_range)(vaddr_t, vsize_t);
    126  1.1       uch 	void (*_dcache_wb_range)(vaddr_t, vsize_t);
    127  1.1       uch };
    128  1.1       uch 
    129  1.1       uch /* Cache configurations */
    130  1.3       uch #define	sh_cache_enable_unified		sh_cache_enable_icache
    131  1.1       uch extern int sh_cache_enable_icache;
    132  1.1       uch extern int sh_cache_enable_dcache;
    133  1.1       uch extern int sh_cache_write_through;
    134  1.1       uch extern int sh_cache_write_through_p0_u0_p3;
    135  1.1       uch extern int sh_cache_write_through_p1;
    136  1.1       uch extern int sh_cache_ways;
    137  1.1       uch extern int sh_cache_unified;
    138  1.3       uch #define	sh_cache_size_unified		sh_cache_size_icache
    139  1.1       uch extern int sh_cache_size_icache;
    140  1.1       uch extern int sh_cache_size_dcache;
    141  1.1       uch extern int sh_cache_line_size;
    142  1.2       uch /* for n-way set associative cache */
    143  1.2       uch extern int sh_cache_way_size;
    144  1.2       uch extern int sh_cache_way_shift;
    145  1.2       uch extern int sh_cache_entry_mask;
    146  1.2       uch 
    147  1.1       uch /* Special mode */
    148  1.1       uch extern int sh_cache_ram_mode;
    149  1.1       uch extern int sh_cache_index_mode_icache;
    150  1.1       uch extern int sh_cache_index_mode_dcache;
    151  1.1       uch 
    152  1.8   tsutsui extern int sh_cache_alias_mask;
    153  1.8   tsutsui #define	sh_cache_indexof(x)	(sh_cache_alias_mask & (x))
    154  1.8   tsutsui extern int sh_cache_prefer_mask;
    155  1.8   tsutsui 
    156  1.1       uch extern struct sh_cache_ops sh_cache_ops;
    157  1.1       uch 
    158  1.1       uch #define	sh_icache_sync_all()						\
    159  1.1       uch 	(*sh_cache_ops._icache_sync_all)()
    160  1.1       uch 
    161  1.1       uch #define	sh_icache_sync_range(v, s)					\
    162  1.1       uch 	(*sh_cache_ops._icache_sync_range)((v), (s))
    163  1.1       uch 
    164  1.1       uch #define	sh_icache_sync_range_index(v, s)				\
    165  1.1       uch 	(*sh_cache_ops._icache_sync_range_index)((v), (s))
    166  1.1       uch 
    167  1.1       uch #define	sh_dcache_wbinv_all()						\
    168  1.1       uch 	(*sh_cache_ops._dcache_wbinv_all)()
    169  1.1       uch 
    170  1.1       uch #define	sh_dcache_wbinv_range(v, s)					\
    171  1.1       uch 	(*sh_cache_ops._dcache_wbinv_range)((v), (s))
    172  1.1       uch 
    173  1.1       uch #define	sh_dcache_wbinv_range_index(v, s)				\
    174  1.1       uch 	(*sh_cache_ops._dcache_wbinv_range_index)((v), (s))
    175  1.1       uch 
    176  1.1       uch #define	sh_dcache_inv_range(v, s)					\
    177  1.1       uch 	(*sh_cache_ops._dcache_inv_range)((v), (s))
    178  1.1       uch 
    179  1.1       uch #define	sh_dcache_wb_range(v, s)					\
    180  1.1       uch 	(*sh_cache_ops._dcache_wb_range)((v), (s))
    181  1.1       uch 
    182  1.2       uch void sh_cache_init(void);
    183  1.1       uch void sh_cache_information(void);
    184  1.4       uch 
    185  1.7       uwe #define	SH_HAS_UNIFIED_CACHE	CPU_IS_SH3
    186  1.4       uch #define	SH_HAS_VIRTUAL_ALIAS	CPU_IS_SH4
    187  1.4       uch #define	SH_HAS_WRITEBACK_CACHE	(!sh_cache_write_through)
    188  1.1       uch 
    189  1.1       uch #endif /* _KERNEL */
    190  1.1       uch #endif /* _SH3_CACHE_H_ */
    191