cache.h revision 1.5
1 /* $NetBSD: cache.h,v 1.5 2005/06/29 16:31:51 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Cache configurations. 41 * 42 * SH3 I/D unified virtual-index physical-tag cache. 43 * SH4 I/D separated virtual-index physical-tag cache. 44 * 45 * 46 * size line-size entry way type 47 * SH7708 4/8K 16B 128 2/4 P0,P2,U0 [1] 48 * P1 [2] 49 * SH7709 4/8K 16B 128 2/4 [1] 50 * SH7709A 16K 16B 256 4 [1] 51 * 52 * SH7750 I$ D$ line-size entry way 53 * 8K 8/16K 32B 256 1 [1] 54 * SH7750 55 * SH7750S 56 * SH7751 I$ D$ line-size entry way 57 * 8K 8/16K 32B 256 1 [1] 58 * 59 * SH7750R 60 * SH7751R I$ D$ line-size entry way 61 * 16K 16/32K 32B 512 2 [1] 62 * 63 * [1] write-through/back selectable 64 * [2] write-through only 65 * 66 * Cache operations. 67 * 68 * There are some rules that must be followed: 69 * 70 * I-cache Synch (all or range): 71 * The goal is to synchronize the instruction stream, 72 * so you may need to write-back dirty data cache 73 * blocks first. If a range is requested, and you 74 * can't synchronize just a range, you have to hit 75 * the whole thing. 76 * 77 * D-cache Write-back Invalidate range: 78 * If you can't WB-Inv a range, you must WB-Inv the 79 * entire D-cache. 80 * 81 * D-cache Invalidate: 82 * If you can't Inv the D-cache without doing a 83 * Write-back, YOU MUST PANIC. This is to catch 84 * errors in calling code. Callers must be aware 85 * of this scenario, and must handle it appropriately 86 * (consider the bus_dma(9) operations). 87 * 88 * D-cache Write-back: 89 * If you can't Write-back without doing an invalidate, 90 * that's fine. Then treat this as a WB-Inv. Skipping 91 * the invalidate is merely an optimization. 92 * 93 * All operations: 94 * Valid virtual addresses must be passed to the 95 * cache operation. 96 * 97 * 98 * sh_icache_sync_all Synchronize I-cache 99 * 100 * sh_icache_sync_range Synchronize I-cache range 101 * 102 * sh_icache_sync_range_index (index ops) 103 * 104 * sh_dcache_wbinv_all Write-back Invalidate D-cache 105 * 106 * sh_dcache_wbinv_range Write-back Invalidate D-cache range 107 * 108 * sh_dcache_wbinv_range_index (index ops) 109 * 110 * sh_dcache_inv_range Invalidate D-cache range 111 * 112 * sh_dcache_wb_range Write-back D-cache range 113 * 114 * If I/D unified cache (SH3), I-cache ops are writeback invalidate 115 * operation. 116 * If write-through mode, sh_dcache_wb_range is no-operation. 117 * 118 */ 119 120 #ifndef _SH3_CACHE_H_ 121 #define _SH3_CACHE_H_ 122 123 #ifdef _KERNEL 124 struct sh_cache_ops { 125 void (*_icache_sync_all)(void); 126 void (*_icache_sync_range)(vaddr_t, vsize_t); 127 void (*_icache_sync_range_index)(vaddr_t, vsize_t); 128 129 void (*_dcache_wbinv_all)(void); 130 void (*_dcache_wbinv_range)(vaddr_t, vsize_t); 131 void (*_dcache_wbinv_range_index)(vaddr_t, vsize_t); 132 void (*_dcache_inv_range)(vaddr_t, vsize_t); 133 void (*_dcache_wb_range)(vaddr_t, vsize_t); 134 }; 135 136 /* Cache configurations */ 137 #define sh_cache_enable_unified sh_cache_enable_icache 138 extern int sh_cache_enable_icache; 139 extern int sh_cache_enable_dcache; 140 extern int sh_cache_write_through; 141 extern int sh_cache_write_through_p0_u0_p3; 142 extern int sh_cache_write_through_p1; 143 extern int sh_cache_ways; 144 extern int sh_cache_unified; 145 #define sh_cache_size_unified sh_cache_size_icache 146 extern int sh_cache_size_icache; 147 extern int sh_cache_size_dcache; 148 extern int sh_cache_line_size; 149 /* for n-way set associative cache */ 150 extern int sh_cache_way_size; 151 extern int sh_cache_way_shift; 152 extern int sh_cache_entry_mask; 153 154 /* Special mode */ 155 extern int sh_cache_ram_mode; 156 extern int sh_cache_index_mode_icache; 157 extern int sh_cache_index_mode_dcache; 158 159 extern struct sh_cache_ops sh_cache_ops; 160 161 #define sh_icache_sync_all() \ 162 (*sh_cache_ops._icache_sync_all)() 163 164 #define sh_icache_sync_range(v, s) \ 165 (*sh_cache_ops._icache_sync_range)((v), (s)) 166 167 #define sh_icache_sync_range_index(v, s) \ 168 (*sh_cache_ops._icache_sync_range_index)((v), (s)) 169 170 #define sh_dcache_wbinv_all() \ 171 (*sh_cache_ops._dcache_wbinv_all)() 172 173 #define sh_dcache_wbinv_range(v, s) \ 174 (*sh_cache_ops._dcache_wbinv_range)((v), (s)) 175 176 #define sh_dcache_wbinv_range_index(v, s) \ 177 (*sh_cache_ops._dcache_wbinv_range_index)((v), (s)) 178 179 #define sh_dcache_inv_range(v, s) \ 180 (*sh_cache_ops._dcache_inv_range)((v), (s)) 181 182 #define sh_dcache_wb_range(v, s) \ 183 (*sh_cache_ops._dcache_wb_range)((v), (s)) 184 185 void sh_cache_init(void); 186 void sh_cache_information(void); 187 188 #if defined(SH3) && defined(SH4) 189 #define SH_HAS_VIRTUAL_ALIAS CPU_IS_SH4 190 #define SH_HAS_UNIFIED_CACHE CPU_IS_SH3 191 #define SH_HAS_WRITEBACK_CACHE (!sh_cache_write_through) 192 #elif defined(SH3) 193 #define SH_HAS_VIRTUAL_ALIAS 0 194 #define SH_HAS_UNIFIED_CACHE 1 195 #define SH_HAS_WRITEBACK_CACHE (!sh_cache_write_through) 196 #elif defined(SH4) 197 #define SH_HAS_VIRTUAL_ALIAS 1 198 #define SH_HAS_UNIFIED_CACHE 0 199 #define SH_HAS_WRITEBACK_CACHE (!sh_cache_write_through) 200 #endif 201 202 #endif /* _KERNEL */ 203 #endif /* _SH3_CACHE_H_ */ 204
Indexes created Fri Sep 26 08:10:20 GMT 2025