cache_sh3.h revision 1.2
1 /* $NetBSD: cache_sh3.h,v 1.2 2002/02/17 20:58:03 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * SH3: SH7708, SH7708S, SH7708R, SH7709, SH7709A 41 */ 42 #ifndef _CACHE_SH3_H_ 43 #define _CACHE_SH3_H_ 44 #ifdef _KERNEL 45 46 #define SH3_CCR 0xffffffec 47 #define SH3_CCR_CE 0x00000001 48 #define SH3_CCR_WT 0x00000002 49 /* SH7708 don't have CB bit */ 50 #define SH3_CCR_CB 0x00000004 51 #define SH3_CCR_CF 0x00000008 52 /* SH7709A don't have RA bit */ 53 #define SH3_CCR_RA 0x00000020 54 55 /* SH7709A specific cache-lock control register */ 56 #define SH7709A_CCR2 0xa40000b0 57 #define SH7709A_CCR2_W2LOCK 0x00000001 58 #define SH7709A_CCR2_W2LOAD 0x00000002 59 #define SH7709A_CCR2_W3LOCK 0x00000100 60 #define SH7709A_CCR2_W3LOAD 0x00000200 61 62 #define SH3_CCA 0xf0000000 63 /* Address specification */ 64 #define CCA_A 0x00000008 65 #define CCA_ENTRY_SHIFT 4 66 /* 8KB cache (SH7708, SH7708S, SH7708R, SH7709) */ 67 #define CCA_8K_ENTRY 128 68 #define CCA_8K_ENTRY_MASK 0x000007f0 /* [10:4] */ 69 #define CCA_8K_WAY_SHIFT 11 70 #define CCA_8K_WAY_MASK 0x00001800 /* [12:11] */ 71 /* 16KB cache (SH7709A) */ 72 #define CCA_16K_ENTRY 256 73 #define CCA_16K_ENTRY_MASK 0x00000ff0 /* [11:4] */ 74 #define CCA_16K_WAY_SHIFT 12 75 #define CCA_16K_WAY_MASK 0x00003000 /* [13:12] */ 76 77 /* Data specification */ 78 #define CCA_V 0x00000001 79 #define CCA_U 0x00000002 80 #define CCA_LRU_SHIFT 4 81 #define CCA_LRU_MASK 0x000003f0 /* [9:4] */ 82 #define CCA_TAGADDR_SHIFT 10 83 #define CCA_TAGADDR_MASK 0xfffffc00 /* [31:10] */ 84 85 #define SH3_CCD 0xf1000000 86 /* Address specification */ 87 #define CCD_L_SHIFT 2 88 #define CCD_L_MASK 0x0000000c /* [3:2] */ 89 #define CCD_E_SHIFT 4 90 #define CCD_8K_E_MASK 0x000007f0 /* [10:4] */ 91 #define CCD_16K_E_MASK 0x00000ff0 /* [11:4] */ 92 #define CCD_8K_W_SHIFT 11 93 #define CCD_8K_W_MASK 0x00001800 /* [12:11] */ 94 #define CCD_16K_W_SHIFT 12 95 #define CCD_16K_W_MASK 0x00003000 /* [13:12] */ 96 /* Data specification */ 97 98 /* 99 * Configuration 100 */ 101 #define SH3_CACHE_LINESZ 16 102 #define SH3_CACHE_NORMAL_WAY 4 103 #define SH3_CACHE_RAMMODE_WAY 2 104 105 #define SH3_CACHE_8K_ENTRY 128 106 #define SH3_CACHE_8K_WAY_NORMAL 4 107 #define SH3_CACHE_8K_WAY_RAMMODE 2 108 109 #define SH3_CACHE_16K_ENTRY 256 110 #define SH3_CACHE_16K_WAY 4 111 112 /* 113 * cache flush macro for locore level code. 114 */ 115 #define SH3_CACHE_8K_FLUSH(maxway) \ 116 do { \ 117 u_int32_t __e, __w, __wa, __a; \ 118 \ 119 for (__w = 0; __w < maxway; __w++) { \ 120 __wa = SH3_CCA | __w << CCA_8K_WAY_SHIFT; \ 121 for (__e = 0; __e < CCA_8K_ENTRY; __e++) { \ 122 __a = __wa |(__e << CCA_ENTRY_SHIFT); \ 123 (*(__volatile__ u_int32_t *)__a) &= \ 124 ~(CCA_U | CCA_V); \ 125 } \ 126 } \ 127 } while (/*CONSTCOND*/0) 128 129 #define SH3_CACHE_16K_FLUSH() \ 130 do { \ 131 u_int32_t __e, __w, __wa, __a; \ 132 \ 133 for (__w = 0; __w < SH3_CACHE_16K_WAY; __w++) { \ 134 __wa = SH3_CCA | __w << CCA_16K_WAY_SHIFT; \ 135 for (__e = 0; __e < CCA_16K_ENTRY; __e++) { \ 136 __a = __wa |(__e << CCA_ENTRY_SHIFT); \ 137 (*(__volatile__ u_int32_t *)__a) &= \ 138 ~(CCA_U | CCA_V); \ 139 } \ 140 } \ 141 } while (/*CONSTCOND*/0) 142 143 #define SH7708_CACHE_FLUSH() SH3_CACHE_8K_FLUSH(4) 144 #define SH7708_CACHE_FLUSH_RAMMODE() SH3_CACHE_8K_FLUSH(2) 145 #define SH7708S_CACHE_FLUSH() SH3_CACHE_8K_FLUSH(4) 146 #define SH7708S_CACHE_FLUSH_RAMMODE() SH3_CACHE_8K_FLUSH(2) 147 #define SH7708R_CACHE_FLUSH() SH3_CACHE_8K_FLUSH(4) 148 #define SH7708R_CACHE_FLUSH_RAMMODE() SH3_CACHE_8K_FLUSH(2) 149 #define SH7709_CACHE_FLUSH() SH3_CACHE_8K_FLUSH(4) 150 #define SH7709_CACHE_FLUSH_RAMMODE() SH3_CACHE_8K_FLUSH(2) 151 #define SH7709A_CACHE_FLUSH() SH3_CACHE_16K_FLUSH() 152 153 #ifndef _LOCORE 154 extern void sh3_cache_config(void); 155 #endif 156 #endif _KERNEL 157 #endif /* _CACHE_SH3_H_ */ 158
Indexes created Thu Sep 25 16:09:42 GMT 2025