cpu.h revision 1.32 1 1.32 agc /* $NetBSD: cpu.h,v 1.32 2003/08/07 16:29:28 agc Exp $ */
2 1.1 itojun
3 1.1 itojun /*-
4 1.1 itojun * Copyright (c) 1990 The Regents of the University of California.
5 1.1 itojun * All rights reserved.
6 1.32 agc *
7 1.32 agc * This code is derived from software contributed to Berkeley by
8 1.32 agc * William Jolitz.
9 1.32 agc *
10 1.32 agc * Redistribution and use in source and binary forms, with or without
11 1.32 agc * modification, are permitted provided that the following conditions
12 1.32 agc * are met:
13 1.32 agc * 1. Redistributions of source code must retain the above copyright
14 1.32 agc * notice, this list of conditions and the following disclaimer.
15 1.32 agc * 2. Redistributions in binary form must reproduce the above copyright
16 1.32 agc * notice, this list of conditions and the following disclaimer in the
17 1.32 agc * documentation and/or other materials provided with the distribution.
18 1.32 agc * 3. Neither the name of the University nor the names of its contributors
19 1.32 agc * may be used to endorse or promote products derived from this software
20 1.32 agc * without specific prior written permission.
21 1.32 agc *
22 1.32 agc * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 1.32 agc * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 1.32 agc * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 1.32 agc * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 1.32 agc * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 1.32 agc * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 1.32 agc * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 1.32 agc * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 1.32 agc * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 1.32 agc * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 1.32 agc * SUCH DAMAGE.
33 1.32 agc *
34 1.32 agc * @(#)cpu.h 5.4 (Berkeley) 5/9/91
35 1.32 agc */
36 1.32 agc
37 1.32 agc /*-
38 1.32 agc * Copyright (c) 2002 The NetBSD Foundation, Inc. All rights reserved.
39 1.1 itojun *
40 1.1 itojun * This code is derived from software contributed to Berkeley by
41 1.1 itojun * William Jolitz.
42 1.1 itojun *
43 1.1 itojun * Redistribution and use in source and binary forms, with or without
44 1.1 itojun * modification, are permitted provided that the following conditions
45 1.1 itojun * are met:
46 1.1 itojun * 1. Redistributions of source code must retain the above copyright
47 1.1 itojun * notice, this list of conditions and the following disclaimer.
48 1.1 itojun * 2. Redistributions in binary form must reproduce the above copyright
49 1.1 itojun * notice, this list of conditions and the following disclaimer in the
50 1.1 itojun * documentation and/or other materials provided with the distribution.
51 1.1 itojun * 3. All advertising materials mentioning features or use of this software
52 1.1 itojun * must display the following acknowledgement:
53 1.1 itojun * This product includes software developed by the University of
54 1.1 itojun * California, Berkeley and its contributors.
55 1.1 itojun * 4. Neither the name of the University nor the names of its contributors
56 1.1 itojun * may be used to endorse or promote products derived from this software
57 1.1 itojun * without specific prior written permission.
58 1.1 itojun *
59 1.1 itojun * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
60 1.1 itojun * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
61 1.1 itojun * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
62 1.1 itojun * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
63 1.1 itojun * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
64 1.1 itojun * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
65 1.1 itojun * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
66 1.1 itojun * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
67 1.1 itojun * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
68 1.1 itojun * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
69 1.1 itojun * SUCH DAMAGE.
70 1.1 itojun *
71 1.1 itojun * @(#)cpu.h 5.4 (Berkeley) 5/9/91
72 1.1 itojun */
73 1.1 itojun
74 1.1 itojun /*
75 1.25 uch * SH3/SH4 support.
76 1.1 itojun *
77 1.1 itojun * T.Horiuchi Brains Corp. 5/22/98
78 1.1 itojun */
79 1.1 itojun
80 1.1 itojun #ifndef _SH3_CPU_H_
81 1.28 uch #define _SH3_CPU_H_
82 1.1 itojun
83 1.12 mrg #if defined(_KERNEL_OPT)
84 1.8 thorpej #include "opt_lockdebug.h"
85 1.8 thorpej #endif
86 1.8 thorpej
87 1.25 uch #include <sys/sched.h>
88 1.25 uch #include <sh3/psl.h>
89 1.25 uch #include <sh3/frame.h>
90 1.8 thorpej
91 1.26 uch #ifdef _KERNEL
92 1.8 thorpej struct cpu_info {
93 1.8 thorpej struct schedstate_percpu ci_schedstate; /* scheduler state */
94 1.8 thorpej #if defined(DIAGNOSTIC) || defined(LOCKDEBUG)
95 1.8 thorpej u_long ci_spin_locks; /* # of spin locks held */
96 1.8 thorpej u_long ci_simple_locks; /* # of simple locks held */
97 1.8 thorpej #endif
98 1.8 thorpej };
99 1.8 thorpej
100 1.8 thorpej extern struct cpu_info cpu_info_store;
101 1.8 thorpej #define curcpu() (&cpu_info_store)
102 1.1 itojun
103 1.1 itojun /*
104 1.1 itojun * definitions of cpu-dependent requirements
105 1.1 itojun * referenced in generic code
106 1.1 itojun */
107 1.1 itojun #define cpu_wait(p) /* nothing */
108 1.2 tsubai #define cpu_number() 0
109 1.28 uch /*
110 1.28 uch * Can't swapout u-area, (__SWAP_BROKEN)
111 1.24 uch * since we use P1 converted address for trapframe.
112 1.24 uch */
113 1.28 uch #define cpu_swapin(p) /* nothing */
114 1.24 uch #define cpu_swapout(p) panic("cpu_swapout: can't get here");
115 1.31 thorpej #define cpu_proc_fork(p1, p2) /* nothing */
116 1.1 itojun
117 1.1 itojun /*
118 1.26 uch * Arguments to hardclock and gatherstats encapsulate the previous
119 1.26 uch * machine state in an opaque clockframe.
120 1.1 itojun */
121 1.26 uch struct clockframe {
122 1.26 uch int spc; /* program counter at time of interrupt */
123 1.26 uch int ssr; /* status register at time of interrupt */
124 1.26 uch int ssp; /* stack pointer at time of interrupt */
125 1.26 uch };
126 1.1 itojun
127 1.26 uch #define CLKF_USERMODE(cf) (!KERNELMODE((cf)->ssr))
128 1.26 uch #define CLKF_BASEPRI(cf) (((cf)->ssr & 0xf0) == 0)
129 1.26 uch #define CLKF_PC(cf) ((cf)->spc)
130 1.29 thorpej #define CLKF_INTR(cf) 0 /* XXX */
131 1.1 itojun
132 1.1 itojun /*
133 1.24 uch * This is used during profiling to integrate system time. It can safely
134 1.24 uch * assume that the process is resident.
135 1.24 uch */
136 1.24 uch #define PROC_PC(p) \
137 1.24 uch (((struct trapframe *)(p)->p_md.md_regs)->tf_spc)
138 1.24 uch
139 1.24 uch /*
140 1.1 itojun * Preempt the current process if in interrupt from user mode,
141 1.1 itojun * or after the current trap/syscall if in system mode.
142 1.1 itojun */
143 1.24 uch #define need_resched(ci) \
144 1.24 uch do { \
145 1.24 uch want_resched = 1; \
146 1.24 uch if (curproc != NULL) \
147 1.31 thorpej aston(curproc); \
148 1.24 uch } while (/*CONSTCOND*/0)
149 1.1 itojun
150 1.1 itojun /*
151 1.1 itojun * Give a profiling tick to the current process when the user profiling
152 1.24 uch * buffer pages are invalid. On the MIPS, request an ast to send us
153 1.24 uch * through trap, marking the proc as needing a profiling tick.
154 1.1 itojun */
155 1.24 uch #define need_proftick(p) \
156 1.24 uch do { \
157 1.24 uch (p)->p_flag |= P_OWEUPC; \
158 1.24 uch aston(p); \
159 1.24 uch } while (/*CONSTCOND*/0)
160 1.1 itojun
161 1.1 itojun /*
162 1.1 itojun * Notify the current process (p) that it has a signal pending,
163 1.1 itojun * process as soon as possible.
164 1.1 itojun */
165 1.24 uch #define signotify(p) aston(p)
166 1.24 uch
167 1.28 uch #define aston(p) ((p)->p_md.md_astpending = 1)
168 1.24 uch
169 1.24 uch extern int want_resched; /* need_resched() was called */
170 1.1 itojun
171 1.1 itojun /*
172 1.1 itojun * We need a machine-independent name for this.
173 1.1 itojun */
174 1.1 itojun #define DELAY(x) delay(x)
175 1.26 uch #endif /* _KERNEL */
176 1.1 itojun
177 1.1 itojun /*
178 1.25 uch * Logical address space of SH3/SH4 CPU.
179 1.1 itojun */
180 1.28 uch #define SH3_PHYS_MASK 0x1fffffff
181 1.25 uch
182 1.28 uch #define SH3_P0SEG_BASE 0x00000000 /* TLB mapped, also U0SEG */
183 1.28 uch #define SH3_P0SEG_END 0x7fffffff
184 1.28 uch #define SH3_P1SEG_BASE 0x80000000 /* pa == va */
185 1.28 uch #define SH3_P1SEG_END 0x9fffffff
186 1.28 uch #define SH3_P2SEG_BASE 0xa0000000 /* pa == va, non-cacheable */
187 1.28 uch #define SH3_P2SEG_END 0xbfffffff
188 1.28 uch #define SH3_P3SEG_BASE 0xc0000000 /* TLB mapped, kernel mode */
189 1.28 uch #define SH3_P3SEG_END 0xdfffffff
190 1.28 uch #define SH3_P4SEG_BASE 0xe0000000 /* peripheral space */
191 1.28 uch #define SH3_P4SEG_END 0xffffffff
192 1.28 uch
193 1.28 uch #define SH3_P1SEG_TO_PHYS(x) ((u_int32_t)(x) & SH3_PHYS_MASK)
194 1.28 uch #define SH3_P2SEG_TO_PHYS(x) ((u_int32_t)(x) & SH3_PHYS_MASK)
195 1.28 uch #define SH3_PHYS_TO_P1SEG(x) ((u_int32_t)(x) | SH3_P1SEG_BASE)
196 1.28 uch #define SH3_PHYS_TO_P2SEG(x) ((u_int32_t)(x) | SH3_P2SEG_BASE)
197 1.28 uch #define SH3_P1SEG_TO_P2SEG(x) ((u_int32_t)(x) | 0x20000000)
198 1.14 uch
199 1.14 uch /* run on P2 */
200 1.28 uch #define RUN_P2 \
201 1.14 uch do { \
202 1.14 uch u_int32_t p; \
203 1.14 uch p = (u_int32_t)&&P2; \
204 1.14 uch goto *(u_int32_t *)(p | 0x20000000); \
205 1.26 uch P2: (void)0; \
206 1.14 uch } while (/*CONSTCOND*/0)
207 1.14 uch
208 1.14 uch /* run on P1 */
209 1.28 uch #define RUN_P1 \
210 1.14 uch do { \
211 1.14 uch u_int32_t p; \
212 1.14 uch p = (u_int32_t)&&P1; \
213 1.14 uch __asm__ __volatile__("nop;nop;nop;nop;nop;nop;nop;nop"); \
214 1.14 uch goto *(u_int32_t *)(p & ~0x20000000); \
215 1.26 uch P1: (void)0; \
216 1.14 uch } while (/*CONSTCOND*/0)
217 1.27 msaitoh
218 1.27 msaitoh #if defined(SH4)
219 1.27 msaitoh /* SH4 Processor Version Register */
220 1.27 msaitoh #define SH4_PVR_ADDR 0xff000030 /* P4 address */
221 1.27 msaitoh #define SH4_PVR (*(volatile unsigned int *) SH4_PVR_ADDR)
222 1.30 msaitoh #define SH4_PRR_ADDR 0xff000044 /* P4 address */
223 1.30 msaitoh #define SH4_PRR (*(volatile unsigned int *) SH4_PRR_ADDR)
224 1.27 msaitoh
225 1.27 msaitoh #define SH4_PVR_MASK 0xffffff00
226 1.27 msaitoh #define SH4_PVR_SH7750 0x04020500 /* SH7750 */
227 1.27 msaitoh #define SH4_PVR_SH7750S 0x04020600 /* SH7750S */
228 1.30 msaitoh #define SH4_PVR_SH775xR 0x04050000 /* SH775xR */
229 1.27 msaitoh #define SH4_PVR_SH7751 0x04110000 /* SH7751 */
230 1.30 msaitoh
231 1.30 msaitoh #define SH4_PRR_MASK 0xfffffff0
232 1.30 msaitoh #define SH4_PRR_7750R 0x00000100 /* SH7750R */
233 1.30 msaitoh #define SH4_PRR_7751R 0x00000110 /* SH7751R */
234 1.27 msaitoh #endif
235 1.1 itojun
236 1.1 itojun /*
237 1.1 itojun * pull in #defines for kinds of processors
238 1.1 itojun */
239 1.1 itojun #include <machine/cputypes.h>
240 1.1 itojun
241 1.22 uch /*
242 1.22 uch * CTL_MACHDEP definitions.
243 1.22 uch */
244 1.22 uch #define CPU_CONSDEV 1 /* dev_t: console terminal device */
245 1.22 uch #define CPU_LOADANDRESET 2 /* load kernel image and reset */
246 1.22 uch #define CPU_MAXID 3 /* number of valid machdep ids */
247 1.22 uch
248 1.22 uch #define CTL_MACHDEP_NAMES { \
249 1.22 uch { 0, 0 }, \
250 1.22 uch { "console_device", CTLTYPE_STRUCT }, \
251 1.22 uch { "load_and_reset", CTLTYPE_INT }, \
252 1.22 uch }
253 1.1 itojun
254 1.25 uch #ifdef _KERNEL
255 1.25 uch void sh_cpu_init(int, int);
256 1.25 uch void sh_startup(void);
257 1.25 uch void cpu_reset(void); /* Soft reset */
258 1.25 uch void _cpu_spin(u_int32_t); /* for delay loop. */
259 1.25 uch void delay(int);
260 1.25 uch struct pcb;
261 1.25 uch void savectx(struct pcb *);
262 1.25 uch void dumpsys(void);
263 1.25 uch #endif /* _KERNEL */
264 1.1 itojun #endif /* !_SH3_CPU_H_ */
265 1.25 uch
266