cpu.h revision 1.29
1 /* $NetBSD: cpu.h,v 1.29 2002/05/07 04:01:59 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. All rights reserved. 5 * Copyright (c) 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * William Jolitz. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * @(#)cpu.h 5.4 (Berkeley) 5/9/91 40 */ 41 42 /* 43 * SH3/SH4 support. 44 * 45 * T.Horiuchi Brains Corp. 5/22/98 46 */ 47 48 #ifndef _SH3_CPU_H_ 49 #define _SH3_CPU_H_ 50 51 #if defined(_KERNEL_OPT) 52 #include "opt_lockdebug.h" 53 #endif 54 55 #include <sys/sched.h> 56 #include <sh3/psl.h> 57 #include <sh3/frame.h> 58 59 #ifdef _KERNEL 60 struct cpu_info { 61 struct schedstate_percpu ci_schedstate; /* scheduler state */ 62 #if defined(DIAGNOSTIC) || defined(LOCKDEBUG) 63 u_long ci_spin_locks; /* # of spin locks held */ 64 u_long ci_simple_locks; /* # of simple locks held */ 65 #endif 66 }; 67 68 extern struct cpu_info cpu_info_store; 69 #define curcpu() (&cpu_info_store) 70 71 /* 72 * definitions of cpu-dependent requirements 73 * referenced in generic code 74 */ 75 #define cpu_wait(p) /* nothing */ 76 #define cpu_number() 0 77 /* 78 * Can't swapout u-area, (__SWAP_BROKEN) 79 * since we use P1 converted address for trapframe. 80 */ 81 #define cpu_swapin(p) /* nothing */ 82 #define cpu_swapout(p) panic("cpu_swapout: can't get here"); 83 84 /* 85 * Arguments to hardclock and gatherstats encapsulate the previous 86 * machine state in an opaque clockframe. 87 */ 88 struct clockframe { 89 int spc; /* program counter at time of interrupt */ 90 int ssr; /* status register at time of interrupt */ 91 int ssp; /* stack pointer at time of interrupt */ 92 }; 93 94 #define CLKF_USERMODE(cf) (!KERNELMODE((cf)->ssr)) 95 #define CLKF_BASEPRI(cf) (((cf)->ssr & 0xf0) == 0) 96 #define CLKF_PC(cf) ((cf)->spc) 97 #define CLKF_INTR(cf) 0 /* XXX */ 98 99 /* 100 * This is used during profiling to integrate system time. It can safely 101 * assume that the process is resident. 102 */ 103 #define PROC_PC(p) \ 104 (((struct trapframe *)(p)->p_md.md_regs)->tf_spc) 105 106 /* 107 * Preempt the current process if in interrupt from user mode, 108 * or after the current trap/syscall if in system mode. 109 */ 110 #define need_resched(ci) \ 111 do { \ 112 want_resched = 1; \ 113 if (curproc != NULL) \ 114 aston(curproc); \ 115 } while (/*CONSTCOND*/0) 116 117 /* 118 * Give a profiling tick to the current process when the user profiling 119 * buffer pages are invalid. On the MIPS, request an ast to send us 120 * through trap, marking the proc as needing a profiling tick. 121 */ 122 #define need_proftick(p) \ 123 do { \ 124 (p)->p_flag |= P_OWEUPC; \ 125 aston(p); \ 126 } while (/*CONSTCOND*/0) 127 128 /* 129 * Notify the current process (p) that it has a signal pending, 130 * process as soon as possible. 131 */ 132 #define signotify(p) aston(p) 133 134 #define aston(p) ((p)->p_md.md_astpending = 1) 135 136 extern int want_resched; /* need_resched() was called */ 137 138 /* 139 * We need a machine-independent name for this. 140 */ 141 #define DELAY(x) delay(x) 142 #endif /* _KERNEL */ 143 144 /* 145 * Logical address space of SH3/SH4 CPU. 146 */ 147 #define SH3_PHYS_MASK 0x1fffffff 148 149 #define SH3_P0SEG_BASE 0x00000000 /* TLB mapped, also U0SEG */ 150 #define SH3_P0SEG_END 0x7fffffff 151 #define SH3_P1SEG_BASE 0x80000000 /* pa == va */ 152 #define SH3_P1SEG_END 0x9fffffff 153 #define SH3_P2SEG_BASE 0xa0000000 /* pa == va, non-cacheable */ 154 #define SH3_P2SEG_END 0xbfffffff 155 #define SH3_P3SEG_BASE 0xc0000000 /* TLB mapped, kernel mode */ 156 #define SH3_P3SEG_END 0xdfffffff 157 #define SH3_P4SEG_BASE 0xe0000000 /* peripheral space */ 158 #define SH3_P4SEG_END 0xffffffff 159 160 #define SH3_P1SEG_TO_PHYS(x) ((u_int32_t)(x) & SH3_PHYS_MASK) 161 #define SH3_P2SEG_TO_PHYS(x) ((u_int32_t)(x) & SH3_PHYS_MASK) 162 #define SH3_PHYS_TO_P1SEG(x) ((u_int32_t)(x) | SH3_P1SEG_BASE) 163 #define SH3_PHYS_TO_P2SEG(x) ((u_int32_t)(x) | SH3_P2SEG_BASE) 164 #define SH3_P1SEG_TO_P2SEG(x) ((u_int32_t)(x) | 0x20000000) 165 166 /* run on P2 */ 167 #define RUN_P2 \ 168 do { \ 169 u_int32_t p; \ 170 p = (u_int32_t)&&P2; \ 171 goto *(u_int32_t *)(p | 0x20000000); \ 172 P2: (void)0; \ 173 } while (/*CONSTCOND*/0) 174 175 /* run on P1 */ 176 #define RUN_P1 \ 177 do { \ 178 u_int32_t p; \ 179 p = (u_int32_t)&&P1; \ 180 __asm__ __volatile__("nop;nop;nop;nop;nop;nop;nop;nop"); \ 181 goto *(u_int32_t *)(p & ~0x20000000); \ 182 P1: (void)0; \ 183 } while (/*CONSTCOND*/0) 184 185 #if defined(SH4) 186 /* SH4 Processor Version Register */ 187 #define SH4_PVR_ADDR 0xff000030 /* P4 address */ 188 #define SH4_PVR (*(volatile unsigned int *) SH4_PVR_ADDR) 189 190 #define SH4_PVR_MASK 0xffffff00 191 #define SH4_PVR_SH7750 0x04020500 /* SH7750 */ 192 #define SH4_PVR_SH7750S 0x04020600 /* SH7750S */ 193 #define SH4_PVR_SH7751 0x04110000 /* SH7751 */ 194 #endif 195 196 /* 197 * pull in #defines for kinds of processors 198 */ 199 #include <machine/cputypes.h> 200 201 /* 202 * CTL_MACHDEP definitions. 203 */ 204 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 205 #define CPU_LOADANDRESET 2 /* load kernel image and reset */ 206 #define CPU_MAXID 3 /* number of valid machdep ids */ 207 208 #define CTL_MACHDEP_NAMES { \ 209 { 0, 0 }, \ 210 { "console_device", CTLTYPE_STRUCT }, \ 211 { "load_and_reset", CTLTYPE_INT }, \ 212 } 213 214 #ifdef _KERNEL 215 void sh_cpu_init(int, int); 216 void sh_startup(void); 217 void cpu_reset(void); /* Soft reset */ 218 void _cpu_spin(u_int32_t); /* for delay loop. */ 219 void delay(int); 220 struct pcb; 221 void savectx(struct pcb *); 222 void dumpsys(void); 223 #endif /* _KERNEL */ 224 #endif /* !_SH3_CPU_H_ */ 225 226
Indexes created Fri Sep 26 08:10:20 GMT 2025