cpu.h revision 1.42
1 /* $NetBSD: cpu.h,v 1.42 2007/02/09 21:55:12 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. All rights reserved. 5 * Copyright (c) 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * William Jolitz. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * @(#)cpu.h 5.4 (Berkeley) 5/9/91 36 */ 37 38 /* 39 * SH3/SH4 support. 40 * 41 * T.Horiuchi Brains Corp. 5/22/98 42 */ 43 44 #ifndef _SH3_CPU_H_ 45 #define _SH3_CPU_H_ 46 47 #if defined(_KERNEL_OPT) 48 #include "opt_lockdebug.h" 49 #endif 50 51 #include <sh3/psl.h> 52 #include <sh3/frame.h> 53 54 #ifdef _KERNEL 55 #include <sys/cpu_data.h> 56 struct cpu_info { 57 struct cpu_data ci_data; /* MI per-cpu data */ 58 int ci_mtx_count; 59 int ci_mtx_oldspl; 60 }; 61 62 extern struct cpu_info cpu_info_store; 63 #define curcpu() (&cpu_info_store) 64 65 /* 66 * definitions of cpu-dependent requirements 67 * referenced in generic code 68 */ 69 #define cpu_number() 0 70 /* 71 * Can't swapout u-area, (__SWAP_BROKEN) 72 * since we use P1 converted address for trapframe. 73 */ 74 #define cpu_swapin(p) /* nothing */ 75 #define cpu_swapout(p) panic("cpu_swapout: can't get here"); 76 #define cpu_proc_fork(p1, p2) /* nothing */ 77 78 /* 79 * Arguments to hardclock and gatherstats encapsulate the previous 80 * machine state in an opaque clockframe. 81 */ 82 struct clockframe { 83 int spc; /* program counter at time of interrupt */ 84 int ssr; /* status register at time of interrupt */ 85 int ssp; /* stack pointer at time of interrupt */ 86 }; 87 88 #define CLKF_USERMODE(cf) (!KERNELMODE((cf)->ssr)) 89 #define CLKF_BASEPRI(cf) (((cf)->ssr & 0xf0) == 0) 90 #define CLKF_PC(cf) ((cf)->spc) 91 #define CLKF_INTR(cf) 0 /* XXX */ 92 93 /* 94 * This is used during profiling to integrate system time. It can safely 95 * assume that the process is resident. 96 */ 97 #define PROC_PC(p) \ 98 (((struct trapframe *)(p)->p_md.md_regs)->tf_spc) 99 100 /* 101 * Preempt the current process if in interrupt from user mode, 102 * or after the current trap/syscall if in system mode. 103 */ 104 #define cpu_need_resched(ci) \ 105 do { \ 106 want_resched = 1; \ 107 if (curlwp != NULL) \ 108 aston(curlwp); \ 109 } while (/*CONSTCOND*/0) 110 111 /* 112 * Give a profiling tick to the current process when the user profiling 113 * buffer pages are invalid. On the MIPS, request an ast to send us 114 * through trap, marking the proc as needing a profiling tick. 115 */ 116 #define cpu_need_proftick(l) \ 117 do { \ 118 (l)->l_pflag |= LP_OWEUPC; \ 119 aston(l); \ 120 } while (/*CONSTCOND*/0) 121 122 /* 123 * Notify the current process (p) that it has a signal pending, 124 * process as soon as possible. 125 */ 126 #define cpu_signotify(l) aston(l) 127 128 #define aston(l) ((l)->l_md.md_astpending = 1) 129 130 extern int want_resched; /* need_resched() was called */ 131 132 /* 133 * We need a machine-independent name for this. 134 */ 135 #define DELAY(x) delay(x) 136 #endif /* _KERNEL */ 137 138 /* 139 * Logical address space of SH3/SH4 CPU. 140 */ 141 #define SH3_PHYS_MASK 0x1fffffff 142 143 #define SH3_P0SEG_BASE 0x00000000 /* TLB mapped, also U0SEG */ 144 #define SH3_P0SEG_END 0x7fffffff 145 #define SH3_P1SEG_BASE 0x80000000 /* pa == va */ 146 #define SH3_P1SEG_END 0x9fffffff 147 #define SH3_P2SEG_BASE 0xa0000000 /* pa == va, non-cacheable */ 148 #define SH3_P2SEG_END 0xbfffffff 149 #define SH3_P3SEG_BASE 0xc0000000 /* TLB mapped, kernel mode */ 150 #define SH3_P3SEG_END 0xdfffffff 151 #define SH3_P4SEG_BASE 0xe0000000 /* peripheral space */ 152 #define SH3_P4SEG_END 0xffffffff 153 154 #define SH3_P1SEG_TO_PHYS(x) ((uint32_t)(x) & SH3_PHYS_MASK) 155 #define SH3_P2SEG_TO_PHYS(x) ((uint32_t)(x) & SH3_PHYS_MASK) 156 #define SH3_PHYS_TO_P1SEG(x) ((uint32_t)(x) | SH3_P1SEG_BASE) 157 #define SH3_PHYS_TO_P2SEG(x) ((uint32_t)(x) | SH3_P2SEG_BASE) 158 #define SH3_P1SEG_TO_P2SEG(x) ((uint32_t)(x) | 0x20000000) 159 #define SH3_P2SEG_TO_P1SEG(x) ((uint32_t)(x) & ~0x20000000) 160 161 #ifndef __lint__ 162 163 /* switch from P1 to P2 */ 164 #define RUN_P2 do { \ 165 void *p; \ 166 p = &&P2; \ 167 goto *(void *)SH3_P1SEG_TO_P2SEG(p); \ 168 P2: (void)0; \ 169 } while (0) 170 171 /* switch from P2 to P1 */ 172 #define RUN_P1 do { \ 173 void *p; \ 174 p = &&P1; \ 175 __asm volatile("nop;nop;nop;nop;nop;nop;nop;nop"); \ 176 goto *(void *)SH3_P2SEG_TO_P1SEG(p); \ 177 P1: (void)0; \ 178 } while (0) 179 180 #else /* __lint__ */ 181 #define RUN_P2 do {} while (/* CONSTCOND */ 0) 182 #define RUN_P1 do {} while (/* CONSTCOND */ 0) 183 #endif 184 185 #if defined(SH4) 186 /* SH4 Processor Version Register */ 187 #define SH4_PVR_ADDR 0xff000030 /* P4 address */ 188 #define SH4_PVR (*(volatile uint32_t *) SH4_PVR_ADDR) 189 #define SH4_PRR_ADDR 0xff000044 /* P4 address */ 190 #define SH4_PRR (*(volatile uint32_t *) SH4_PRR_ADDR) 191 192 #define SH4_PVR_MASK 0xffffff00 193 #define SH4_PVR_SH7750 0x04020500 /* SH7750 */ 194 #define SH4_PVR_SH7750S 0x04020600 /* SH7750S */ 195 #define SH4_PVR_SH775xR 0x04050000 /* SH775xR */ 196 #define SH4_PVR_SH7751 0x04110000 /* SH7751 */ 197 198 #define SH4_PRR_MASK 0xfffffff0 199 #define SH4_PRR_7750R 0x00000100 /* SH7750R */ 200 #define SH4_PRR_7751R 0x00000110 /* SH7751R */ 201 #endif 202 203 /* 204 * pull in #defines for kinds of processors 205 */ 206 #include <machine/cputypes.h> 207 208 /* 209 * CTL_MACHDEP definitions. 210 */ 211 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 212 #define CPU_LOADANDRESET 2 /* load kernel image and reset */ 213 #define CPU_MAXID 3 /* number of valid machdep ids */ 214 215 #define CTL_MACHDEP_NAMES { \ 216 { 0, 0 }, \ 217 { "console_device", CTLTYPE_STRUCT }, \ 218 { "load_and_reset", CTLTYPE_INT }, \ 219 } 220 221 #ifdef _KERNEL 222 void sh_cpu_init(int, int); 223 void sh_startup(void); 224 void cpu_reset(void) __attribute__((__noreturn__)); /* soft reset */ 225 void _cpu_spin(uint32_t); /* for delay loop. */ 226 void delay(int); 227 struct pcb; 228 void savectx(struct pcb *); 229 void dumpsys(void); 230 #endif /* _KERNEL */ 231 #endif /* !_SH3_CPU_H_ */ 232
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