dacreg.h revision 1.1 1 1.1 uwe /* $NetBSD: dacreg.h,v 1.1 2003/11/05 03:08:13 uwe Exp $ */
2 1.1 uwe
3 1.1 uwe /*
4 1.1 uwe * Copyright (c) 2003 Valeriy E. Ushakov
5 1.1 uwe * All rights reserved.
6 1.1 uwe *
7 1.1 uwe * Redistribution and use in source and binary forms, with or without
8 1.1 uwe * modification, are permitted provided that the following conditions
9 1.1 uwe * are met:
10 1.1 uwe * 1. Redistributions of source code must retain the above copyright
11 1.1 uwe * notice, this list of conditions and the following disclaimer.
12 1.1 uwe * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 uwe * notice, this list of conditions and the following disclaimer in the
14 1.1 uwe * documentation and/or other materials provided with the distribution.
15 1.1 uwe * 3. The name of the author may not be used to endorse or promote products
16 1.1 uwe * derived from this software without specific prior written permission
17 1.1 uwe *
18 1.1 uwe * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 1.1 uwe * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 1.1 uwe * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 1.1 uwe * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 1.1 uwe * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 1.1 uwe * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 1.1 uwe * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 1.1 uwe * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 1.1 uwe * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 1.1 uwe * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 1.1 uwe */
29 1.1 uwe
30 1.1 uwe #ifndef _SH3_DACREG_H_
31 1.1 uwe #define _SH3_DACREG_H_
32 1.1 uwe
33 1.1 uwe /* D/A data registers for channels 0 and 1 */
34 1.1 uwe #define SH7709_DADR0 0xa40000a0
35 1.1 uwe #define SH7709_DADR1 0xa40000a2
36 1.1 uwe
37 1.1 uwe /* D/A control register */
38 1.1 uwe #define SH7709_DACR 0xa40000a4
39 1.1 uwe
40 1.1 uwe #define SH7709_DACR_DAOE1 0x80 /* output enable for channel 1 */
41 1.1 uwe #define SH7709_DACR_DAOE0 0x40 /* output enable for channel 0 */
42 1.1 uwe #define SH7709_DACR_DAE 0x20 /* D/A enable */
43 1.1 uwe
44 1.1 uwe #define SH7709_DACR_BITS \
45 1.1 uwe "\177\020" "b\07DAOE1\0" "b\06DAOE0\0" "b\05DAE\0"
46 1.1 uwe
47 1.1 uwe #endif /* _SH3_DACREG_H_ */
48