devreg.h revision 1.7 1 1.7 andvar /* $NetBSD: devreg.h,v 1.7 2021/10/06 20:36:58 andvar Exp $ */
2 1.1 uch
3 1.1 uch /*-
4 1.1 uch * Copyright (c) 2002 The NetBSD Foundation, Inc.
5 1.1 uch * All rights reserved.
6 1.1 uch *
7 1.1 uch * Redistribution and use in source and binary forms, with or without
8 1.1 uch * modification, are permitted provided that the following conditions
9 1.1 uch * are met:
10 1.1 uch * 1. Redistributions of source code must retain the above copyright
11 1.1 uch * notice, this list of conditions and the following disclaimer.
12 1.1 uch * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 uch * notice, this list of conditions and the following disclaimer in the
14 1.1 uch * documentation and/or other materials provided with the distribution.
15 1.1 uch *
16 1.1 uch * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 1.1 uch * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 1.1 uch * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 1.1 uch * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 1.1 uch * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 1.1 uch * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 1.1 uch * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 1.1 uch * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 1.1 uch * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 1.1 uch * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 1.1 uch * POSSIBILITY OF SUCH DAMAGE.
27 1.1 uch */
28 1.1 uch
29 1.1 uch #ifndef _SH3_DEVREG_H_
30 1.2 uch #define _SH3_DEVREG_H_
31 1.1 uch /*
32 1.7 andvar * SH embedded device register defines.
33 1.1 uch */
34 1.1 uch
35 1.1 uch /*
36 1.1 uch * Access method
37 1.1 uch */
38 1.5 uwe #define _reg_read_1(a) (*(volatile uint8_t *)((vaddr_t)(a)))
39 1.5 uwe #define _reg_read_2(a) (*(volatile uint16_t *)((vaddr_t)(a)))
40 1.5 uwe #define _reg_read_4(a) (*(volatile uint32_t *)((vaddr_t)(a)))
41 1.1 uch #define _reg_write_1(a, v) \
42 1.5 uwe (*(volatile uint8_t *)(a) = (uint8_t)(v))
43 1.1 uch #define _reg_write_2(a, v) \
44 1.5 uwe (*(volatile uint16_t *)(a) = (uint16_t)(v))
45 1.1 uch #define _reg_write_4(a, v) \
46 1.5 uwe (*(volatile uint32_t *)(a) = (uint32_t)(v))
47 1.3 tsutsui #define _reg_bset_1(a, v) \
48 1.5 uwe (*(volatile uint8_t *)(a) |= (uint8_t)(v))
49 1.3 tsutsui #define _reg_bset_2(a, v) \
50 1.5 uwe (*(volatile uint16_t *)(a) |= (uint16_t)(v))
51 1.3 tsutsui #define _reg_bset_4(a, v) \
52 1.5 uwe (*(volatile uint32_t *)(a) |= (uint32_t)(v))
53 1.3 tsutsui #define _reg_bclr_1(a, v) \
54 1.5 uwe (*(volatile uint8_t *)(a) &= ~(uint8_t)(v))
55 1.3 tsutsui #define _reg_bclr_2(a, v) \
56 1.5 uwe (*(volatile uint16_t *)(a) &= ~(uint16_t)(v))
57 1.3 tsutsui #define _reg_bclr_4(a, v) \
58 1.5 uwe (*(volatile uint32_t *)(a) &= ~(uint32_t)(v))
59 1.1 uch
60 1.1 uch /*
61 1.1 uch * Register address.
62 1.1 uch */
63 1.1 uch #if defined(SH3) && defined(SH4)
64 1.2 uch #define SH_(x) __sh_ ## x
65 1.1 uch #elif defined(SH3)
66 1.2 uch #define SH_(x) SH3_ ## x
67 1.1 uch #elif defined(SH4)
68 1.2 uch #define SH_(x) SH4_ ## x
69 1.1 uch #endif
70 1.1 uch
71 1.1 uch #ifndef _LOCORE
72 1.1 uch /* Initialize register address for SH3 && SH4 kernel. */
73 1.1 uch void sh_devreg_init(void);
74 1.1 uch #endif
75 1.1 uch #endif /* !_SH3_DEVREG_H_ */
76