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dmacreg.h revision 1.4
      1  1.4  rillig /*	$NetBSD: dmacreg.h,v 1.4 2025/09/29 20:08:54 rillig Exp $ */
      2  1.1     uwe 
      3  1.1     uwe /*
      4  1.1     uwe  * Copyright (c) 2004 Valeriy E. Ushakov
      5  1.1     uwe  * All rights reserved.
      6  1.1     uwe  *
      7  1.1     uwe  * Redistribution and use in source and binary forms, with or without
      8  1.1     uwe  * modification, are permitted provided that the following conditions
      9  1.1     uwe  * are met:
     10  1.1     uwe  * 1. Redistributions of source code must retain the above copyright
     11  1.1     uwe  *    notice, this list of conditions and the following disclaimer.
     12  1.1     uwe  * 2. Redistributions in binary form must reproduce the above copyright
     13  1.1     uwe  *    notice, this list of conditions and the following disclaimer in the
     14  1.1     uwe  *    documentation and/or other materials provided with the distribution.
     15  1.1     uwe  * 3. The name of the author may not be used to endorse or promote products
     16  1.1     uwe  *    derived from this software without specific prior written permission
     17  1.1     uwe  *
     18  1.1     uwe  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     19  1.1     uwe  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     20  1.1     uwe  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     21  1.1     uwe  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     22  1.1     uwe  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     23  1.1     uwe  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     24  1.1     uwe  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     25  1.1     uwe  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     26  1.1     uwe  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     27  1.1     uwe  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     28  1.1     uwe  */
     29  1.1     uwe 
     30  1.1     uwe #ifndef _SH3_DMACREG_H_
     31  1.1     uwe #define _SH3_DMACREG_H_
     32  1.1     uwe 
     33  1.3     uwe #include <sh3/devreg.h>
     34  1.3     uwe 
     35  1.3     uwe 
     36  1.1     uwe #define SH3_DMAC_SAR0		0xa4000020 /* Source Address */
     37  1.1     uwe #define SH3_DMAC_DAR0		0xa4000024 /* Destination Address */
     38  1.1     uwe #define SH3_DMAC_DMATCR0	0xa4000028 /* Transfer Counter */
     39  1.1     uwe #define SH3_DMAC_CHCR0		0xa400002c /* Channel Control */
     40  1.1     uwe 
     41  1.1     uwe #define SH3_DMAC_SAR1		0xa4000030 /* ditto for channel 1 */
     42  1.1     uwe #define SH3_DMAC_DAR1		0xa4000034
     43  1.1     uwe #define SH3_DMAC_DMATCR1	0xa4000038
     44  1.1     uwe #define SH3_DMAC_CHCR1		0xa400003c
     45  1.1     uwe 
     46  1.1     uwe #define SH3_DMAC_SAR2		0xa4000040 /* ditto for channel 2 */
     47  1.1     uwe #define SH3_DMAC_DAR2		0xa4000044
     48  1.1     uwe #define SH3_DMAC_DMATCR2	0xa4000048
     49  1.1     uwe #define SH3_DMAC_CHCR2		0xa400004c
     50  1.1     uwe 
     51  1.1     uwe #define SH3_DMAC_SAR3		0xa4000050 /* ditto for channel 3 */
     52  1.1     uwe #define SH3_DMAC_DAR3		0xa4000054
     53  1.1     uwe #define SH3_DMAC_DMATCR3	0xa4000058
     54  1.1     uwe #define SH3_DMAC_CHCR3		0xa400005c
     55  1.1     uwe 
     56  1.1     uwe #define SH3_DMAC_DMAOR		0xa4000060 /* DMA Operation Register */
     57  1.1     uwe 
     58  1.1     uwe #define SH3_DMAC_CMT_CMSTR	0xa4000070 /* CMT Start */
     59  1.1     uwe #define SH3_DMAC_CMT_CMCSR	0xa4000072 /* CMT Control/Status */
     60  1.1     uwe #define SH3_DMAC_CMT_CMCNT	0xa4000074 /* CMT Counter */
     61  1.1     uwe #define SH3_DMAC_CMT_CMCOR	0xa4000076 /* CMT Constant */
     62  1.1     uwe 
     63  1.1     uwe 
     64  1.1     uwe /**
     65  1.1     uwe  * Only bits 0..23 of DMATCR registers are valid.
     66  1.1     uwe  * Writing 0 to these registers means count of SH3_DMAC_DMATCR_MAX.
     67  1.1     uwe  */
     68  1.1     uwe #define SH3_DMAC_DMATCR_MAX		0x01000000
     69  1.1     uwe 
     70  1.1     uwe 
     71  1.1     uwe /**
     72  1.1     uwe  * Channel Control Register bits.
     73  1.1     uwe  */
     74  1.1     uwe 
     75  1.1     uwe /* Direct (0) or Indirect (1) mode. */
     76  1.1     uwe #define SH3_DMAC_CHCR_DI		0x00100000
     77  1.1     uwe 
     78  1.1     uwe /* Source address reload.
     79  1.1     uwe    Only valid for channel 2. */
     80  1.1     uwe #define SH3_DMAC_CHCR_RO		0x00080000
     81  1.1     uwe 
     82  1.1     uwe /* Request check level (0 - low, 1 - high).
     83  1.1     uwe    Only valid for channels 0 and 1. */
     84  1.1     uwe #define SH3_DMAC_CHCR_RL		0x00040000
     85  1.1     uwe 
     86  1.1     uwe /* Acknowledge mode (0 - read, 1 - write).
     87  1.1     uwe    Only valid for channels 0 and 1. */
     88  1.1     uwe #define SH3_DMAC_CHCR_AM		0x00020000
     89  1.1     uwe 
     90  1.1     uwe /* Acknowledge level (0 - low, 1 - high).
     91  1.1     uwe    Only valid for channels 0 and 1. */
     92  1.1     uwe #define SH3_DMAC_CHCR_AL		0x00010000
     93  1.1     uwe 
     94  1.1     uwe /* Destination address mode. */
     95  1.1     uwe #define SH3_DMAC_CHCR_DM_MASK		0x0000c000
     96  1.1     uwe #define SH3_DMAC_CHCR_DM_FIXED		0x00000000
     97  1.1     uwe #define SH3_DMAC_CHCR_DM_INC		0x00004000
     98  1.1     uwe #define SH3_DMAC_CHCR_DM_DEC		0x00008000
     99  1.1     uwe 
    100  1.1     uwe /* Source address mode. */
    101  1.1     uwe #define SH3_DMAC_CHCR_SM_MASK		0x00003000
    102  1.1     uwe #define SH3_DMAC_CHCR_SM_FIXED		0x00000000
    103  1.1     uwe #define SH3_DMAC_CHCR_SM_INC		0x00001000
    104  1.1     uwe #define SH3_DMAC_CHCR_SM_DEC		0x00002000
    105  1.1     uwe 
    106  1.1     uwe /* Resource select */
    107  1.1     uwe #define SH3_DMAC_CHCR_RS_MASK		0x00000f00
    108  1.1     uwe #define SH3_DMAC_CHCR_RS_EXT_DUAL	0x00000000
    109  1.1     uwe #define SH3_DMAC_CHCR_RS_EXT_OUT	0x00000200
    110  1.1     uwe #define SH3_DMAC_CHCR_RS_EXT_IN		0x00000300
    111  1.1     uwe #define SH3_DMAC_CHCR_RS_AUTO		0x00000400
    112  1.1     uwe #define SH3_DMAC_CHCR_RS_IRDA_TX	0x00000a00
    113  1.1     uwe #define SH3_DMAC_CHCR_RS_IRDA_RX	0x00000b00
    114  1.1     uwe #define SH3_DMAC_CHCR_RS_SCIF_TX	0x00000c00
    115  1.1     uwe #define SH3_DMAC_CHCR_RS_SCIF_RX	0x00000d00
    116  1.1     uwe #define SH3_DMAC_CHCR_RS_ADC		0x00000e00
    117  1.1     uwe #define SH3_DMAC_CHCR_RS_CMT		0x00000f00
    118  1.1     uwe 
    119  1.1     uwe /* ~DREQ select (0 - low, 1 - high).
    120  1.1     uwe    Only valid for channels 0 and 1. */
    121  1.1     uwe #define SH3_DMAC_CHCR_DS		0x00000040
    122  1.1     uwe 
    123  1.1     uwe /* Transmit mode (0 - cycle steal, 1 - burst). */
    124  1.1     uwe #define SH3_DMAC_CHCR_TM		0x00000020
    125  1.1     uwe 
    126  1.1     uwe /* Transmit size */
    127  1.1     uwe #define SH3_DMAC_CHCR_TS_MASK		0x00000018
    128  1.1     uwe #define SH3_DMAC_CHCR_TS_1		0x00000000
    129  1.1     uwe #define SH3_DMAC_CHCR_TS_2		0x00000008
    130  1.1     uwe #define SH3_DMAC_CHCR_TS_4		0x00000010
    131  1.1     uwe #define SH3_DMAC_CHCR_TS_16		0x00000018
    132  1.1     uwe 
    133  1.1     uwe /* Interrupt enable. */
    134  1.1     uwe #define SH3_DMAC_CHCR_IE		0x00000004
    135  1.1     uwe 
    136  1.1     uwe /* Transfer end. */
    137  1.1     uwe #define SH3_DMAC_CHCR_TE		0x00000002
    138  1.1     uwe 
    139  1.1     uwe /* DMAC enable. */
    140  1.1     uwe #define SH3_DMAC_CHCR_DE		0x00000001
    141  1.1     uwe 
    142  1.1     uwe #define SH3_DMAC_CHCR_BITS "\177\20"					\
    143  1.4  rillig 	"b\24DI\0"							\
    144  1.4  rillig 	"b\23RO\0"	"b\22RL\0"	"b\21AM\0"	"b\20AL\0"	\
    145  1.4  rillig 	"f\16\2DM\0"	"=\0FIXED\0"	"=\1INC\0"	"=\2DEC\0"	\
    146  1.4  rillig 	"f\14\2SM\0"	"=\0FIXED\0"	"=\1INC\0"	"=\2DEC\0"	\
    147  1.4  rillig 	"f\10\4RS\0"	"=\0EXT_DUAL\0"	"=\2EXT_OUT\0"	"=\3EXT_IN\0"	\
    148  1.4  rillig 			"=\4AUTO\0"					\
    149  1.4  rillig 			"=\12IRTX\0"	"=\13IRRX\0"	"=\14SCTX\0"	\
    150  1.4  rillig 			"=\15SCRX\0"	"=\16ADC\0"	"=\17CMT\0"	\
    151  1.4  rillig 	"b\6DS\0"	"b\5TM\0"					\
    152  1.4  rillig 	"f\3\2TS\0"	"=\0001\0"	"=\0012\0"	"=\0024\0"	\
    153  1.4  rillig 			"=\00316\0"					\
    154  1.4  rillig 	"b\2IE\0"	"b\1TE\0"	"b\0DE\0"
    155  1.1     uwe 
    156  1.1     uwe 
    157  1.1     uwe /**
    158  1.1     uwe  * DMA Operation Register bits
    159  1.1     uwe  */
    160  1.1     uwe 
    161  1.1     uwe /* Priority mode. */
    162  1.1     uwe #define SH3_DMAC_DMAOR_PR_MASK		0x0300
    163  1.1     uwe #define SH3_DMAC_DMAOR_PR_0123		0x0000 /* 0 > 1 > 2 > 3 */
    164  1.1     uwe #define SH3_DMAC_DMAOR_PR_0231		0x0100 /* 0 > 2 > 3 > 1 */
    165  1.1     uwe #define SH3_DMAC_DMAOR_PR_2013		0x0200 /* 2 > 0 > 1 > 3 */
    166  1.1     uwe #define SH3_DMAC_DMAOR_PR_RR		0x0300 /* round robbin */
    167  1.1     uwe 
    168  1.1     uwe /* Address error flag. */
    169  1.1     uwe #define SH3_DMAC_DMAOR_AE		0x0004
    170  1.1     uwe 
    171  1.1     uwe /* NMI flag. */
    172  1.1     uwe #define SH3_DMAC_DMAOR_NMIF		0x0002
    173  1.1     uwe 
    174  1.1     uwe /* DMA master enable. */
    175  1.1     uwe #define SH3_DMAC_DMAOR_DME		0x0001
    176  1.1     uwe 
    177  1.4  rillig #define SH3_DMAC_DMAOR_BITS "\177\20"					\
    178  1.4  rillig 	"f\10\2PR\0" "=\0000123\0" "=\0010231\0" "=\0022013\0" "=\3RR\0"\
    179  1.1     uwe 	"b\2AE\0" "b\1NMIF\0" "b\0DME\0"
    180  1.1     uwe 
    181  1.1     uwe 
    182  1.1     uwe /**
    183  1.1     uwe  * Compare Match Timer.
    184  1.1     uwe  */
    185  1.1     uwe 
    186  1.1     uwe /* Start the CMT. */
    187  1.1     uwe #define SH3_DMAC_CMT_CMSTR_STR		0x0001
    188  1.1     uwe 
    189  1.1     uwe /* Compare Match Flag. */
    190  1.1     uwe #define SH3_DMAC_CMT_CMCSR_CMF		0x0080
    191  1.1     uwe 
    192  1.1     uwe /* Clock select (PCLOCK/x). */
    193  1.1     uwe #define SH3_DMAC_CMT_CMCSR_CKS_MASK	0x0003
    194  1.1     uwe #define SH3_DMAC_CMT_CMCSR_CKS_4	0x0000
    195  1.1     uwe #define SH3_DMAC_CMT_CMCSR_CKS_8	0x0001
    196  1.1     uwe #define SH3_DMAC_CMT_CMCSR_CKS_16	0x0002
    197  1.1     uwe #define SH3_DMAC_CMT_CMCSR_CKS_64	0x0003
    198  1.1     uwe 
    199  1.1     uwe #define SH3_DMAC_CMT_CMCSR_BITS "\177\20"				\
    200  1.1     uwe 	"b\7CMF\0"							\
    201  1.4  rillig 	"f\0\2CKS\0" "=\0001/4\0" "=\0011/8\0" "=\0021/16\0" "=\0031/64\0"
    202  1.1     uwe 
    203  1.1     uwe #endif /* _SH3_DMACREG_H_ */
    204