dmacreg.h revision 1.1
1 /* $NetBSD: dmacreg.h,v 1.1 2004/04/08 21:02:57 uwe Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Valeriy E. Ushakov 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #ifndef _SH3_DMACREG_H_ 31 #define _SH3_DMACREG_H_ 32 33 #define SH3_DMAC_SAR0 0xa4000020 /* Source Address */ 34 #define SH3_DMAC_DAR0 0xa4000024 /* Destination Address */ 35 #define SH3_DMAC_DMATCR0 0xa4000028 /* Transfer Counter */ 36 #define SH3_DMAC_CHCR0 0xa400002c /* Channel Control */ 37 38 #define SH3_DMAC_SAR1 0xa4000030 /* ditto for channel 1 */ 39 #define SH3_DMAC_DAR1 0xa4000034 40 #define SH3_DMAC_DMATCR1 0xa4000038 41 #define SH3_DMAC_CHCR1 0xa400003c 42 43 #define SH3_DMAC_SAR2 0xa4000040 /* ditto for channel 2 */ 44 #define SH3_DMAC_DAR2 0xa4000044 45 #define SH3_DMAC_DMATCR2 0xa4000048 46 #define SH3_DMAC_CHCR2 0xa400004c 47 48 #define SH3_DMAC_SAR3 0xa4000050 /* ditto for channel 3 */ 49 #define SH3_DMAC_DAR3 0xa4000054 50 #define SH3_DMAC_DMATCR3 0xa4000058 51 #define SH3_DMAC_CHCR3 0xa400005c 52 53 #define SH3_DMAC_DMAOR 0xa4000060 /* DMA Operation Register */ 54 55 #define SH3_DMAC_CMT_CMSTR 0xa4000070 /* CMT Start */ 56 #define SH3_DMAC_CMT_CMCSR 0xa4000072 /* CMT Control/Status */ 57 #define SH3_DMAC_CMT_CMCNT 0xa4000074 /* CMT Counter */ 58 #define SH3_DMAC_CMT_CMCOR 0xa4000076 /* CMT Constant */ 59 60 61 /** 62 * Only bits 0..23 of DMATCR registers are valid. 63 * Writing 0 to these registers means count of SH3_DMAC_DMATCR_MAX. 64 */ 65 #define SH3_DMAC_DMATCR_MAX 0x01000000 66 67 68 /** 69 * Channel Control Register bits. 70 */ 71 72 /* Direct (0) or Indirect (1) mode. */ 73 #define SH3_DMAC_CHCR_DI 0x00100000 74 75 /* Source address reload. 76 Only valid for channel 2. */ 77 #define SH3_DMAC_CHCR_RO 0x00080000 78 79 /* Request check level (0 - low, 1 - high). 80 Only valid for channels 0 and 1. */ 81 #define SH3_DMAC_CHCR_RL 0x00040000 82 83 /* Acknowledge mode (0 - read, 1 - write). 84 Only valid for channels 0 and 1. */ 85 #define SH3_DMAC_CHCR_AM 0x00020000 86 87 /* Acknowledge level (0 - low, 1 - high). 88 Only valid for channels 0 and 1. */ 89 #define SH3_DMAC_CHCR_AL 0x00010000 90 91 /* Destination address mode. */ 92 #define SH3_DMAC_CHCR_DM_MASK 0x0000c000 93 #define SH3_DMAC_CHCR_DM_FIXED 0x00000000 94 #define SH3_DMAC_CHCR_DM_INC 0x00004000 95 #define SH3_DMAC_CHCR_DM_DEC 0x00008000 96 97 /* Source address mode. */ 98 #define SH3_DMAC_CHCR_SM_MASK 0x00003000 99 #define SH3_DMAC_CHCR_SM_FIXED 0x00000000 100 #define SH3_DMAC_CHCR_SM_INC 0x00001000 101 #define SH3_DMAC_CHCR_SM_DEC 0x00002000 102 103 /* Resource select */ 104 #define SH3_DMAC_CHCR_RS_MASK 0x00000f00 105 #define SH3_DMAC_CHCR_RS_EXT_DUAL 0x00000000 106 #define SH3_DMAC_CHCR_RS_EXT_OUT 0x00000200 107 #define SH3_DMAC_CHCR_RS_EXT_IN 0x00000300 108 #define SH3_DMAC_CHCR_RS_AUTO 0x00000400 109 #define SH3_DMAC_CHCR_RS_IRDA_TX 0x00000a00 110 #define SH3_DMAC_CHCR_RS_IRDA_RX 0x00000b00 111 #define SH3_DMAC_CHCR_RS_SCIF_TX 0x00000c00 112 #define SH3_DMAC_CHCR_RS_SCIF_RX 0x00000d00 113 #define SH3_DMAC_CHCR_RS_ADC 0x00000e00 114 #define SH3_DMAC_CHCR_RS_CMT 0x00000f00 115 116 /* ~DREQ select (0 - low, 1 - high). 117 Only valid for channels 0 and 1. */ 118 #define SH3_DMAC_CHCR_DS 0x00000040 119 120 /* Transmit mode (0 - cycle steal, 1 - burst). */ 121 #define SH3_DMAC_CHCR_TM 0x00000020 122 123 /* Transmit size */ 124 #define SH3_DMAC_CHCR_TS_MASK 0x00000018 125 #define SH3_DMAC_CHCR_TS_1 0x00000000 126 #define SH3_DMAC_CHCR_TS_2 0x00000008 127 #define SH3_DMAC_CHCR_TS_4 0x00000010 128 #define SH3_DMAC_CHCR_TS_16 0x00000018 129 130 /* Interrupt enable. */ 131 #define SH3_DMAC_CHCR_IE 0x00000004 132 133 /* Transfer end. */ 134 #define SH3_DMAC_CHCR_TE 0x00000002 135 136 /* DMAC enable. */ 137 #define SH3_DMAC_CHCR_DE 0x00000001 138 139 #define SH3_DMAC_CHCR_BITS "\177\20" \ 140 "b\24DI\0" "b\23RO\0" "b\22RL\0" "b\21AM\0" "b\20AL\0" \ 141 "f\16\2DM\0" ":\0(FIXED)\0" ":\1(INC)\0" ":\2(DEC)\0" \ 142 "f\14\2SM\0" ":\0(FIXED)\0" ":\1(INC)\0" ":\2(DEC)\0" \ 143 "f\10\4RS\0" ":\0(EXT_DUAL)\0" ":\2(EXT_OUT)\0" ":\3(EXT_IN)\0" \ 144 ":\4(AUTO)\0" \ 145 ":\12(IRTX)\0" ":\13(IRRX)\0" ":\14(SCTX)\0" \ 146 ":\15(SCRX)\0" ":\16(ADC)\0" ":\17(CMT)\0" \ 147 "b\6DS\0" "b\5TM\0" \ 148 "f\3\2TS\0" ":\0(1)\0" ":\1(2)\0" ":\2(4)\0" ":\3(16)\0" \ 149 "b\2IE\0" "b\1TE\0" "b\0DE\0" 150 151 152 /** 153 * DMA Operation Register bits 154 */ 155 156 /* Priority mode. */ 157 #define SH3_DMAC_DMAOR_PR_MASK 0x0300 158 #define SH3_DMAC_DMAOR_PR_0123 0x0000 /* 0 > 1 > 2 > 3 */ 159 #define SH3_DMAC_DMAOR_PR_0231 0x0100 /* 0 > 2 > 3 > 1 */ 160 #define SH3_DMAC_DMAOR_PR_2013 0x0200 /* 2 > 0 > 1 > 3 */ 161 #define SH3_DMAC_DMAOR_PR_RR 0x0300 /* round robbin */ 162 163 /* Address error flag. */ 164 #define SH3_DMAC_DMAOR_AE 0x0004 165 166 /* NMI flag. */ 167 #define SH3_DMAC_DMAOR_NMIF 0x0002 168 169 /* DMA master enable. */ 170 #define SH3_DMAC_DMAOR_DME 0x0001 171 172 #define SH3_DMAC_DMAOR_BITS "\177\20" \ 173 "f\10\2PR\0" ":\0(0123)\0" ":\1(0231)\0" ":\2(2013)\0" ":\3(RR)\0" \ 174 "b\2AE\0" "b\1NMIF\0" "b\0DME\0" 175 176 177 /** 178 * Compare Match Timer. 179 */ 180 181 /* Start the CMT. */ 182 #define SH3_DMAC_CMT_CMSTR_STR 0x0001 183 184 /* Compare Match Flag. */ 185 #define SH3_DMAC_CMT_CMCSR_CMF 0x0080 186 187 /* Clock select (PCLOCK/x). */ 188 #define SH3_DMAC_CMT_CMCSR_CKS_MASK 0x0003 189 #define SH3_DMAC_CMT_CMCSR_CKS_4 0x0000 190 #define SH3_DMAC_CMT_CMCSR_CKS_8 0x0001 191 #define SH3_DMAC_CMT_CMCSR_CKS_16 0x0002 192 #define SH3_DMAC_CMT_CMCSR_CKS_64 0x0003 193 194 #define SH3_DMAC_CMT_CMCSR_BITS "\177\20" \ 195 "b\7CMF\0" \ 196 "f\0\2CKS\0" ":\0(1/4)\0" ":\1(1/8)\0" ":\2(1/16)\0" ":\3(1/64)\0" 197 198 #endif /* _SH3_DMACREG_H_ */ 199
Indexes created Sun Sep 28 16:09:52 GMT 2025