intcreg.h revision 1.2.2.1
1 /* $NetBSD: intcreg.h,v 1.2.2.1 2000/11/20 20:24:30 bouyer Exp $ */ 2 3 /*- 4 * Copyright (C) 1999 SAITOH Masanobu. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef _SH3_INTCREG_H__ 30 #define _SH3_INTCREG_H__ 31 32 #ifndef _BYTE_ORDER 33 #error Define _BYTE_ORDER! 34 #endif 35 36 /* 37 * Interrupt Controller 38 */ 39 struct sh3_intc { 40 /* Interrupt control register (0xFFFFFEE0) */ 41 union { 42 unsigned short WORD; /* Word Access */ 43 struct { /* Bit Access */ 44 #if _BYTE_ORDER == BIG_ENDIAN 45 /* Bit 15..0 */ 46 unsigned char NMIL:1; 47 unsigned char :6; 48 unsigned char NMIE:1; 49 unsigned char :8; 50 #else /* _BYTE_ORDER == LITTLE_ENDIAN */ 51 /* Bit 0..15 */ 52 unsigned char :8; 53 unsigned char NMIE:1; 54 unsigned char :6; 55 unsigned char NMIL:1; 56 #endif 57 } BIT; 58 } ICR; 59 60 /* Interrupt priority setting register A (FFFFFEE2) */ 61 union { 62 unsigned short WORD; /* Word Access */ 63 struct { /* Bit Access */ 64 #if _BYTE_ORDER == BIG_ENDIAN 65 /* Bit 15..0 */ 66 unsigned short TMU0 :4; 67 unsigned short TMU1 :4; 68 unsigned short TMU2 :4; 69 unsigned short RTC :4; 70 #else /* _BYTE_ORDER == LITTLE_ENDIAN */ 71 /* Bit 0..15 */ 72 unsigned short RTC :4; 73 unsigned short TMU2 :4; 74 unsigned short TMU1 :4; 75 unsigned short TMU0 :4; 76 #endif 77 } BIT; 78 } IPRA; 79 80 /* Interrupt priority setting register B (FFFFFEE4) */ 81 union { 82 unsigned short WORD; /* Word Access */ 83 struct { /* Bit Access */ 84 #if _BYTE_ORDER == BIG_ENDIAN 85 /* Bit 15..0 */ 86 unsigned short WDT :4; 87 unsigned short REF :4; 88 unsigned short SCI :4; 89 unsigned short :4; 90 #else /* _BYTE_ORDER == LITTLE_ENDIAN */ 91 /* Bit 0..15 */ 92 unsigned short :4; 93 unsigned short SCI :4; 94 unsigned short REF :4; 95 unsigned short WDT :4; 96 #endif 97 } BIT; 98 } IPRB; 99 }; 100 101 /* address definitions for interrupt controller (INTC)*/ 102 103 #if !defined(SH4) 104 105 /* SH3 definition */ 106 107 #define SHREG_ICR0 (*(volatile unsigned short *)0xfffffee0) 108 #define SHREG_IPRA (*(volatile unsigned short *)0xfffffee2) 109 #define SHREG_IPRB (*(volatile unsigned short *)0xfffffee4) 110 111 #if defined(SH7709) || defined(SH7709A) 112 #define SHREG_ICR1 (*(volatile unsigned short *)0xa4000010) 113 #define SHREG_ICR2 (*(volatile unsigned short *)0xa4000012) 114 #define SHREG_PINTER (*(volatile unsigned short *)0xa4000014) 115 #define SHREG_IPRC (*(volatile unsigned short *)0xa4000016) 116 #define SHREG_IPRD (*(volatile unsigned short *)0xa4000018) 117 #define SHREG_IPRE (*(volatile unsigned short *)0xa400001a) 118 #define SHREG_IRR0 (*(volatile unsigned char *)0xa4000004) 119 #define SHREG_IRR1 (*(volatile unsigned char *)0xa4000006) 120 #define SHREG_IRR2 (*(volatile unsigned char *)0xa4000008) 121 122 #define IPRC_IRQ3_MASK 0xf000 123 #define IPRC_IRQ2_MASK 0x0f00 124 #define IPRC_IRQ1_MASK 0x00f0 125 #define IPRC_IRQ0_MASK 0x000f 126 127 #define IPRD_PINT07_MASK 0xf000 128 #define IPRD_PINT8F_MASK 0x0f00 129 #define IPRD_IRQ5_MASK 0x00f0 130 #define IPRD_IRQ4_MASK 0x000f 131 132 #define IPRE_DMAC_MASK 0xf000 133 #define IPRE_IRDA_MASK 0x0f00 134 #define IPRE_SCIF_MASK 0x00f0 135 #define IPRE_ADC_MASK 0x000f 136 137 #endif 138 139 #else 140 141 /* SH4 definitions */ 142 143 #define SHREG_ICR (*(volatile unsigned short *)0xffd00000) 144 #define SHREG_IPRA (*(volatile unsigned short *)0xffd00004) 145 #define SHREG_IPRB (*(volatile unsigned short *)0xffd00008) 146 #define SHREG_IPRC (*(volatile unsigned short *)0xffd0000c) 147 148 149 #define IPRC_GPIO_MASK 0xf000 150 #define IPRC_DMAC_MASK 0x0f00 151 #define IPRC_SCIF_MASK 0x00f0 152 #define IPRC_HUDI_MASK 0x000f 153 154 #endif 155 156 #define IPRA_TMU0_MASK 0xf000 157 #define IPRA_TMU1_MASK 0x0f00 158 #define IPRA_TMU2_MASK 0x00f0 159 #define IPRA_RTC_MASK 0x000f 160 161 #define IPRB_WDT_MASK 0xf000 162 #define IPRB_REF_MASK 0x0f00 163 #define IPRB_SCI_MASK 0x00f0 164 165 166 #endif /* !_SH3_INTCREG_H__ */ 167
Indexes created Sat Oct 25 00:10:07 GMT 2025