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intr.h revision 1.1 
      1 /*	$NetBSD: intr.h,v 1.1 1999/09/13 10:31:19 itojun Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1996, 1997 Charles M. Hannum.  All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  * 3. All advertising materials mentioning features or use of this software
     15  *    must display the following acknowledgement:
     16  *	This product includes software developed by Charles M. Hannum.
     17  * 4. The name of the author may not be used to endorse or promote products
     18  *    derived from this software without specific prior written permission.
     19  *
     20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     21  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     22  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     23  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     26  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     27  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     29  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 /*
     33  * SH3 Version
     34  *
     35  * T.Horiuchi Brains Corp.  5/22/98
     36  */
     37 
     38 #ifndef _SH3_INTR_H_
     39 #define _SH3_INTR_H_
     40 
     41 /* Interrupt priority `levels'. */
     42 #define	IPL_NONE	9	/* nothing */
     43 #define	IPL_SOFTCLOCK	8	/* timeouts */
     44 #define	IPL_SOFTNET	7	/* protocol stacks */
     45 #define	IPL_BIO		6	/* block I/O */
     46 #define	IPL_NET		5	/* network */
     47 #define	IPL_SOFTSERIAL	4	/* serial */
     48 #define	IPL_TTY		3	/* terminal */
     49 #define	IPL_IMP		3	/* memory allocation */
     50 #define	IPL_AUDIO	2	/* audio */
     51 #define	IPL_CLOCK	1	/* clock */
     52 #define	IPL_HIGH	1	/* everything */
     53 #define	IPL_SERIAL	0	/* serial */
     54 #define	NIPL		10
     55 
     56 /* Interrupt sharing types. */
     57 #define	IST_NONE	0	/* none */
     58 #define	IST_PULSE	1	/* pulsed */
     59 #define	IST_EDGE	2	/* edge-triggered */
     60 #define	IST_LEVEL	3	/* level-triggered */
     61 
     62 #ifndef _LOCORE
     63 
     64 volatile int cpl, ipending, astpending;
     65 int imask[NIPL];
     66 
     67 extern void Xspllower __P((void));
     68 
     69 static __inline int splraise __P((int));
     70 static __inline int spllower __P((int));
     71 static __inline void splx __P((int));
     72 static __inline void softintr __P((int));
     73 
     74 /*
     75  * Add a mask to cpl, and return the old value of cpl.
     76  */
     77 static __inline int
     78 splraise(ncpl)
     79 	register int ncpl;
     80 {
     81 	int ocpl ;
     82 
     83 	ocpl = cpl;
     84 
     85 	cpl = ocpl | ncpl;
     86 	return (ocpl);
     87 }
     88 
     89 /*
     90  * Restore a value to cpl (unmasking interrupts).  If any unmasked
     91  * interrupts are pending, call Xspllower() to process them.
     92  */
     93 static __inline void
     94 splx(ncpl)
     95 	register int ncpl;
     96 {
     97 
     98 	cpl = ncpl;
     99 	if (ipending & ~ncpl)
    100 		Xspllower();
    101 }
    102 
    103 /*
    104  * Same as splx(), but we return the old value of spl, for the
    105  * benefit of some splsoftclock() callers.
    106  */
    107 static __inline int
    108 spllower(ncpl)
    109 	register int ncpl;
    110 {
    111 	register int ocpl = cpl;
    112 
    113 	cpl = ncpl;
    114 	if (ipending & ~ncpl)
    115 		Xspllower();
    116 	return (ocpl);
    117 }
    118 
    119 /*
    120  * Hardware interrupt masks
    121  */
    122 #define	splbio()	splraise(imask[IPL_BIO])
    123 #define	splnet()	splraise(imask[IPL_NET])
    124 #define	spltty()	splraise(imask[IPL_TTY])
    125 #define	splaudio()	splraise(imask[IPL_AUDIO])
    126 #define	splclock()	splraise(imask[IPL_CLOCK])
    127 #define	splstatclock()	splclock()
    128 #define	splserial()	splraise(imask[IPL_SERIAL])
    129 
    130 /*
    131  * Software interrupt masks
    132  *
    133  * NOTE: splsoftclock() is used by hardclock() to lower the priority from
    134  * clock to softclock before it calls softclock().
    135  */
    136 #define	splsoftclock()	spllower(imask[IPL_SOFTCLOCK])
    137 #define	splsoftnet()	splraise(imask[IPL_SOFTNET])
    138 #define	splsoftserial()	splraise(imask[IPL_SOFTSERIAL])
    139 
    140 /*
    141  * Miscellaneous
    142  */
    143 #define	splimp()	splraise(imask[IPL_IMP])
    144 #define	splhigh()	splraise(imask[IPL_HIGH])
    145 #define	spl0()		spllower(0)
    146 
    147 /*
    148  * Software interrupt registration
    149  *
    150  * We hand-code this to ensure that it's atomic.
    151  */
    152 static __inline void
    153 softintr(mask)
    154 	register int mask;
    155 {
    156 	ipending |= (1 << mask);
    157 }
    158 
    159 #define	setsoftast()	(astpending = 1)
    160 #define	setsoftclock()	softintr(SIR_CLOCK)
    161 #define	setsoftnet()	softintr(SIR_NET)
    162 #define	setsoftserial()	softintr(SIR_SERIAL)
    163 
    164 #endif /* !_LOCORE */
    165 
    166 #define	INTEVT_SOFT	0xf00	/* This value is stored to INTEVT reg,
    167 				   when software interrupt occured */
    168 #define INTEVT_TMU0 0x400
    169 #define INTEVT_TMU1 0x420
    170 #define INTEVT_TMU2 0x440
    171 
    172 #endif /* !_SH3_INTR_H_ */
    173