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intr.h revision 1.14 
      1 /*	$NetBSD: intr.h,v 1.14 2002/02/19 17:21:21 uch Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1996, 1997 Charles M. Hannum.  All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  * 3. All advertising materials mentioning features or use of this software
     15  *    must display the following acknowledgement:
     16  *	This product includes software developed by Charles M. Hannum.
     17  * 4. The name of the author may not be used to endorse or promote products
     18  *    derived from this software without specific prior written permission.
     19  *
     20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     21  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     22  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     23  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     26  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     27  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     29  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 /*
     33  * SH3 Version
     34  *
     35  * T.Horiuchi Brains Corp.  5/22/98
     36  */
     37 
     38 #ifndef _SH3_INTR_H_
     39 #define _SH3_INTR_H_
     40 
     41 #include <sh3/cpufunc.h>
     42 
     43 /* Interrupt sharing types. */
     44 #define	IST_NONE	0	/* none */
     45 #define	IST_PULSE	1	/* pulsed */
     46 #define	IST_EDGE	2	/* edge-triggered */
     47 #define	IST_LEVEL	3	/* level-triggered */
     48 
     49 #ifndef _LOCORE
     50 
     51 volatile int cpl, ipending, astpending;
     52 int imask[NIPL];
     53 
     54 extern void Xspllower(void);
     55 
     56 static __inline int splraise(int);
     57 static __inline void spllower(int);
     58 static __inline void softintr(int);
     59 
     60 /*
     61  * Add a mask to cpl, and return the old value of cpl.
     62  */
     63 static __inline int
     64 splraise(int ncpl)
     65 {
     66 	int ocpl ;
     67 
     68 	ocpl = cpl;
     69 
     70 	cpl = ocpl | ncpl;
     71 	return (ocpl);
     72 }
     73 
     74 /*
     75  * Restore a value to cpl (unmasking interrupts).  If any unmasked
     76  * interrupts are pending, call Xspllower() to process them.
     77  */
     78 static __inline void
     79 spllower(int ncpl)
     80 {
     81 
     82 	cpl = ncpl;
     83 	if (ipending & ~ncpl)
     84 		Xspllower();
     85 }
     86 
     87 /*
     88  * Hardware interrupt masks
     89  */
     90 #define	splbio()	splraise(imask[IPL_BIO])
     91 #define	splnet()	splraise(imask[IPL_NET])
     92 #define	spltty()	splraise(imask[IPL_TTY])
     93 #define	splaudio()	splraise(imask[IPL_AUDIO])
     94 #define	splclock()	splraise(imask[IPL_CLOCK])
     95 #define	splstatclock()	splclock()
     96 #define	splserial()	splraise(imask[IPL_SERIAL])
     97 
     98 /*
     99  * Software interrupt masks
    100  *
    101  * NOTE: splsoftclock() is used by hardclock() to lower the priority from
    102  * clock to softclock before it calls softclock().
    103  */
    104 #define	spllowersoftclock() spllower(imask[IPL_SOFTCLOCK])
    105 #define	splsoftclock()	splraise(imask[IPL_SOFTCLOCK])
    106 #define	splsoftnet()	splraise(imask[IPL_SOFTNET])
    107 #define	splsoftserial()	splraise(imask[IPL_SOFTSERIAL])
    108 
    109 /*
    110  * Miscellaneous
    111  */
    112 #define	splvm()		splraise(imask[IPL_IMP])
    113 #define	splhigh()	splraise(imask[IPL_HIGH])
    114 #define	splsched()	splhigh()
    115 #define	spllock()	splhigh()
    116 #define	spl0()		spllower(0)
    117 #define	splx(x)		spllower(x)
    118 
    119 /*
    120  * Software interrupt registration
    121  *
    122  * We hand-code this to ensure that it's atomic.
    123  */
    124 static __inline void
    125 softintr(int mask)
    126 {
    127 	int s;
    128 
    129 	s = _cpu_intr_suspend();
    130 	ipending |= (1 << mask);
    131 	_cpu_intr_resume(s);
    132 }
    133 
    134 #define	setsoftast()	(astpending = 1)
    135 #define	setsoftclock()	softintr(SIR_CLOCK)
    136 #define	setsoftnet()	softintr(SIR_NET)
    137 #define	setsoftserial()	softintr(SIR_SERIAL)
    138 
    139 #endif /* !_LOCORE */
    140 
    141 #define	INTEVT_SOFT	0xf00	/* This value is stored to INTEVT reg,
    142 				   when software interrupt occurred */
    143 #define INTEVT_TMU0 0x400
    144 #define INTEVT_TMU1 0x420
    145 #define INTEVT_TMU2 0x440
    146 
    147 #define INTEVT_SCI0_ERI	0x4e0
    148 #define INTEVT_SCI0_RXI	0x500
    149 #define INTEVT_SCI0_TXI	0x520
    150 #define INTEVT_SCI0_TEI	0x540
    151 
    152 #define INTEVT_WDT	0x560
    153 
    154 #define IS_INTEVT_SCI0(x) ((x == INTEVT_SCI0_ERI) || (x == INTEVT_SCI0_RXI) \
    155 			|| (x == INTEVT_SCI0_TXI) || (x == INTEVT_SCI0_TEI))
    156 
    157 #define	INTEVT_PRI	0x4a0	/* Periodic interrupt generated by RTC */
    158 
    159 #if defined(SH4)
    160 #define	INTEVT_SCIF	0x700
    161 #endif
    162 
    163 #endif /* !_SH3_INTR_H_ */
    164