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intr.h revision 1.5 
      1 /*	$NetBSD: intr.h,v 1.5 2000/04/13 15:36:10 msaitoh Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1996, 1997 Charles M. Hannum.  All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  * 3. All advertising materials mentioning features or use of this software
     15  *    must display the following acknowledgement:
     16  *	This product includes software developed by Charles M. Hannum.
     17  * 4. The name of the author may not be used to endorse or promote products
     18  *    derived from this software without specific prior written permission.
     19  *
     20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     21  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     22  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     23  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     26  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     27  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     29  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 /*
     33  * SH3 Version
     34  *
     35  * T.Horiuchi Brains Corp.  5/22/98
     36  */
     37 
     38 #ifndef _SH3_INTR_H_
     39 #define _SH3_INTR_H_
     40 
     41 /* Interrupt sharing types. */
     42 #define	IST_NONE	0	/* none */
     43 #define	IST_PULSE	1	/* pulsed */
     44 #define	IST_EDGE	2	/* edge-triggered */
     45 #define	IST_LEVEL	3	/* level-triggered */
     46 
     47 #ifndef _LOCORE
     48 
     49 volatile int cpl, ipending, astpending;
     50 int imask[NIPL];
     51 
     52 extern void Xspllower __P((void));
     53 
     54 static __inline int splraise __P((int));
     55 static __inline int spllower __P((int));
     56 static __inline void splx __P((int));
     57 static __inline void softintr __P((int));
     58 
     59 /*
     60  * Add a mask to cpl, and return the old value of cpl.
     61  */
     62 static __inline int
     63 splraise(ncpl)
     64 	register int ncpl;
     65 {
     66 	int ocpl ;
     67 
     68 	ocpl = cpl;
     69 
     70 	cpl = ocpl | ncpl;
     71 	return (ocpl);
     72 }
     73 
     74 /*
     75  * Restore a value to cpl (unmasking interrupts).  If any unmasked
     76  * interrupts are pending, call Xspllower() to process them.
     77  */
     78 static __inline void
     79 splx(ncpl)
     80 	register int ncpl;
     81 {
     82 
     83 	cpl = ncpl;
     84 	if (ipending & ~ncpl)
     85 		Xspllower();
     86 }
     87 
     88 /*
     89  * Same as splx(), but we return the old value of spl, for the
     90  * benefit of some splsoftclock() callers.
     91  */
     92 static __inline int
     93 spllower(ncpl)
     94 	register int ncpl;
     95 {
     96 	register int ocpl = cpl;
     97 
     98 	cpl = ncpl;
     99 	if (ipending & ~ncpl)
    100 		Xspllower();
    101 	return (ocpl);
    102 }
    103 
    104 /*
    105  * Hardware interrupt masks
    106  */
    107 #define	splbio()	splraise(imask[IPL_BIO])
    108 #define	splnet()	splraise(imask[IPL_NET])
    109 #define	spltty()	splraise(imask[IPL_TTY])
    110 #define	splaudio()	splraise(imask[IPL_AUDIO])
    111 #define	splclock()	splraise(imask[IPL_CLOCK])
    112 #define	splstatclock()	splclock()
    113 #define	splserial()	splraise(imask[IPL_SERIAL])
    114 
    115 /*
    116  * Software interrupt masks
    117  *
    118  * NOTE: splsoftclock() is used by hardclock() to lower the priority from
    119  * clock to softclock before it calls softclock().
    120  */
    121 #define	spllowersoftclock() spllower(imask[IPL_SOFTCLOCK])
    122 #define	splsoftclock()	splraise(imask[IPL_SOFTCLOCK])
    123 #define	splsoftnet()	splraise(imask[IPL_SOFTNET])
    124 #define	splsoftserial()	splraise(imask[IPL_SOFTSERIAL])
    125 
    126 /*
    127  * Miscellaneous
    128  */
    129 #define	splimp()	splraise(imask[IPL_IMP])
    130 #define	splhigh()	splraise(imask[IPL_HIGH])
    131 #define	spl0()		spllower(0)
    132 
    133 /*
    134  * Software interrupt registration
    135  *
    136  * We hand-code this to ensure that it's atomic.
    137  */
    138 static __inline void
    139 softintr(mask)
    140 	register int mask;
    141 {
    142 	extern void enable_interrupt(void);	/* XXX */
    143 	extern void disable_interrupt(void);
    144 
    145 	disable_interrupt();
    146 	ipending |= (1 << mask);
    147 	enable_interrupt();
    148 }
    149 
    150 #define	setsoftast()	(astpending = 1)
    151 #define	setsoftclock()	softintr(SIR_CLOCK)
    152 #define	setsoftnet()	softintr(SIR_NET)
    153 #define	setsoftserial()	softintr(SIR_SERIAL)
    154 
    155 #endif /* !_LOCORE */
    156 
    157 #define	INTEVT_SOFT	0xf00	/* This value is stored to INTEVT reg,
    158 				   when software interrupt occured */
    159 #define INTEVT_TMU0 0x400
    160 #define INTEVT_TMU1 0x420
    161 #define INTEVT_TMU2 0x440
    162 
    163 #define INTEVT_SCI0_ERI	0x4e0
    164 #define INTEVT_SCI0_RXI	0x500
    165 #define INTEVT_SCI0_TXI	0x520
    166 #define INTEVT_SCI0_TEI	0x540
    167 
    168 #define IS_INTEVT_SCI0(x) ((x == INTEVT_SCI0_ERI) || (x == INTEVT_SCI0_RXI) \
    169 			|| (x == INTEVT_SCI0_TXI) || (x == INTEVT_SCI0_TEI))
    170 
    171 #define	INTEVT_PRI	0x4a0	/* Periodic interrupt generated by RTC */
    172 
    173 #if defined(SH4)
    174 #define	INTEVT_SCIF	0x700
    175 #endif
    176 
    177 #endif /* !_SH3_INTR_H_ */
    178