locore.h revision 1.1
1 /* $NetBSD: locore.h,v 1.1 2002/02/24 18:19:42 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* XXX XXX XXX */ 37 #define SH3_BBRA 0xffffffb8 38 #define SH4_BBRA 0xff200008 39 #define SH3_EXPEVT 0xffffffd4 40 #define SH3_INTEVT 0xffffffd8 41 #define SH4_EXPEVT 0xff000024 42 #define SH4_INTEVT 0xff000028 43 /* XXX XXX XXX */ 44 45 #if defined(SH3) && defined(SH4) 46 #define MOV(x, r) mov.l _L./**/x, r; mov.l @r, r 47 #define REG_SYMBOL(x) _L./**/x: .long _C_LABEL(__sh_/**/x) 48 #define FUNC_SYMBOL(x) _L./**/x: .long _C_LABEL(__sh_/**/x) 49 #elif defined(SH3) 50 #define MOV(x, r) mov.l _L./**/x, r 51 #define REG_SYMBOL(x) _L./**/x: .long SH3_/**/x 52 #define FUNC_SYMBOL(x) _L./**/x: .long _C_LABEL(sh3_/**/x) 53 #elif defined(SH4) 54 #define MOV(x, r) mov.l _L./**/x, r 55 #define REG_SYMBOL(x) _L./**/x: .long SH4_/**/x 56 #define FUNC_SYMBOL(x) _L./**/x: .long _C_LABEL(sh4_/**/x) 57 #endif 58 59 /* 60 * BANK1 r7 contains kernel stack top address. 61 */ 62 /* 63 * EXCEPTION_ENTRY: 64 * + setup stack pointer 65 * + save all register to stack. (struct trapframe) 66 * + change bank from 1 to 0 67 * + set BANK0 (r4, r5) = (ssr, spc) 68 */ 69 #define EXCEPTION_ENTRY ;\ 70 /* Check kernel/user mode. */ ;\ 71 mov #0x40, r3 ;\ 72 swap.b r3, r3 ;\ 73 stc ssr, r1 ;\ 74 swap.w r3, r3 /* r3 = 0x40000000 */ ;\ 75 mov r1, r0 /* r1 = r0 = SSR */ ;\ 76 and r3, r0 ;\ 77 tst r0, r0 /* if (SSR.MD == 0) T = 1 */ ;\ 78 bf/s 1f /* T==0 ...Exception from kernel mode */;\ 79 mov r15, r0 /* r0 = old stack */ ;\ 80 /* Exception from user mode */ ;\ 81 mov r7, r15 /* change to kernel stack */ ;\ 82 1: ;\ 83 /* Save registers */ ;\ 84 mov.l r0, @-r15 /* tf_r15 */ ;\ 85 stc.l r0_bank,@-r15 /* tf_r0 */ ;\ 86 stc.l r1_bank,@-r15 /* tf_r1 */ ;\ 87 stc.l r2_bank,@-r15 /* tf_r2 */ ;\ 88 stc.l r3_bank,@-r15 /* tf_r3 */ ;\ 89 stc.l r4_bank,@-r15 /* tf_r4 */ ;\ 90 stc.l r5_bank,@-r15 /* tf_r5 */ ;\ 91 stc.l r6_bank,@-r15 /* tf_r6 */ ;\ 92 stc.l r7_bank,@-r15 /* tf_r7 */ ;\ 93 mov.l r8, @-r15 /* tf_r8 */ ;\ 94 mov.l r9, @-r15 /* tf_r9 */ ;\ 95 mov.l r10, @-r15 /* tf_r10 */ ;\ 96 mov.l r11, @-r15 /* tf_r11 */ ;\ 97 mov.l r12, @-r15 /* tf_r12 */ ;\ 98 mov.l r13, @-r15 /* tf_r13 */ ;\ 99 mov.l r14, @-r15 /* tf_r14 */ ;\ 100 sts.l pr, @-r15 /* tf_pr */ ;\ 101 sts.l mach, @-r15 /* tf_mach*/ ;\ 102 sts.l macl, @-r15 /* tf_macl*/ ;\ 103 mov.l r1, @-r15 /* tf_ssr */ ;\ 104 stc.l spc, @-r15 /* tf_spc */ ;\ 105 add #-8, r15 /* skip tf_ubc, tf_trapno */ ;\ 106 /* Change register bank to 0 */ ;\ 107 shlr r3 /* r3 = 0x20000000 */ ;\ 108 stc sr, r0 /* r0 = SR */ ;\ 109 not r3, r3 ;\ 110 and r0, r3 ;\ 111 ldc r3, sr /* SR.RB = 0 */ ;\ 112 /* Set up argument. r4 = ssr, r5 = spc */ ;\ 113 stc r1_bank,r4 ;\ 114 stc spc, r5 115 116 /* 117 * EXCEPTION_RETURN: 118 * + block exception 119 * + restore all register from stack. 120 * + rte. 121 */ 122 #define EXCEPTION_RETURN ;\ 123 mov #0x10, r0 ;\ 124 swap.b r0, r0 ;\ 125 swap.w r0, r0 /* r0 = 0x10000000 */ ;\ 126 stc sr, r1 ;\ 127 or r0, r1 ;\ 128 ldc r1, sr /* SR.BL = 1 */ ;\ 129 add #8, r15 /* skip tf_trapno, tf_ubc */ ;\ 130 mov.l @r15+, r0 /* tf_spc */ ;\ 131 ldc r0, spc ;\ 132 mov.l @r15+, r0 /* tf_ssr */ ;\ 133 ldc r0, ssr ;\ 134 lds.l @r15+, macl /* tf_macl*/ ;\ 135 lds.l @r15+, mach /* tf_mach*/ ;\ 136 lds.l @r15+, pr /* tf_pr */ ;\ 137 mov.l @r15+, r14 /* tf_r14 */ ;\ 138 mov.l @r15+, r13 /* tf_r13 */ ;\ 139 mov.l @r15+, r12 /* tf_r12 */ ;\ 140 mov.l @r15+, r11 /* tf_r11 */ ;\ 141 mov.l @r15+, r10 /* tf_r10 */ ;\ 142 mov.l @r15+, r9 /* tf_r9 */ ;\ 143 mov.l @r15+, r8 /* tf_r8 */ ;\ 144 mov.l @r15+, r7 /* tf_r7 */ ;\ 145 mov.l @r15+, r6 /* tf_r6 */ ;\ 146 mov.l @r15+, r5 /* tf_r5 */ ;\ 147 mov.l @r15+, r4 /* tf_r4 */ ;\ 148 mov.l @r15+, r3 /* tf_r3 */ ;\ 149 mov.l @r15+, r2 /* tf_r2 */ ;\ 150 mov.l @r15+, r1 /* tf_r1 */ ;\ 151 mov.l @r15+, r0 /* tf_r0 */ ;\ 152 mov.l @r15, r15 /* tf_r15 */ ;\ 153 rte ;\ 154 nop 155 156 157 /* 158 * Macros to disable and enable exceptions (including interrupts). 159 * This modifies SR.BL 160 */ 161 #define __EXCEPTION_BLOCK_r0_r1 ;\ 162 mov #0x10, r0 ;\ 163 swap.b r0, r0 ;\ 164 swap.w r0, r0 /* r0 = 0x10000000 */ ;\ 165 stc sr, r1 ;\ 166 or r0, r1 ;\ 167 ldc r1, sr /* block exceptions */ 168 169 #define __EXCEPTION_UNBLOCK_r0_r1 ;\ 170 mov #0x10, r0 ;\ 171 swap.b r0, r0 ;\ 172 swap.w r0, r0 /* r0 = 0x10000000 */ ;\ 173 not r0, r0 ;\ 174 stc sr, r1 ;\ 175 and r0, r1 ;\ 176 ldc r1, sr /* unblock exceptions */ 177 178 /* 179 * Macros to disable and enable interrupts. 180 * This modifies SR.I[0-3] 181 */ 182 #define __INTR_MASK_r0_r1 ;\ 183 mov #0x78, r0 ;\ 184 shll r0 /* r0 = 0x000000f0 */ ;\ 185 stc sr, r1 ;\ 186 or r0, r1 ;\ 187 ldc r1, sr /* mask all interrupt */ 188 189 #define __INTR_UNMASK_r0_r1 ;\ 190 mov #0x78, r0 ;\ 191 shll r0 /* r0 = 0x000000f0 */ ;\ 192 not r0, r0 ;\ 193 stc sr, r1 ;\ 194 and r0, r1 ;\ 195 ldc r1, sr /* unmask all interrupt */ 196 197 198 #define RECURSEENTRY ;\ 199 mov r15, r0 ;\ 200 mov.l r0, @-r15 ;\ 201 mov.l r0, @-r15 ;\ 202 mov.l r1, @-r15 ;\ 203 mov.l r2, @-r15 ;\ 204 mov.l r3, @-r15 ;\ 205 mov.l r4, @-r15 ;\ 206 mov.l r5, @-r15 ;\ 207 mov.l r6, @-r15 ;\ 208 mov.l r7, @-r15 ;\ 209 mov.l r8, @-r15 ;\ 210 mov.l r9, @-r15 ;\ 211 mov.l r10, @-r15 ;\ 212 mov.l r11, @-r15 ;\ 213 mov.l r12, @-r15 ;\ 214 mov.l r13, @-r15 ;\ 215 mov.l r14, @-r15 ;\ 216 sts.l pr, @-r15 ;\ 217 sts.l mach, @-r15 ;\ 218 sts.l macl, @-r15 ;\ 219 stc.l ssr, @-r15 ;\ 220 stc.l spc, @-r15 ;\ 221 add #-8, r15 /* tf_ubc, tf_trapno */ 222
Indexes created Tue Sep 30 07:10:03 GMT 2025