locore.h revision 1.13
1 /* $NetBSD: locore.h,v 1.13 2007/09/25 01:55:07 uwe Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #ifdef _LOCORE 37 38 #if defined(SH3) && defined(SH4) 39 #define MOV(x, r) mov.l .L_/**/x, r; mov.l @r, r 40 #define REG_SYMBOL(x) .L_/**/x: .long _C_LABEL(__sh_/**/x) 41 #define FUNC_SYMBOL(x) .L_/**/x: .long _C_LABEL(__sh_/**/x) 42 #elif defined(SH3) 43 #define MOV(x, r) mov.l .L_/**/x, r 44 #define REG_SYMBOL(x) .L_/**/x: .long SH3_/**/x 45 #define FUNC_SYMBOL(x) .L_/**/x: .long _C_LABEL(sh3_/**/x) 46 #elif defined(SH4) 47 #define MOV(x, r) mov.l .L_/**/x, r 48 #define REG_SYMBOL(x) .L_/**/x: .long SH4_/**/x 49 #define FUNC_SYMBOL(x) .L_/**/x: .long _C_LABEL(sh4_/**/x) 50 #endif /* SH3 && SH4 */ 51 52 /* 53 * BANK1 r6 contains current trapframe pointer. 54 * BANK1 r7 contains bottom address of lwp's kernel stack. 55 */ 56 /* 57 * __EXCEPTION_ENTRY: 58 * + setup stack pointer 59 * + save all registers to trapframe. 60 * + setup kernel stack. 61 * + change bank from 1 to 0 62 * + set BANK0 (r4, r5, r6) = (ssr, spc, ssp) 63 */ 64 #define __EXCEPTION_ENTRY ;\ 65 /* Check kernel/user mode. */ ;\ 66 mov #0x40, r3 ;\ 67 swap.b r3, r3 ;\ 68 stc ssr, r2 ;\ 69 swap.w r3, r3 /* r3 = 0x40000000 */ ;\ 70 mov r2, r0 /* r2 = r0 = SSR */ ;\ 71 and r3, r0 ;\ 72 tst r0, r0 /* if (SSR.MD == 0) T = 1 */ ;\ 73 mov r14, r1 ;\ 74 mov r6, r14 /* frame pointer */ ;\ 75 bf/s 1f /* T==0 ...Exception from kernel mode */;\ 76 mov r15, r0 ;\ 77 /* Exception from user mode */ ;\ 78 mov r7, r15 /* change to kernel stack */ ;\ 79 1: ;\ 80 /* Save registers */ ;\ 81 mov.l r1, @-r14 /* tf_r14 */ ;\ 82 mov.l r0, @-r14 /* tf_r15 */ ;\ 83 stc.l r0_bank,@-r14 /* tf_r0 */ ;\ 84 stc.l r1_bank,@-r14 /* tf_r1 */ ;\ 85 stc.l r2_bank,@-r14 /* tf_r2 */ ;\ 86 stc.l r3_bank,@-r14 /* tf_r3 */ ;\ 87 stc.l r4_bank,@-r14 /* tf_r4 */ ;\ 88 stc.l r5_bank,@-r14 /* tf_r5 */ ;\ 89 stc.l r6_bank,@-r14 /* tf_r6 */ ;\ 90 stc.l r7_bank,@-r14 /* tf_r7 */ ;\ 91 mov.l r8, @-r14 /* tf_r8 */ ;\ 92 mov.l r9, @-r14 /* tf_r9 */ ;\ 93 mov.l r10, @-r14 /* tf_r10 */ ;\ 94 mov.l r11, @-r14 /* tf_r11 */ ;\ 95 mov.l r12, @-r14 /* tf_r12 */ ;\ 96 mov.l r13, @-r14 /* tf_r13 */ ;\ 97 sts.l pr, @-r14 /* tf_pr */ ;\ 98 sts.l mach, @-r14 /* tf_mach*/ ;\ 99 sts.l macl, @-r14 /* tf_macl*/ ;\ 100 mov.l r2, @-r14 /* tf_ssr */ ;\ 101 stc.l spc, @-r14 /* tf_spc */ ;\ 102 add #-8, r14 /* skip tf_ubc, tf_expevt */ ;\ 103 mov r14, r6 /* store frame pointer */ ;\ 104 /* Change register bank to 0 */ ;\ 105 shlr r3 /* r3 = 0x20000000 */ ;\ 106 stc sr, r1 /* r1 = SR */ ;\ 107 not r3, r3 ;\ 108 and r1, r3 ;\ 109 ldc r3, sr /* SR.RB = 0 */ ;\ 110 /* Set up arguments. r4 = ssr, r5 = spc */ ;\ 111 stc r2_bank,r4 ;\ 112 stc spc, r5 113 114 /* 115 * __EXCEPTION_RETURN: 116 * + block exceptions 117 * + restore all registers from stack. 118 * + rte. 119 */ 120 #define __EXCEPTION_RETURN ;\ 121 mov #0x10, r0 ;\ 122 swap.b r0, r0 ;\ 123 swap.w r0, r0 /* r0 = 0x10000000 */ ;\ 124 stc sr, r1 ;\ 125 or r0, r1 ;\ 126 ldc r1, sr /* SR.BL = 1 */ ;\ 127 stc r6_bank,r0 ;\ 128 mov r0, r14 ;\ 129 add #TF_SIZE, r0 ;\ 130 ldc r0, r6_bank /* roll up frame pointer */ ;\ 131 add #8, r14 /* skip tf_expevt, tf_ubc */ ;\ 132 mov.l @r14+, r0 /* tf_spc */ ;\ 133 ldc r0, spc ;\ 134 mov.l @r14+, r0 /* tf_ssr */ ;\ 135 ldc r0, ssr ;\ 136 lds.l @r14+, macl /* tf_macl*/ ;\ 137 lds.l @r14+, mach /* tf_mach*/ ;\ 138 lds.l @r14+, pr /* tf_pr */ ;\ 139 mov.l @r14+, r13 /* tf_r13 */ ;\ 140 mov.l @r14+, r12 /* tf_r12 */ ;\ 141 mov.l @r14+, r11 /* tf_r11 */ ;\ 142 mov.l @r14+, r10 /* tf_r10 */ ;\ 143 mov.l @r14+, r9 /* tf_r9 */ ;\ 144 mov.l @r14+, r8 /* tf_r8 */ ;\ 145 mov.l @r14+, r7 /* tf_r7 */ ;\ 146 mov.l @r14+, r6 /* tf_r6 */ ;\ 147 mov.l @r14+, r5 /* tf_r5 */ ;\ 148 mov.l @r14+, r4 /* tf_r4 */ ;\ 149 mov.l @r14+, r3 /* tf_r3 */ ;\ 150 mov.l @r14+, r2 /* tf_r2 */ ;\ 151 mov.l @r14+, r1 /* tf_r1 */ ;\ 152 mov.l @r14+, r0 /* tf_r0 */ ;\ 153 mov.l @r14+ r15 /* tf_r15 */ ;\ 154 mov.l @r14+, r14 /* tf_r14 */ ;\ 155 rte ;\ 156 nop 157 158 159 /* 160 * Macros to disable and enable exceptions (including interrupts). 161 * This modifies SR.BL 162 */ 163 164 #define __EXCEPTION_BLOCK(Rn, Rm) ;\ 165 mov #0x10, Rn ;\ 166 swap.b Rn, Rn ;\ 167 swap.w Rn, Rn /* Rn = 0x10000000 */ ;\ 168 stc sr, Rm ;\ 169 or Rn, Rm ;\ 170 ldc Rm, sr /* block exceptions */ 171 172 #define __EXCEPTION_UNBLOCK(Rn, Rm) ;\ 173 mov #0x10, Rn ;\ 174 swap.b Rn, Rn ;\ 175 swap.w Rn, Rn /* Rn = 0x10000000 */ ;\ 176 not Rn, Rn ;\ 177 stc sr, Rm ;\ 178 and Rn, Rm ;\ 179 ldc Rm, sr /* unblock exceptions */ 180 181 /* 182 * Macros to disable and enable interrupts. 183 * This modifies SR.I[0-3] 184 */ 185 #define __INTR_MASK(Rn, Rm) ;\ 186 mov #0x78, Rn ;\ 187 shll Rn /* Rn = 0x000000f0 */ ;\ 188 stc sr, Rm ;\ 189 or Rn, Rm ;\ 190 ldc Rm, sr /* mask all interrupts */ 191 192 #define __INTR_UNMASK(Rn, Rm) ;\ 193 mov #0x78, Rn ;\ 194 shll Rn /* Rn = 0x000000f0 */ ;\ 195 not Rn, Rn ;\ 196 stc sr, Rm ;\ 197 and Rn, Rm ;\ 198 ldc Rm, sr /* unmask all interrupts */ 199 200 #else /* !_LOCORE */ 201 202 void sh3_switch_setup(struct lwp *); 203 void sh4_switch_setup(struct lwp *); 204 void sh3_switch_resume(struct lwp *); 205 void sh4_switch_resume(struct lwp *); 206 extern void (*__sh_switch_resume)(struct lwp *); 207 208 #endif /* !_LOCORE */ 209
Indexes created Tue Sep 30 06:09:59 GMT 2025