locore.h revision 1.2
1 /* $NetBSD: locore.h,v 1.2 2002/02/28 01:53:43 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #if defined(SH3) && defined(SH4) 37 #define MOV(x, r) mov.l _L./**/x, r; mov.l @r, r 38 #define REG_SYMBOL(x) _L./**/x: .long _C_LABEL(__sh_/**/x) 39 #define FUNC_SYMBOL(x) _L./**/x: .long _C_LABEL(__sh_/**/x) 40 #elif defined(SH3) 41 #define MOV(x, r) mov.l _L./**/x, r 42 #define REG_SYMBOL(x) _L./**/x: .long SH3_/**/x 43 #define FUNC_SYMBOL(x) _L./**/x: .long _C_LABEL(sh3_/**/x) 44 #elif defined(SH4) 45 #define MOV(x, r) mov.l _L./**/x, r 46 #define REG_SYMBOL(x) _L./**/x: .long SH4_/**/x 47 #define FUNC_SYMBOL(x) _L./**/x: .long _C_LABEL(sh4_/**/x) 48 #endif 49 50 /* 51 * BANK1 r7 contains kernel stack top address. 52 */ 53 /* 54 * EXCEPTION_ENTRY: 55 * + setup stack pointer 56 * + save all register to stack. (struct trapframe) 57 * + change bank from 1 to 0 58 * + set BANK0 (r4, r5) = (ssr, spc) 59 */ 60 #define EXCEPTION_ENTRY ;\ 61 /* Check kernel/user mode. */ ;\ 62 mov #0x40, r3 ;\ 63 swap.b r3, r3 ;\ 64 stc ssr, r1 ;\ 65 swap.w r3, r3 /* r3 = 0x40000000 */ ;\ 66 mov r1, r0 /* r1 = r0 = SSR */ ;\ 67 and r3, r0 ;\ 68 tst r0, r0 /* if (SSR.MD == 0) T = 1 */ ;\ 69 bf/s 1f /* T==0 ...Exception from kernel mode */;\ 70 mov r15, r0 /* r0 = old stack */ ;\ 71 /* Exception from user mode */ ;\ 72 mov r7, r15 /* change to kernel stack */ ;\ 73 1: ;\ 74 /* Save registers */ ;\ 75 mov.l r0, @-r15 /* tf_r15 */ ;\ 76 stc.l r0_bank,@-r15 /* tf_r0 */ ;\ 77 stc.l r1_bank,@-r15 /* tf_r1 */ ;\ 78 stc.l r2_bank,@-r15 /* tf_r2 */ ;\ 79 stc.l r3_bank,@-r15 /* tf_r3 */ ;\ 80 stc.l r4_bank,@-r15 /* tf_r4 */ ;\ 81 stc.l r5_bank,@-r15 /* tf_r5 */ ;\ 82 stc.l r6_bank,@-r15 /* tf_r6 */ ;\ 83 stc.l r7_bank,@-r15 /* tf_r7 */ ;\ 84 mov.l r8, @-r15 /* tf_r8 */ ;\ 85 mov.l r9, @-r15 /* tf_r9 */ ;\ 86 mov.l r10, @-r15 /* tf_r10 */ ;\ 87 mov.l r11, @-r15 /* tf_r11 */ ;\ 88 mov.l r12, @-r15 /* tf_r12 */ ;\ 89 mov.l r13, @-r15 /* tf_r13 */ ;\ 90 mov.l r14, @-r15 /* tf_r14 */ ;\ 91 sts.l pr, @-r15 /* tf_pr */ ;\ 92 sts.l mach, @-r15 /* tf_mach*/ ;\ 93 sts.l macl, @-r15 /* tf_macl*/ ;\ 94 mov.l r1, @-r15 /* tf_ssr */ ;\ 95 stc.l spc, @-r15 /* tf_spc */ ;\ 96 add #-8, r15 /* skip tf_ubc, tf_trapno */ ;\ 97 /* Change register bank to 0 */ ;\ 98 shlr r3 /* r3 = 0x20000000 */ ;\ 99 stc sr, r0 /* r0 = SR */ ;\ 100 not r3, r3 ;\ 101 and r0, r3 ;\ 102 ldc r3, sr /* SR.RB = 0 */ ;\ 103 /* Set up argument. r4 = ssr, r5 = spc */ ;\ 104 stc r1_bank,r4 ;\ 105 stc spc, r5 106 107 /* 108 * EXCEPTION_RETURN: 109 * + block exception 110 * + restore all register from stack. 111 * + rte. 112 */ 113 #define EXCEPTION_RETURN ;\ 114 mov #0x10, r0 ;\ 115 swap.b r0, r0 ;\ 116 swap.w r0, r0 /* r0 = 0x10000000 */ ;\ 117 stc sr, r1 ;\ 118 or r0, r1 ;\ 119 ldc r1, sr /* SR.BL = 1 */ ;\ 120 add #8, r15 /* skip tf_trapno, tf_ubc */ ;\ 121 mov.l @r15+, r0 /* tf_spc */ ;\ 122 ldc r0, spc ;\ 123 mov.l @r15+, r0 /* tf_ssr */ ;\ 124 ldc r0, ssr ;\ 125 lds.l @r15+, macl /* tf_macl*/ ;\ 126 lds.l @r15+, mach /* tf_mach*/ ;\ 127 lds.l @r15+, pr /* tf_pr */ ;\ 128 mov.l @r15+, r14 /* tf_r14 */ ;\ 129 mov.l @r15+, r13 /* tf_r13 */ ;\ 130 mov.l @r15+, r12 /* tf_r12 */ ;\ 131 mov.l @r15+, r11 /* tf_r11 */ ;\ 132 mov.l @r15+, r10 /* tf_r10 */ ;\ 133 mov.l @r15+, r9 /* tf_r9 */ ;\ 134 mov.l @r15+, r8 /* tf_r8 */ ;\ 135 mov.l @r15+, r7 /* tf_r7 */ ;\ 136 mov.l @r15+, r6 /* tf_r6 */ ;\ 137 mov.l @r15+, r5 /* tf_r5 */ ;\ 138 mov.l @r15+, r4 /* tf_r4 */ ;\ 139 mov.l @r15+, r3 /* tf_r3 */ ;\ 140 mov.l @r15+, r2 /* tf_r2 */ ;\ 141 mov.l @r15+, r1 /* tf_r1 */ ;\ 142 mov.l @r15+, r0 /* tf_r0 */ ;\ 143 mov.l @r15, r15 /* tf_r15 */ ;\ 144 rte ;\ 145 nop 146 147 148 /* 149 * Macros to disable and enable exceptions (including interrupts). 150 * This modifies SR.BL 151 */ 152 #define __0x10 #0x10 153 #define __0x78 #0x78 154 155 #define __EXCEPTION_BLOCK(Rn, Rm) ;\ 156 mov __0x10, Rn ;\ 157 swap.b Rn, Rn ;\ 158 swap.w Rn, Rn /* Rn = 0x10000000 */ ;\ 159 stc sr, Rm ;\ 160 or Rn, Rm ;\ 161 ldc Rm, sr /* block exceptions */ 162 163 #define __EXCEPTION_UNBLOCK(Rn, Rm) ;\ 164 mov __0x10, Rn ;\ 165 swap.b Rn, Rn ;\ 166 swap.w Rn, Rn /* Rn = 0x10000000 */ ;\ 167 not Rn, Rn ;\ 168 stc sr, Rm ;\ 169 and Rn, Rm ;\ 170 ldc Rm, sr /* unblock exceptions */ 171 172 /* 173 * Macros to disable and enable interrupts. 174 * This modifies SR.I[0-3] 175 */ 176 #define __INTR_MASK(Rn, Rm) ;\ 177 mov __0x78, Rn ;\ 178 shll Rn /* Rn = 0x000000f0 */ ;\ 179 stc sr, Rm ;\ 180 or Rn, Rm ;\ 181 ldc Rm, sr /* mask all interrupt */ 182 183 #define __INTR_UNMASK(Rn, Rm) ;\ 184 mov __0x78, Rn ;\ 185 shll Rn /* Rn = 0x000000f0 */ ;\ 186 not Rn, Rn ;\ 187 stc sr, Rm ;\ 188 and Rn, Rm ;\ 189 ldc Rm, sr /* unmask all interrupt */ 190 191 #define RECURSEENTRY ;\ 192 mov r15, r0 ;\ 193 mov.l r0, @-r15 ;\ 194 mov.l r0, @-r15 ;\ 195 mov.l r1, @-r15 ;\ 196 mov.l r2, @-r15 ;\ 197 mov.l r3, @-r15 ;\ 198 mov.l r4, @-r15 ;\ 199 mov.l r5, @-r15 ;\ 200 mov.l r6, @-r15 ;\ 201 mov.l r7, @-r15 ;\ 202 mov.l r8, @-r15 ;\ 203 mov.l r9, @-r15 ;\ 204 mov.l r10, @-r15 ;\ 205 mov.l r11, @-r15 ;\ 206 mov.l r12, @-r15 ;\ 207 mov.l r13, @-r15 ;\ 208 mov.l r14, @-r15 ;\ 209 sts.l pr, @-r15 ;\ 210 sts.l mach, @-r15 ;\ 211 sts.l macl, @-r15 ;\ 212 stc.l ssr, @-r15 ;\ 213 stc.l spc, @-r15 ;\ 214 add #-8, r15 /* tf_ubc, tf_trapno */ 215
Indexes created Tue Sep 30 07:10:03 GMT 2025