mmu.h revision 1.1
1 /* $NetBSD: mmu.h,v 1.1 2002/02/17 20:55:50 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _SH3_MMU_H_ 40 #define _SH3_MMU_H_ 41 42 /* 43 * Initialize routines. 44 * sh_mmu_init Assign function vector, and register addresses. 45 * Don't access hardware. 46 * Call as possible as first. 47 * sh_mmu_start Reset TLB entry, set default ASID, and start to 48 * translate address. 49 * Call after exception vector was installed. 50 * 51 * TLB access ops. 52 * sh_tlb_invalidate_addr invalidate TLB entris for given 53 * virtual addr with ASID. 54 * sh_tlb_invalidate_asid invalidate TLB entries for given ASID. 55 * sh_tlb_invalidate_all invalidate all non-wired TLB entries. //sana 56 * sh_tlb_reset invalidate all TLB entries. 57 * sh_tlb_set_asid set ASID to PTEH 58 * 59 * Page table acess ops. (for current NetBSD/sh3 implementation) 60 * 61 */ 62 63 extern void sh_mmu_init(void); 64 65 extern void (*__sh_mmu_start)(void); 66 extern void sh3_mmu_start(void); 67 extern void sh4_mmu_start(void); 68 #define sh_mmu_start() (*__sh_mmu_start)() 69 70 extern void sh_tlb_set_asid(int); 71 72 extern void (*__sh_tlb_invalidate_addr)(int, vaddr_t); 73 extern void (*__sh_tlb_invalidate_asid)(int); 74 extern void (*__sh_tlb_invalidate_all)(void); 75 extern void (*__sh_tlb_reset)(void); 76 extern void sh3_tlb_invalidate_addr(int, vaddr_t); 77 extern void sh3_tlb_invalidate_asid(int); 78 extern void sh3_tlb_invalidate_all(void); 79 extern void sh3_tlb_reset(void); 80 extern void sh4_tlb_invalidate_addr(int, vaddr_t); 81 extern void sh4_tlb_invalidate_asid(int); 82 extern void sh4_tlb_invalidate_all(void); 83 extern void sh4_tlb_reset(void); 84 #if defined(SH3) && defined(SH4) 85 #define sh_tlb_invalidate_addr(a, va) (*__sh_tlb_invalidate_addr)(a, va) 86 #define sh_tlb_invalidate_asid(a) (*__sh_tlb_invalidate_asid)(a) 87 #define sh_tlb_invalidate_all() (*__sh_tlb_invalidate_all)() 88 #define sh_tlb_reset() (*__sh_tlb_reset)() 89 #elif defined(SH3) 90 #define sh_tlb_invalidate_addr(a, va) sh3_tlb_invalidate_addr(a, va) 91 #define sh_tlb_invalidate_asid(a) sh3_tlb_invalidate_asid(a) 92 #define sh_tlb_invalidate_all() sh3_tlb_invalidate_all() 93 #define sh_tlb_reset() sh3_tlb_reset() 94 #elif defined(SH4) 95 #define sh_tlb_invalidate_addr(a, va) sh4_tlb_invalidate_addr(a, va) 96 #define sh_tlb_invalidate_asid(a) sh4_tlb_invalidate_asid(a) 97 #define sh_tlb_invalidate_all() sh4_tlb_invalidate_all() 98 #define sh_tlb_reset() sh4_tlb_reset() 99 #endif 100 101 /* 102 * MMU and page table entry access ops. 103 */ 104 #if defined(SH3) && defined(SH4) 105 extern u_int32_t __sh_PTEH; 106 extern u_int32_t __sh_TTB; 107 extern u_int32_t __sh_TEA; 108 extern u_int32_t __sh_TRA; 109 extern u_int32_t __sh_EXPEVT; 110 extern u_int32_t __sh_INTEVT; 111 #define SH_PTEH (*(__volatile__ u_int32_t *)__sh_PTEH) 112 #define SH_TTB (*(__volatile__ u_int32_t *)__sh_TTB) 113 #define SH_TEA (*(__volatile__ u_int32_t *)__sh_TEA) 114 #define SH_TRA (*(__volatile__ u_int32_t *)__sh_TRA) 115 #define SH_EXPEVT (*(__volatile__ u_int32_t *)__sh_EXPEVT) 116 #define SH_INTEVT (*(__volatile__ u_int32_t *)__sh_INTEVT) 117 #elif defined(SH3) 118 #define SH_PTEH (*(__volatile__ u_int32_t *)SH3_PTEH) 119 #define SH_TTB (*(__volatile__ u_int32_t *)SH3_TTB) 120 #define SH_TEA (*(__volatile__ u_int32_t *)SH3_TEA) 121 #define SH_TRA (*(__volatile__ u_int32_t *)0xffffffd0) 122 #define SH_EXPEVT (*(__volatile__ u_int32_t *)0xffffffd4) 123 #define SH_INTEVT (*(__volatile__ u_int32_t *)0xffffffd8) 124 #elif defined(SH4) 125 #define SH_PTEH (*(__volatile__ u_int32_t *)SH4_PTEH) 126 #define SH_TTB (*(__volatile__ u_int32_t *)SH4_TTB) 127 #define SH_TEA (*(__volatile__ u_int32_t *)SH4_TEA) 128 #define SH_TRA (*(__volatile__ u_int32_t *)0xff000020) 129 #define SH_EXPEVT (*(__volatile__ u_int32_t *)0xff000024) 130 #define SH_INTEVT (*(__volatile__ u_int32_t *)0xff000028) 131 #endif 132 133 extern void (*__sh_mmu_pte_setup)(vaddr_t, u_int32_t); 134 extern void sh3_mmu_pte_setup(vaddr_t, u_int32_t); 135 extern void sh4_mmu_pte_setup(vaddr_t, u_int32_t); 136 #if defined(SH3) && defined(SH4) 137 #define SH_MMU_PTE_SETUP(v, pte) (*__sh_mmu_pte_setup)((v), (pte)) 138 #elif defined(SH3) 139 #define SH_MMU_PTE_SETUP(v, pte) sh3_mmu_pte_setup((v), (pte)) 140 #elif defined(SH4) 141 #define SH_MMU_PTE_SETUP(v, pte) sh4_mmu_pte_setup((v), (pte)) 142 #endif 143 144 /* 145 * SH3 port access pte from P1, SH4 port access it from P2. 146 */ 147 extern u_int32_t (*__sh_mmu_pd_area)(u_int32_t); 148 extern u_int32_t __sh3_mmu_pd_area(u_int32_t); 149 extern u_int32_t __sh4_mmu_pd_area(u_int32_t); 150 #if defined(SH3) && defined(SH4) 151 #define SH_MMU_PD_AREA(x) __sh_mmu_pd_area(x) 152 #elif defined(SH3) 153 #define SH_MMU_PD_AREA(x) (x) 154 #elif defined(SH4) 155 #define SH_MMU_PD_AREA(x) SH3_P1SEG_TO_P2SEG(x) 156 #endif 157 158 /* 159 * TTB stores pte entry start address. 160 */ 161 extern u_int32_t (*__sh_mmu_ttb_read)(void); 162 extern void (*__sh_mmu_ttb_write)(u_int32_t); 163 extern u_int32_t sh3_mmu_ttb_read(void); 164 extern void sh3_mmu_ttb_write(u_int32_t); 165 extern u_int32_t sh4_mmu_ttb_read(void); 166 extern void sh4_mmu_ttb_write(u_int32_t); 167 #if defined(SH3) && defined(SH4) 168 #define SH_MMU_TTB_READ() (*__sh_mmu_ttb_read)() 169 #define SH_MMU_TTB_WRITE(x) (*__sh_mmu_ttb_write)(x) 170 #elif defined(SH3) 171 #define SH_MMU_TTB_READ() sh3_mmu_ttb_read() 172 #define SH_MMU_TTB_WRITE(x) sh3_mmu_ttb_write(x) 173 #elif defined(SH4) 174 #define SH_MMU_TTB_READ() sh4_mmu_ttb_read() 175 #define SH_MMU_TTB_WRITE(x) sh4_mmu_ttb_write(x) 176 #endif 177 178 /* 179 * some macros for pte access. 180 */ 181 #define SH_MMU_PD_TOP() ((u_long *)SH_MMU_PD_AREA(SH_MMU_TTB_READ())) 182 #define SH_MMU_PDE(pd, i) ((u_long *)SH_MMU_PD_AREA((pd)[(i)])) 183 184 #include <sh3/mmu_sh3.h> 185 #include <sh3/mmu_sh4.h> 186 #endif /* !_SH3_MMU_H_ */ 187
Indexes created Wed Oct 22 13:09:56 GMT 2025