mmu.h revision 1.3.2.1
1 /* $NetBSD: mmu.h,v 1.3.2.1 2002/02/28 04:11:38 nathanw Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _SH3_MMU_H_ 40 #define _SH3_MMU_H_ 41 42 /* 43 * Initialize routines. 44 * sh_mmu_init Assign function vector, and register addresses. 45 * Don't access hardware. 46 * Call as possible as first. 47 * sh_mmu_start Reset TLB entry, set default ASID, and start to 48 * translate address. 49 * Call after exception vector was installed. 50 * 51 * TLB access ops. 52 * sh_tlb_invalidate_addr invalidate TLB entris for given 53 * virtual addr with ASID. 54 * sh_tlb_invalidate_asid invalidate TLB entries for given ASID. 55 * sh_tlb_invalidate_all invalidate all non-wired TLB entries. //sana 56 * sh_tlb_reset invalidate all TLB entries. 57 * sh_tlb_set_asid set ASID to PTEH 58 * 59 * Page table acess ops. (for current NetBSD/sh3 implementation) 60 * 61 */ 62 63 extern void sh_mmu_init(void); 64 extern void sh_mmu_information(void); 65 66 extern void (*__sh_mmu_start)(void); 67 extern void sh3_mmu_start(void); 68 extern void sh4_mmu_start(void); 69 #define sh_mmu_start() (*__sh_mmu_start)() 70 71 extern void sh_tlb_set_asid(int); 72 73 extern void (*__sh_tlb_invalidate_addr)(int, vaddr_t); 74 extern void (*__sh_tlb_invalidate_asid)(int); 75 extern void (*__sh_tlb_invalidate_all)(void); 76 extern void (*__sh_tlb_reset)(void); 77 extern void sh3_tlb_invalidate_addr(int, vaddr_t); 78 extern void sh3_tlb_invalidate_asid(int); 79 extern void sh3_tlb_invalidate_all(void); 80 extern void sh3_tlb_reset(void); 81 extern void sh4_tlb_invalidate_addr(int, vaddr_t); 82 extern void sh4_tlb_invalidate_asid(int); 83 extern void sh4_tlb_invalidate_all(void); 84 extern void sh4_tlb_reset(void); 85 #if defined(SH3) && defined(SH4) 86 #define sh_tlb_invalidate_addr(a, va) (*__sh_tlb_invalidate_addr)(a, va) 87 #define sh_tlb_invalidate_asid(a) (*__sh_tlb_invalidate_asid)(a) 88 #define sh_tlb_invalidate_all() (*__sh_tlb_invalidate_all)() 89 #define sh_tlb_reset() (*__sh_tlb_reset)() 90 #elif defined(SH3) 91 #define sh_tlb_invalidate_addr(a, va) sh3_tlb_invalidate_addr(a, va) 92 #define sh_tlb_invalidate_asid(a) sh3_tlb_invalidate_asid(a) 93 #define sh_tlb_invalidate_all() sh3_tlb_invalidate_all() 94 #define sh_tlb_reset() sh3_tlb_reset() 95 #elif defined(SH4) 96 #define sh_tlb_invalidate_addr(a, va) sh4_tlb_invalidate_addr(a, va) 97 #define sh_tlb_invalidate_asid(a) sh4_tlb_invalidate_asid(a) 98 #define sh_tlb_invalidate_all() sh4_tlb_invalidate_all() 99 #define sh_tlb_reset() sh4_tlb_reset() 100 #endif 101 102 /* 103 * MMU and page table entry access ops. 104 */ 105 #if defined(SH3) && defined(SH4) 106 extern u_int32_t __sh_PTEH; 107 extern u_int32_t __sh_TTB; 108 extern u_int32_t __sh_TEA; 109 extern u_int32_t __sh_TRA; 110 extern u_int32_t __sh_EXPEVT; 111 extern u_int32_t __sh_INTEVT; 112 #define SH_PTEH (*(__volatile__ u_int32_t *)__sh_PTEH) 113 #define SH_TTB (*(__volatile__ u_int32_t *)__sh_TTB) 114 #define SH_TEA (*(__volatile__ u_int32_t *)__sh_TEA) 115 #define SH_TRA (*(__volatile__ u_int32_t *)__sh_TRA) 116 #define SH_EXPEVT (*(__volatile__ u_int32_t *)__sh_EXPEVT) 117 #define SH_INTEVT (*(__volatile__ u_int32_t *)__sh_INTEVT) 118 #elif defined(SH3) 119 #define SH_PTEH (*(__volatile__ u_int32_t *)SH3_PTEH) 120 #define SH_TTB (*(__volatile__ u_int32_t *)SH3_TTB) 121 #define SH_TEA (*(__volatile__ u_int32_t *)SH3_TEA) 122 #define SH_TRA (*(__volatile__ u_int32_t *)0xffffffd0) 123 #define SH_EXPEVT (*(__volatile__ u_int32_t *)0xffffffd4) 124 #define SH_INTEVT (*(__volatile__ u_int32_t *)0xffffffd8) 125 #elif defined(SH4) 126 #define SH_PTEH (*(__volatile__ u_int32_t *)SH4_PTEH) 127 #define SH_TTB (*(__volatile__ u_int32_t *)SH4_TTB) 128 #define SH_TEA (*(__volatile__ u_int32_t *)SH4_TEA) 129 #define SH_TRA (*(__volatile__ u_int32_t *)0xff000020) 130 #define SH_EXPEVT (*(__volatile__ u_int32_t *)0xff000024) 131 #define SH_INTEVT (*(__volatile__ u_int32_t *)0xff000028) 132 #endif 133 134 extern void (*__sh_mmu_pte_setup)(vaddr_t, u_int32_t); 135 extern void sh3_mmu_pte_setup(vaddr_t, u_int32_t); 136 extern void sh4_mmu_pte_setup(vaddr_t, u_int32_t); 137 #if defined(SH3) && defined(SH4) 138 #define SH_MMU_PTE_SETUP(v, pte) (*__sh_mmu_pte_setup)((v), (pte)) 139 #elif defined(SH3) 140 #define SH_MMU_PTE_SETUP(v, pte) sh3_mmu_pte_setup((v), (pte)) 141 #elif defined(SH4) 142 #define SH_MMU_PTE_SETUP(v, pte) sh4_mmu_pte_setup((v), (pte)) 143 #endif 144 145 /* 146 * SH3 port access pte from P1, SH4 port access it from P2. 147 */ 148 extern u_int32_t (*__sh_mmu_pd_area)(u_int32_t); 149 extern u_int32_t __sh3_mmu_pd_area(u_int32_t); 150 extern u_int32_t __sh4_mmu_pd_area(u_int32_t); 151 #if defined(SH3) && defined(SH4) 152 #define SH_MMU_PD_AREA(x) __sh_mmu_pd_area(x) 153 #elif defined(SH3) 154 #define SH_MMU_PD_AREA(x) (x) 155 #elif defined(SH4) 156 #define SH_MMU_PD_AREA(x) SH3_P1SEG_TO_P2SEG(x) 157 #endif 158 159 /* 160 * TTB stores pte entry start address. 161 */ 162 extern u_int32_t (*__sh_mmu_ttb_read)(void); 163 extern void (*__sh_mmu_ttb_write)(u_int32_t); 164 extern u_int32_t sh3_mmu_ttb_read(void); 165 extern void sh3_mmu_ttb_write(u_int32_t); 166 extern u_int32_t sh4_mmu_ttb_read(void); 167 extern void sh4_mmu_ttb_write(u_int32_t); 168 #if defined(SH3) && defined(SH4) 169 #define SH_MMU_TTB_READ() (*__sh_mmu_ttb_read)() 170 #define SH_MMU_TTB_WRITE(x) (*__sh_mmu_ttb_write)(x) 171 #elif defined(SH3) 172 #define SH_MMU_TTB_READ() sh3_mmu_ttb_read() 173 #define SH_MMU_TTB_WRITE(x) sh3_mmu_ttb_write(x) 174 #elif defined(SH4) 175 #define SH_MMU_TTB_READ() sh4_mmu_ttb_read() 176 #define SH_MMU_TTB_WRITE(x) sh4_mmu_ttb_write(x) 177 #endif 178 179 /* 180 * some macros for pte access. 181 */ 182 #define SH_MMU_PD_TOP() ((u_long *)SH_MMU_PD_AREA(SH_MMU_TTB_READ())) 183 #define SH_MMU_PDE(pd, i) ((u_long *)SH_MMU_PD_AREA((pd)[(i)])) 184 185 #include <sh3/mmu_sh3.h> 186 #include <sh3/mmu_sh4.h> 187 #endif /* !_SH3_MMU_H_ */ 188
Indexes created Wed Oct 22 06:10:02 GMT 2025