mmu_sh4.h revision 1.1
1 /* $NetBSD: mmu_sh4.h,v 1.1 2002/02/17 20:55:51 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _SH3_MMU_SH4_H_ 40 #define _SH3_MMU_SH4_H_ 41 42 /* ITLB 4-entry full-associative UTLB 64-entry full-associative */ 43 #define SH4_PTEH 0xff000000 44 #define SH4_PTEH_VPN_MASK 0xfffffc00 45 #define SH4_PTEH_ASID_MASK 0x0000000f 46 #define SH4_PTEL 0xff000004 47 #define SH4_PTEL_WT 0x00000001 48 #define SH4_PTEL_SH 0x00000002 49 #define SH4_PTEL_D 0x00000004 50 #define SH4_PTEL_C 0x00000008 51 #define SH4_PTEL_PR_SHIFT 5 52 #define SH4_PTEL_PR_MASK 0x00000060 /* [5:6] */ 53 #define SH4_PTEL_SZ_MASK 0x00000090 /* [4][7] */ 54 #define SH4_PTEL_SZ_1K 0x00000000 55 #define SH4_PTEL_SZ_4K 0x00000010 56 #define SH4_PTEL_SZ_64K 0x00000080 57 #define SH4_PTEL_SZ_1M 0x00000090 58 #define SH4_PTEL_V 0x00000100 59 #define SH4_PTEL_HWBITS 0x1ffff1ff /* [28:12]PFN [8:0]attr. */ 60 61 #define SH4_PTEA 0xff000034 62 #define SH4_PTEA_SA_MASK 0x00000007 63 #define SH4_PTEA_SA_TC 0x00000008 64 #define SH4_TTB 0xff000008 65 #define SH4_TEA 0xff00000c 66 #define SH4_MMUCR 0xff000010 67 #define SH4_MMUCR_AT 0x00000001 68 #define SH4_MMUCR_TI 0x00000004 69 #define SH4_MMUCR_SV 0x00000100 70 #define SH4_MMUCR_SQMD 0x00000200 71 #define SH4_MMUCR_URC_SHIFT 10 72 #define SH4_MMUCR_URC_MASK 0x0000fc00 /* [10:15] */ 73 #define SH4_MMUCR_URB_SHIFT 18 74 #define SH4_MMUCR_URB_MASK 0x00fc0000 /* [18:23] */ 75 #define SH4_MMUCR_LRUI_SHIFT 26 76 #define SH4_MMUCR_LRUT_MASK 0xfc000000 /* [26:31] */ 77 78 #define SH4_MMUCR_MASK (SH4_MMUCR_LRUT_MASK | SH4_MMUCR_URB_MASK | \ 79 SH4_MMUCR_URC_MASK | SH4_MMUCR_SQMD | SH4_MMUCR_SV | SH4_MMUCR_AT) 80 /* 81 * memory-mapped TLB 82 * must be access from P2-area program. 83 * branch to the other area must be maed at least 8 instruction 84 * after access. 85 */ 86 #define SH4_ITLB_ENTRY 4 87 #define SH4_UTLB_ENTRY 64 88 89 /* ITLB */ 90 #define SH4_ITLB_AA 0xf2000000 91 /* address specification (common for address and data array(0,1)) */ 92 #define SH4_ITLB_E_SHIFT 8 93 #define SH4_ITLB_E_MASK 0x00000300 /* [9:8] */ 94 /* data specification */ 95 /* address-array */ 96 #define SH4_ITLB_AA_ASID_MASK 0x000000ff /* [7:0] */ 97 #define SH4_ITLB_AA_V 0x00000100 98 #define SH4_ITLB_AA_VPN_SHIFT 10 99 #define SH4_ITLB_AA_VPN_MASK 0xfffffc00 /* [31:10] */ 100 /* data-array 1 */ 101 #define SH4_ITLB_DA1 0xf3000000 102 #define SH4_ITLB_DA1_SH 0x00000002 103 #define SH4_ITLB_DA1_C 0x00000008 104 #define SH4_ITLB_DA1_SZ_MASK 0x00000090 /* [7][4] */ 105 #define SH4_ITLB_DA1_SZ_1K 0x00000000 106 #define SH4_ITLB_DA1_SZ_4K 0x00000010 107 #define SH4_ITLB_DA1_SZ_64K 0x00000080 108 #define SH4_ITLB_DA1_SZ_1M 0x00000090 109 #define SH4_ITLB_DA1_PR 0x00000040 110 #define SH4_ITLB_DA1_V 0x00000100 111 #define SH4_ITLB_DA1_PPN_SHIFT 11 112 #define SH4_ITLB_DA1_PPN_MASK 0x1ffffc00 /* [28:10] */ 113 /* data-array 2 */ 114 #define SH4_ITLB_DA2 0xf3800000 115 #define SH4_ITLB_DA2_SA_MASK 0x00000003 116 #define SH4_ITLB_DA2_TC 0x00000004 117 118 /* UTLB */ 119 #define SH4_UTLB_AA 0xf6000000 120 /* address specification (common for address and data array(0,1)) */ 121 #define SH4_UTLB_E_SHIFT 8 122 #define SH4_UTLB_E_MASK 0x00003f00 123 #define SH4_UTLB_A 0x00000080 124 /* data specification */ 125 /* address-array */ 126 #define SH4_UTLB_AA_VPN_MASK 0xfffffc00 /* [31:10] */ 127 #define SH4_UTLB_AA_D 0x00000200 128 #define SH4_UTLB_AA_V 0x00000100 129 #define SH4_UTLB_AA_ASID_MASK 0x000000ff /* [7:0] */ 130 /* data-array 1 */ 131 #define SH4_UTLB_DA1 0xf7000000 132 #define SH4_UTLB_DA1_WT 0x00000001 133 #define SH4_UTLB_DA1_SH 0x00000002 134 #define SH4_UTLB_DA1_D 0x00000004 135 #define SH4_UTLB_DA1_C 0x00000008 136 #define SH4_UTLB_DA1_SZ_MASK 0x00000090 /* [7][4] */ 137 #define SH4_UTLB_DA1_SZ_1K 0x00000000 138 #define SH4_UTLB_DA1_SZ_4K 0x00000010 139 #define SH4_UTLB_DA1_SZ_64K 0x00000080 140 #define SH4_UTLB_DA1_SZ_1M 0x00000090 141 #define SH4_UTLB_DA1_PR_SHIFT 5 142 #define SH4_UTLB_DA1_PR_MASK 0x00000060 143 #define SH4_UTLB_DA1_V 0x00000100 144 #define SH4_UTLB_DA1_PPN_SHIFT 11 145 #define SH4_UTLB_DA1_PPN_MASK 0x1ffffc00 /* [28:10] */ 146 /* data-array 2 */ 147 #define SH4_UTLB_DA2 0xf7800000 148 #define SH4_UTLB_DA2_SA_MASK 0x00000003 149 #define SH4_UTLB_DA2_TC 0x00000004 150 151 #endif !_SH3_MMU_SH4_H_ 152
Indexes created Mon Sep 29 21:09:56 GMT 2025