pmb.h revision 1.4
1/* $NetBSD: pmb.h,v 1.4 2020/07/30 21:25:43 uwe Exp $ */ 2/* 3 * Copyright (c) 2020 Valery Ushakov 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#ifndef _SH3_PMB_H_ 28#define _SH3_PMB_H_ 29/* 30 * ST40 Privileged Mapping Buffer (PMB) 31 * 32 * Original SuperH can handle only 29-bit external memory space. 33 * "The physical address space is permanently mapped onto 29-bit 34 * external memory space." See <sh3/cpu.h>. 35 * 36 * ST40-200, ST40-300 and ST40-500 have "space enhanced" SE mode where 37 * the mapping from the physical address space P1 and P2 segments to 38 * the 32-bit external memory space is defined via 16-entry PMB. 39 */ 40 41 42/* on ST40-200 and ST40-500 SE bit is in MMUCR */ 43#define ST40_MMUCR_SE 0x00000010 44 45 46/* Physical address space control register (ST4-300) */ 47#define ST40_PASCR 0xff000070 48#define ST40_PASCR_UB_MASK 0x0000000f 49#define ST40_PASCR_SE 0x80000000 50 51#define ST40_PASCR_BITS \ 52 "\177\020" \ 53 "b\037" "SE\0" \ 54 "f\0\04" "UB\0" 55 56 57/* Memory-mapped PMB */ 58#define ST40_PMB_ENTRY 16 59 60#define ST40_PMB_E_MASK 0x00000f00 61#define ST40_PMB_E_SHIFT 8 62 63 64/* PMB Address Array */ 65#define ST40_PMB_AA 0xf6100000 66#define ST40_PMB_AA_V 0x00000100 67#define ST40_PMB_AA_VPN_MASK 0xff000000 68#define ST40_PMB_AA_VPN_SHIFT 24 69 70#define ST40_PMB_AA_BITS \ 71 "\177\020" \ 72 "f\030\010" "VPN\0" \ 73 "b\010" "V\0" 74 75 76/* PMB Data Array */ 77#define ST40_PMB_DA 0xf7100000 78#define ST40_PMB_DA_WT 0x00000001 79#define ST40_PMB_DA_C 0x00000008 80#define ST40_PMB_DA_UB 0x00000200 81#define ST40_PMB_DA_SZ_MASK 0x00000090 82#define ST40_PMB_DA_SZ_16M 0x00000000 83#define ST40_PMB_DA_SZ_64M 0x00000010 84#define ST40_PMB_DA_SZ_128M 0x00000080 85#define ST40_PMB_DA_SZ_512M 0x00000090 86#define ST40_PMB_DA_V 0x00000100 87#define ST40_PMB_DA_PPN_MASK 0xff000000 88#define ST40_PMB_DA_PPN_SHIFT 24 89 90/* 91 * size field is not continuous hence the kludgy list with all the 92 * possible junk bits in the middle. 93 */ 94#define ST40_PMB_DA_BITS \ 95 "\177\020" \ 96 "f\030\010" "PPN\0" \ 97 "b\010" "V\0" \ 98 "F\04\04" "\0" \ 99 ":\017" "512M\0" \ 100 ":\016" "128M\0" \ 101 ":\015" "512M\0" \ 102 ":\014" "128M\0" \ 103 ":\013" "512M\0" \ 104 ":\012" "128M\0" \ 105 ":\011" "512M\0" \ 106 ":\010" "128M\0" \ 107 ":\007" "64M\0" \ 108 ":\006" "16M\0" \ 109 ":\005" "64M\0" \ 110 ":\004" "16M\0" \ 111 ":\003" "64M\0" \ 112 ":\002" "16M\0" \ 113 ":\001" "64M\0" \ 114 ":\000" "16M\0" \ 115 "b\011" "UB\0" \ 116 "b\03" "C\0" \ 117 "F\0\01" "\0" \ 118 ":\01" "WT\0" \ 119 ":\0" "CB\0" 120 121 122#ifndef _LOCORE 123void st40_pmb_init(int); 124#endif /* !_LOCORE */ 125 126#endif /* !_SH3_PMB_H_ */ 127