1 1.13 andvar /* $NetBSD: psl.h,v 1.13 2025/06/27 19:52:04 andvar Exp $ */ 2 1.1 itojun 3 1.1 itojun /*- 4 1.1 itojun * Copyright (c) 1990 The Regents of the University of California. 5 1.1 itojun * All rights reserved. 6 1.1 itojun * 7 1.1 itojun * This code is derived from software contributed to Berkeley by 8 1.1 itojun * William Jolitz. 9 1.1 itojun * 10 1.1 itojun * Redistribution and use in source and binary forms, with or without 11 1.1 itojun * modification, are permitted provided that the following conditions 12 1.1 itojun * are met: 13 1.1 itojun * 1. Redistributions of source code must retain the above copyright 14 1.1 itojun * notice, this list of conditions and the following disclaimer. 15 1.1 itojun * 2. Redistributions in binary form must reproduce the above copyright 16 1.1 itojun * notice, this list of conditions and the following disclaimer in the 17 1.1 itojun * documentation and/or other materials provided with the distribution. 18 1.7 agc * 3. Neither the name of the University nor the names of its contributors 19 1.1 itojun * may be used to endorse or promote products derived from this software 20 1.1 itojun * without specific prior written permission. 21 1.1 itojun * 22 1.1 itojun * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 1.1 itojun * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 1.1 itojun * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 1.1 itojun * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 1.1 itojun * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 1.1 itojun * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 1.1 itojun * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 1.1 itojun * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 1.1 itojun * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 1.1 itojun * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 1.1 itojun * SUCH DAMAGE. 33 1.1 itojun * 34 1.1 itojun * @(#)psl.h 5.2 (Berkeley) 1/18/91 35 1.1 itojun */ 36 1.1 itojun 37 1.1 itojun #ifndef _SH3_PSL_H_ 38 1.5 uch #define _SH3_PSL_H_ 39 1.1 itojun 40 1.1 itojun /* 41 1.13 andvar * SuperH Processor Status Register. 42 1.1 itojun */ 43 1.5 uch #define PSL_TBIT 0x00000001 /* T bit */ 44 1.5 uch #define PSL_SBIT 0x00000002 /* S bit */ 45 1.5 uch #define PSL_IMASK 0x000000f0 /* Interrupt Mask bit */ 46 1.1 itojun #define PSL_QBIT 0x00000100 /* Q bit */ 47 1.1 itojun #define PSL_MBIT 0x00000200 /* M bit */ 48 1.11 uwe #define PSL_FD 0x00008000 /* FPU Disable bit */ 49 1.3 uch #define PSL_BL 0x10000000 /* Exception Block bit */ 50 1.1 itojun #define PSL_RB 0x20000000 /* Register Bank bit */ 51 1.1 itojun #define PSL_MD 0x40000000 /* Processor Mode bit */ 52 1.3 uch /* 1 = kernel, 0 = user */ 53 1.1 itojun 54 1.1 itojun #define PSL_MBO 0x00000000 /* must be one bits */ 55 1.1 itojun #define PSL_MBZ 0x8ffffc0c /* must be zero bits */ 56 1.1 itojun 57 1.5 uch #define PSL_USERSET 0 58 1.5 uch #define PSL_USERSTATIC (PSL_BL|PSL_RB|PSL_MD|PSL_IMASK|PSL_MBO|PSL_MBZ) 59 1.1 itojun 60 1.3 uch #define KERNELMODE(sr) ((sr) & PSL_MD) 61 1.3 uch 62 1.1 itojun #ifdef _KERNEL 63 1.3 uch #ifndef _LOCORE 64 1.9 uwe 65 1.12 uwe static inline __always_inline void 66 1.12 uwe _cpu_set_sr(uint32_t sr) 67 1.12 uwe { 68 1.12 uwe __asm volatile("ldc %0, sr" :: "r"(sr)); 69 1.12 uwe } 70 1.12 uwe 71 1.4 uch /* SR.IMASK */ 72 1.4 uch int _cpu_intr_raise(int); 73 1.4 uch int _cpu_intr_suspend(void); 74 1.4 uch int _cpu_intr_resume(int); 75 1.9 uwe 76 1.4 uch /* SR.BL */ 77 1.4 uch int _cpu_exception_suspend(void); 78 1.4 uch void _cpu_exception_resume(int); 79 1.3 uch 80 1.9 uwe #endif /* !_LOCORE */ 81 1.3 uch #endif /* _KERNEL */ 82 1.1 itojun 83 1.1 itojun #endif /* !_SH3_PSL_H_ */ 84