rtcreg.h revision 1.5
1 1.5 uch /* $NetBSD: rtcreg.h,v 1.5 2002/02/22 19:44:02 uch Exp $ */ 2 1.1 itojun 3 1.1 itojun /*- 4 1.1 itojun * Copyright (C) 1999 SAITOH Masanobu. All rights reserved. 5 1.1 itojun * 6 1.1 itojun * Redistribution and use in source and binary forms, with or without 7 1.1 itojun * modification, are permitted provided that the following conditions 8 1.1 itojun * are met: 9 1.1 itojun * 1. Redistributions of source code must retain the above copyright 10 1.1 itojun * notice, this list of conditions and the following disclaimer. 11 1.1 itojun * 2. Redistributions in binary form must reproduce the above copyright 12 1.1 itojun * notice, this list of conditions and the following disclaimer in the 13 1.1 itojun * documentation and/or other materials provided with the distribution. 14 1.1 itojun * 3. The name of the author may not be used to endorse or promote products 15 1.1 itojun * derived from this software without specific prior written permission. 16 1.1 itojun * 17 1.1 itojun * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 1.1 itojun * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 1.1 itojun * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 1.1 itojun * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 1.1 itojun * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 1.1 itojun * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 1.1 itojun * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 1.1 itojun * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 1.1 itojun * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 1.1 itojun * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 1.1 itojun */ 28 1.1 itojun 29 1.1 itojun #ifndef _SH3_RTCREG_H__ 30 1.1 itojun #define _SH3_RTCREG_H__ 31 1.1 itojun 32 1.1 itojun /* 33 1.5 uch * RTC 34 1.1 itojun */ 35 1.5 uch #define SH3_R64CNT 0xfffffec0 36 1.5 uch #define SH3_RSECCNT 0xfffffec2 37 1.5 uch #define SH3_RMINCNT 0xfffffec4 38 1.5 uch #define SH3_RHRCNT 0xfffffec6 39 1.5 uch #define SH3_RWKCNT 0xfffffec8 40 1.5 uch #define SH3_RDAYCNT 0xfffffeca 41 1.5 uch #define SH3_RMONCNT 0xfffffecc 42 1.5 uch #define SH3_RYRCNT 0xfffffece 43 1.5 uch #define SH3_RSECAR 0xfffffed0 44 1.5 uch #define SH3_RMINAR 0xfffffed2 45 1.5 uch #define SH3_RHRAR 0xfffffed4 46 1.5 uch #define SH3_RWKAR 0xfffffed6 47 1.5 uch #define SH3_RDAYAR 0xfffffed8 48 1.5 uch #define SH3_RMONAR 0xfffffeda 49 1.5 uch #define SH3_RCR1 0xfffffedc 50 1.5 uch #define SH3_RCR2 0xfffffede 51 1.5 uch 52 1.5 uch #define SH4_R64CNT 0xffc80000 53 1.5 uch #define SH4_RSECCNT 0xffc80004 54 1.5 uch #define SH4_RMINCNT 0xffc80008 55 1.5 uch #define SH4_RHRCNT 0xffc8000c 56 1.5 uch #define SH4_RWKCNT 0xffc80010 57 1.5 uch #define SH4_RDAYCNT 0xffc80014 58 1.5 uch #define SH4_RMONCNT 0xffc80018 59 1.5 uch #define SH4_RYRCNT 0xffc8001c /* 16 bit */ 60 1.5 uch #define SH4_RSECAR 0xffc80020 61 1.5 uch #define SH4_RMINAR 0xffc80024 62 1.5 uch #define SH4_RHRAR 0xffc80028 63 1.5 uch #define SH4_RWKAR 0xffc8002c 64 1.5 uch #define SH4_RDAYAR 0xffc80030 65 1.5 uch #define SH4_RMONAR 0xffc80034 66 1.5 uch #define SH4_RCR1 0xffc80038 67 1.5 uch #define SH4_RCR2 0xffc8003c 68 1.5 uch 69 1.5 uch #define SH_RCR1_CF 0x80 70 1.5 uch #define SH_RCR1_CIE 0x10 71 1.5 uch #define SH_RCR1_AIE 0x08 72 1.5 uch #define SH_RCR1_AF 0x01 73 1.5 uch #define SH_RCR2_PEF 0x80 74 1.5 uch #define SH_RCR2_PES2 0x40 75 1.5 uch #define SH_RCR2_PES1 0x20 76 1.5 uch #define SH_RCR2_PES0 0x10 77 1.5 uch #define SH_RCR2_ENABLE 0x08 78 1.5 uch #define SH_RCR2_ADJ 0x04 79 1.5 uch #define SH_RCR2_RESET 0x02 80 1.5 uch #define SH_RCR2_START 0x01 81 1.1 itojun 82 1.1 itojun #endif /* !_SH3_RTCREG_H__ */ 83
Indexes created Thu Sep 25 16:09:42 GMT 2025