rtcreg.h revision 1.5
1 /* $NetBSD: rtcreg.h,v 1.5 2002/02/22 19:44:02 uch Exp $ */ 2 3 /*- 4 * Copyright (C) 1999 SAITOH Masanobu. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef _SH3_RTCREG_H__ 30 #define _SH3_RTCREG_H__ 31 32 /* 33 * RTC 34 */ 35 #define SH3_R64CNT 0xfffffec0 36 #define SH3_RSECCNT 0xfffffec2 37 #define SH3_RMINCNT 0xfffffec4 38 #define SH3_RHRCNT 0xfffffec6 39 #define SH3_RWKCNT 0xfffffec8 40 #define SH3_RDAYCNT 0xfffffeca 41 #define SH3_RMONCNT 0xfffffecc 42 #define SH3_RYRCNT 0xfffffece 43 #define SH3_RSECAR 0xfffffed0 44 #define SH3_RMINAR 0xfffffed2 45 #define SH3_RHRAR 0xfffffed4 46 #define SH3_RWKAR 0xfffffed6 47 #define SH3_RDAYAR 0xfffffed8 48 #define SH3_RMONAR 0xfffffeda 49 #define SH3_RCR1 0xfffffedc 50 #define SH3_RCR2 0xfffffede 51 52 #define SH4_R64CNT 0xffc80000 53 #define SH4_RSECCNT 0xffc80004 54 #define SH4_RMINCNT 0xffc80008 55 #define SH4_RHRCNT 0xffc8000c 56 #define SH4_RWKCNT 0xffc80010 57 #define SH4_RDAYCNT 0xffc80014 58 #define SH4_RMONCNT 0xffc80018 59 #define SH4_RYRCNT 0xffc8001c /* 16 bit */ 60 #define SH4_RSECAR 0xffc80020 61 #define SH4_RMINAR 0xffc80024 62 #define SH4_RHRAR 0xffc80028 63 #define SH4_RWKAR 0xffc8002c 64 #define SH4_RDAYAR 0xffc80030 65 #define SH4_RMONAR 0xffc80034 66 #define SH4_RCR1 0xffc80038 67 #define SH4_RCR2 0xffc8003c 68 69 #define SH_RCR1_CF 0x80 70 #define SH_RCR1_CIE 0x10 71 #define SH_RCR1_AIE 0x08 72 #define SH_RCR1_AF 0x01 73 #define SH_RCR2_PEF 0x80 74 #define SH_RCR2_PES2 0x40 75 #define SH_RCR2_PES1 0x20 76 #define SH_RCR2_PES0 0x10 77 #define SH_RCR2_ENABLE 0x08 78 #define SH_RCR2_ADJ 0x04 79 #define SH_RCR2_RESET 0x02 80 #define SH_RCR2_START 0x01 81 82 #endif /* !_SH3_RTCREG_H__ */ 83
Indexes created Fri Sep 26 08:10:20 GMT 2025