scifreg.h revision 1.1
1 /* $NetBSD: scifreg.h,v 1.1 1999/09/13 10:31:22 itojun Exp $ */ 2 3 /*- 4 * Copyright (C) 1999 SAITOH Masanobu. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef _SH3_SCIFREG_H_ 30 #define _SH3_SCIFREG_H_ 31 32 #ifndef BYTE_ORDER 33 #error Define BYTE_ORDER! 34 #endif 35 36 /* 37 * Serial Communication Interface (SCIF) 38 */ 39 40 #if !defined(SH4) 41 42 /* SH3 definitions */ 43 44 /* Serial Mode Register */ 45 typedef union { 46 unsigned char BYTE; /* Byte Access */ 47 struct { /* Bit Access */ 48 #if BYTE_ORDER == BIG_ENDIAN 49 /* Bit 7..0 */ 50 unsigned char CA :1; 51 unsigned char CHR :1; 52 unsigned char PE :1; 53 unsigned char OE :1; 54 unsigned char STOP:1; 55 unsigned char MP :1; 56 unsigned char CKS :2; 57 #else /* BYTE_ORDER == LITTLE_ENDIAN */ 58 /* Bit 0..7 */ 59 unsigned char CKS :2; 60 unsigned char MP :1; 61 unsigned char STOP:1; 62 unsigned char OE :1; 63 unsigned char PE :1; 64 unsigned char CHR :1; 65 unsigned char CA :1; 66 #endif 67 } BIT; 68 } SH3SCSMR; 69 70 /* Serial Control Register */ 71 typedef union { 72 unsigned char BYTE; /* Byte Access */ 73 struct { /* Bit Access */ 74 #if BYTE_ORDER == BIG_ENDIAN 75 /* Bit 7..0 */ 76 unsigned char TIE :1; 77 unsigned char RIE :1; 78 unsigned char TE :1; 79 unsigned char RE :1; 80 unsigned char MPIE:1; 81 unsigned char TEIE:1; 82 unsigned char CKE :2; 83 #else /* BYTE_ORDER == LITTLE_ENDIAN */ 84 /* Bit 0..7 */ 85 unsigned char CKE :2; 86 unsigned char TEIE:1; 87 unsigned char MPIE:1; 88 unsigned char RE :1; 89 unsigned char TE :1; 90 unsigned char RIE :1; 91 unsigned char TIE :1; 92 #endif 93 } BIT; 94 } SH3SCSCR; 95 96 /* Serial Status Register */ 97 typedef union { 98 unsigned char BYTE; /* Byte Access */ 99 struct { /* Bit Access */ 100 #if BYTE_ORDER == BIG_ENDIAN 101 /* Bit 7..0 */ 102 unsigned char TDRE:1; 103 unsigned char RDRF:1; 104 unsigned char ORER:1; 105 unsigned char FER :1; 106 unsigned char PER :1; 107 unsigned char TEND:1; 108 unsigned char MPB :1; 109 unsigned char MPBT:1; 110 #else /* BYTE_ORDER == LITTLE_ENDIAN */ 111 /* Bit 0..7 */ 112 unsigned char MPBT:1; 113 unsigned char MPB :1; 114 unsigned char TEND:1; 115 unsigned char PER :1; 116 unsigned char FER :1; 117 unsigned char ORER:1; 118 unsigned char RDRF:1; 119 unsigned char TDRE:1; 120 #endif 121 } BIT; 122 } SH3SCSSR; 123 124 125 #define SHREG_SCSMR2 (*(volatile unsigned char *) 0xa4000150) 126 #define SHREG_SCBRR2 (*(volatile unsigned char *) 0xa4000152) 127 #define SHREG_SCSCR2 (*(volatile unsigned char *) 0xa4000154) 128 #define SHREG_SCFTDR2 (*(volatile unsigned char *) 0xa4000156) 129 #define SHREG_SCSSR2 (*(volatile unsigned short *) 0xa4000158) 130 #define SHREG_SCFRDR2 (*(volatile unsigned char *) 0xa400015A) 131 #define SHREG_SCFCR2 (*(volatile unsigned char *) 0xa400015C) 132 #define SHREG_SCFDR2 (*(volatile unsigned short *) 0xa400015E) 133 134 #define SCSCR2_TIE 0x80 /* Transmit Interrupt Enable */ 135 #define SCSCR2_RIE 0x40 /* Recieve Interrupt Enable */ 136 #define SCSCR2_TE 0x20 /* Transmit Enable */ 137 #define SCSCR2_RE 0x10 /* Receive Enable */ 138 #define SCSCR2_CKE1 0x02 /* ClocK Enable 1 */ 139 #define SCSCR2_CKE0 0x01 /* ClocK Enable 0 */ 140 141 #define SCSSR2_ER 0x0080 /* ERror */ 142 #define SCSSR2_TEND 0x0040 /* Transmit END */ 143 #define SCSSR2_TDFE 0x0020 /* Transmit Data Fifo Empty */ 144 #define SCSSR2_BRK 0x0010 /* BReaK detection */ 145 #define SCSSR2_FER 0x0008 /* Framing ERror */ 146 #define SCSSR2_PER 0x0004 /* Parity ERror */ 147 #define SCSSR2_RDF 0x0002 /* Recieve fifo Data Full */ 148 #define SCSSR2_DR 0x0001 /* Data Ready */ 149 150 #define SCFCR2_RTRG1 0x80 /* Receive TRiGger 1 */ 151 #define SCFCR2_RTRG0 0x40 /* Receive TRiGger 0 */ 152 #define SCFCR2_TTRG1 0x20 /* Transmit TRiGger 1 */ 153 #define SCFCR2_TTRG0 0x10 /* Transmit TRiGger 0 */ 154 #define SCFCR2_MCE 0x08 /* Modem Control Enable */ 155 #define SCFCR2_TFRST 0x04 /* Transmit Fifo register ReSeT */ 156 #define SCFCR2_RFRST 0x02 /* Receive Fifo register ReSeT */ 157 #define SCFCR2_LOOP 0x01 /* LOOP back test */ 158 #define FIFO_RCV_TRIGGER_1 0x00 159 #define FIFO_RCV_TRIGGER_4 0x40 160 #define FIFO_RCV_TRIGGER_8 0x80 161 #define FIFO_RCV_TRIGGER_14 0xc0 162 #define FIFO_XMT_TRIGGER_8 0x00 163 #define FIFO_XMT_TRIGGER_4 0x10 164 #define FIFO_XMT_TRIGGER_2 0x20 165 #define FIFO_XMT_TRIGGER_1 0x30 166 167 #else 168 169 /* SH4 definitions */ 170 171 /* Serial Mode Register */ 172 typedef union { 173 unsigned short BYTE; /* Byte Access */ 174 struct { /* Bit Access */ 175 #if BYTE_ORDER == BIG_ENDIAN 176 /* Bit 15..0 */ 177 unsigned short :8; 178 unsigned short CA :1; 179 unsigned short CHR :1; 180 unsigned short PE :1; 181 unsigned short OE :1; 182 unsigned short STOP :1; 183 unsigned short MP :1; 184 unsigned short CKS :2; 185 #else /* BYTE_ORDER == LITTLE_ENDIAN */ 186 /* Bit 0..15 */ 187 unsigned short CKS :2; 188 unsigned short MP :1; 189 unsigned short STOP :1; 190 unsigned short OE :1; 191 unsigned short PE :1; 192 unsigned short CHR :1; 193 unsigned short CA :1; 194 unsigned short :8; 195 #endif 196 } BIT; 197 } SH3SCSMR; 198 199 /* Serial Control Register */ 200 typedef union { 201 unsigned short BYTE; /* Byte Access */ 202 struct { /* Bit Access */ 203 #if BYTE_ORDER == BIG_ENDIAN 204 /* Bit 15..0 */ 205 unsigned short :8; 206 unsigned short TIE :1; 207 unsigned short RIE :1; 208 unsigned short TE :1; 209 unsigned short RE :1; 210 unsigned short REIE :1; 211 unsigned short :1; 212 unsigned short CKE1 :1; 213 unsigned short :1; 214 #else /* BYTE_ORDER == LITTLE_ENDIAN */ 215 /* Bit 0..15 */ 216 unsigned short :1; 217 unsigned short CKE1 :1; 218 unsigned short :1; 219 unsigned short REIE :1; 220 unsigned short RE :1; 221 unsigned short TE :1; 222 unsigned short RIE :1; 223 unsigned short TIE :1; 224 unsigned short :8; 225 #endif 226 } BIT; 227 } SH3SCSCR; 228 229 /* Serial Status Register */ 230 typedef union { 231 unsigned short BYTE; /* Byte Access */ 232 struct { /* Bit Access */ 233 #if BYTE_ORDER == BIG_ENDIAN 234 /* Bit 15..0 */ 235 unsigned short PER3 :1; 236 unsigned short PER2 :1; 237 unsigned short PER1 :1; 238 unsigned short PER0 :1; 239 unsigned short FER3 :1; 240 unsigned short FER2 :1; 241 unsigned short FER1 :1; 242 unsigned short FER0 :1; 243 unsigned short ER :1; 244 unsigned short TEND :1; 245 unsigned short TDFE :1; 246 unsigned short BRK :1; 247 unsigned short FER :1; 248 unsigned short PER :1; 249 unsigned short RDF :1; 250 unsigned short DR :1; 251 #else /* BYTE_ORDER == LITTLE_ENDIAN */ 252 /* Bit 0..15 */ 253 unsigned short DR :1; 254 unsigned short RDF :1; 255 unsigned short PER :1; 256 unsigned short FER :1; 257 unsigned short BRK :1; 258 unsigned short TDFE :1; 259 unsigned short TEND :1; 260 unsigned short ER :1; 261 unsigned short FER0 :1; 262 unsigned short FER1 :1; 263 unsigned short FER2 :1; 264 unsigned short FER3 :1; 265 unsigned short PER0 :1; 266 unsigned short PER1 :1; 267 unsigned short PER2 :1; 268 unsigned short PER3 :1; 269 #endif 270 } BIT; 271 } SH3SCSSR; 272 273 #define SHREG_SCSMR2 (*(volatile unsigned short *) 0xffe80000) 274 #define SHREG_SCBRR2 (*(volatile unsigned char *) 0xffe80004) 275 #define SHREG_SCSCR2 (*(volatile unsigned short *) 0xffe80008) 276 #define SHREG_SCFTDR2 (*(volatile unsigned char *) 0xffe8000c) 277 #define SHREG_SCFSR2 (*(volatile unsigned short *) 0xffe80010) 278 #define SHREG_SCFRDR2 (*(volatile unsigned char *) 0xffe80014) 279 #define SHREG_SCFCR2 (*(volatile unsigned short *) 0xffe80018) 280 #define SHREG_SCFDR2 (*(volatile unsigned short *) 0xffe8001c) 281 #define SHREG_SCSPTR2 (*(volatile unsigned short *) 0xffe80020) 282 #define SHREG_SCLSR2 (*(volatile unsigned short *) 0xffe80024) 283 284 /* alias */ 285 #define SHREG_SCSFDR2 SHREG_SCFTDR2 286 #define SHREG_SCSSR2 SHREG_SCFSR2 287 288 #define SCSCR2_TIE 0x0080 /* Transmit Interrupt Enable */ 289 #define SCSCR2_RIE 0x0040 /* Recieve Interrupt Enable */ 290 #define SCSCR2_TE 0x0020 /* Transmit Enable */ 291 #define SCSCR2_RE 0x0010 /* Receive Enable */ 292 #define SCSCR2_CKE1 0x0002 /* ClocK Enable 1 */ 293 294 #define SCSSR2_ER 0x0080 /* ERror */ 295 #define SCSSR2_TEND 0x0040 /* Transmit END */ 296 #define SCSSR2_TDFE 0x0020 /* Transmit Data Fifo Empty */ 297 #define SCSSR2_BRK 0x0010 /* BReaK detection */ 298 #define SCSSR2_FER 0x0008 /* Framing ERror */ 299 #define SCSSR2_PER 0x0004 /* Parity ERror */ 300 #define SCSSR2_RDF 0x0002 /* Recieve fifo Data Full */ 301 #define SCSSR2_DR 0x0001 /* Data Ready */ 302 303 #define SCFCR2_RTRG1 0x0080 /* Receive TRiGger 1 */ 304 #define SCFCR2_RTRG0 0x0040 /* Receive TRiGger 0 */ 305 #define SCFCR2_TTRG1 0x0020 /* Transmit TRiGger 1 */ 306 #define SCFCR2_TTRG0 0x0010 /* Transmit TRiGger 0 */ 307 #define SCFCR2_MCE 0x0008 /* Modem Control Enable */ 308 #define SCFCR2_TFRST 0x0004 /* Transmit Fifo register ReSeT */ 309 #define SCFCR2_RFRST 0x0002 /* Receive Fifo register ReSeT */ 310 #define SCFCR2_LOOP 0x0001 /* LOOP back test */ 311 #define FIFO_RCV_TRIGGER_1 0x0000 312 #define FIFO_RCV_TRIGGER_4 0x0040 313 #define FIFO_RCV_TRIGGER_8 0x0080 314 #define FIFO_RCV_TRIGGER_14 0x00c0 315 #define FIFO_XMT_TRIGGER_8 0x0000 316 #define FIFO_XMT_TRIGGER_4 0x0010 317 #define FIFO_XMT_TRIGGER_2 0x0020 318 #define FIFO_XMT_TRIGGER_1 0x0030 319 320 #endif 321 322 /* common definitions */ 323 324 #define SCFDR2_TXCNT 0xff00 /* Tx CouNT */ 325 #define SCFDR2_RECVCNT 0x00ff /* Rx CouNT */ 326 #define SCFDR2_TXF_FULL 0x1000 /* Tx FULL */ 327 #define SCFDR2_RXF_EPTY 0x0000 /* Rx EMPTY */ 328 329 #endif /* !_SH3_SCIFREG_ */ 330
Indexes created Mon Sep 29 21:09:56 GMT 2025