scireg.h revision 1.1
1 /* $NetBSD: scireg.h,v 1.1 1999/09/13 10:31:22 itojun Exp $ */ 2 3 /*- 4 * Copyright (C) 1999 SAITOH Masanobu. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef _SH3_SCIREG_H_ 30 #define _SH3_SCIREG_H_ 31 32 #ifndef BYTE_ORDER 33 #error Define BYTE_ORDER! 34 #endif 35 36 /* 37 * Serial Communication Interface (SCI) 38 */ 39 40 /* Serial Mode Register */ 41 typedef union { 42 unsigned char BYTE; /* Byte Access */ 43 struct { /* Bit Access */ 44 #if BYTE_ORDER == BIG_ENDIAN 45 /* Bit 7..0 */ 46 unsigned char CA :1; 47 unsigned char CHR :1; 48 unsigned char PE :1; 49 unsigned char OE :1; 50 unsigned char STOP:1; 51 unsigned char MP :1; 52 unsigned char CKS :2; 53 #else /* BYTE_ORDER == LITTLE_ENDIAN */ 54 /* Bit 0..7 */ 55 unsigned char CKS :2; 56 unsigned char MP :1; 57 unsigned char STOP:1; 58 unsigned char OE :1; 59 unsigned char PE :1; 60 unsigned char CHR :1; 61 unsigned char CA :1; 62 #endif 63 } BIT; 64 } SH3SCSMR; 65 66 /* Serial Control Register */ 67 typedef union { 68 unsigned char BYTE; /* Byte Access */ 69 struct { /* Bit Access */ 70 #if BYTE_ORDER == BIG_ENDIAN 71 /* Bit 7..0 */ 72 unsigned char TIE :1; 73 unsigned char RIE :1; 74 unsigned char TE :1; 75 unsigned char RE :1; 76 unsigned char MPIE:1; 77 unsigned char TEIE:1; 78 unsigned char CKE :2; 79 #else /* BYTE_ORDER == LITTLE_ENDIAN */ 80 /* Bit 0..7 */ 81 unsigned char CKE :2; 82 unsigned char TEIE:1; 83 unsigned char MPIE:1; 84 unsigned char RE :1; 85 unsigned char TE :1; 86 unsigned char RIE :1; 87 unsigned char TIE :1; 88 #endif 89 } BIT; 90 } SH3SCSCR; 91 92 /* Serial Status Register */ 93 typedef union { 94 unsigned char BYTE; /* Byte Access */ 95 struct { /* Bit Access */ 96 #if BYTE_ORDER == BIG_ENDIAN 97 /* Bit 7..0 */ 98 unsigned char TDRE:1; 99 unsigned char RDRF:1; 100 unsigned char ORER:1; 101 unsigned char FER :1; 102 unsigned char PER :1; 103 unsigned char TEND:1; 104 unsigned char MPB :1; 105 unsigned char MPBT:1; 106 #else /* BYTE_ORDER == LITTLE_ENDIAN */ 107 /* Bit 0..7 */ 108 unsigned char MPBT:1; 109 unsigned char MPB :1; 110 unsigned char TEND:1; 111 unsigned char PER :1; 112 unsigned char FER :1; 113 unsigned char ORER:1; 114 unsigned char RDRF:1; 115 unsigned char TDRE:1; 116 #endif 117 } BIT; 118 } SH3SCSSR; 119 120 121 #if !defined(SH4) 122 123 /* SH3 definitions */ 124 125 #define SHREG_SCSMR (*(volatile unsigned char *) 0xFFFFFE80) 126 #define SHREG_SCBRR (*(volatile unsigned char *) 0xFFFFFE82) 127 #define SHREG_SCSCR (*(volatile unsigned char *) 0xFFFFFE84) 128 #define SHREG_SCTDR (*(volatile unsigned char *) 0xFFFFFE86) 129 #define SHREG_SCSSR (*(volatile unsigned char *) 0xFFFFFE88) 130 #define SHREG_SCRDR (*(volatile unsigned char *) 0xFFFFFE8A) 131 132 #else 133 134 /* SH4 definitions */ 135 136 #define SHREG_SCSMR (*(volatile unsigned char *) 0xffe00000) 137 #define SHREG_SCBRR (*(volatile unsigned char *) 0xffe00004) 138 #define SHREG_SCSCR (*(volatile unsigned char *) 0xffe00008) 139 #define SHREG_SCTDR (*(volatile unsigned char *) 0xffe0000c) 140 #define SHREG_SCSSR (*(volatile unsigned char *) 0xffe00010) 141 #define SHREG_SCRDR (*(volatile unsigned char *) 0xffe00014) 142 143 #endif 144 145 #define SCSCR_TIE 0x80 /* Transmit Interrupt Enable */ 146 #define SCSCR_RIE 0x40 /* Recieve Interrupt Enable */ 147 #define SCSCR_TE 0x20 /* Transmit Enable */ 148 #define SCSCR_RE 0x10 /* Receive Enable */ 149 #define SCSCR_MPIE 0x08 /* Multi Processor Interrupt Enable */ 150 #define SCSCR_TEIE 0x04 /* Transmit End Interrupt Enable */ 151 #define SCSCR_CKE1 0x02 /* ClocK Enable 1 */ 152 #define SCSCR_CKE0 0x01 /* ClocK Enable 0 */ 153 154 #define SCSSR_TDRE 0x80 155 #define SCSSR_RDRF 0x40 156 #define SCSSR_ORER 0x20 157 #define SCSSR_FER 0x10 158 #define SCSSR_PER 0x08 159 160 #endif /* !_SH3_SCIREG_ */ 161
Indexes created Sun Sep 28 16:09:52 GMT 2025