tmureg.h revision 1.1
1 /* $NetBSD: tmureg.h,v 1.1 1999/09/13 10:31:23 itojun Exp $ */ 2 3 /*- 4 * Copyright (C) 1999 SAITOH Masanobu. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef _SH3_TMUREG_H_ 30 #define _SH3_TMUREG_H_ 31 32 #ifndef BYTE_ORDER 33 #error Define BYTE_ORDER! 34 #endif 35 36 /* 37 * Timer Unit 38 */ 39 struct sh3_tmu { 40 /* Timer Output Control Register (FFFFFE90) */ 41 union { 42 unsigned char BYTE; /* Byte Access */ 43 struct { /* Bit Access */ 44 #if BYTE_ORDER == BIG_ENDIAN 45 /* Bit 7..0 */ 46 unsigned char :7; 47 unsigned char TCOE:1; 48 #else /* BYTE_ORDER == LITTLE_ENDIAN */ 49 /* Bit 0..7 */ 50 unsigned char TCOE:1; 51 unsigned char :7; 52 #endif 53 } BIT; 54 } TOCR; 55 unsigned char dummy; 56 57 /* Timer Start Register (0xFFFFFE92) */ 58 union { 59 unsigned char BYTE; /* Byte Access */ 60 struct { /* Bit Access */ 61 #if BYTE_ORDER == BIG_ENDIAN 62 /* Bit 7..0 */ 63 unsigned char :5; 64 unsigned char STR2:1; 65 unsigned char STR1:1; 66 unsigned char STR0:1; 67 #else /* BYTE_ORDER == LITTLE_ENDIAN */ 68 /* Bit 0..7 */ 69 unsigned char STR0:1; 70 unsigned char STR1:1; 71 unsigned char STR2:1; 72 unsigned char :5; 73 #endif 74 } BIT; 75 } TSTR; 76 unsigned char dummy1; 77 78 /* Timer COnstant Register 0 (0xFFFFFE94) */ 79 unsigned int TCOR0; 80 81 /* Timer CouNTer 0 (0xFFFFFE98) */ 82 unsigned int TCNT0; 83 84 /* Timer Control Register 0 (0xFFFFFE9C) */ 85 union { 86 unsigned short WORD; /* Word Access */ 87 struct { /* Bit Access */ 88 #if BYTE_ORDER == BIG_ENDIAN 89 /* Bit 15..0 */ 90 unsigned short :7; 91 unsigned short UNF :1; 92 unsigned short :2; 93 unsigned short UNIE :1; 94 unsigned short CKEG1:1; 95 unsigned short CKEG0:1; 96 unsigned short TPSC2:1; 97 unsigned short TPSC1:1; 98 unsigned short TPSC0:1; 99 #else /* BYTE_ORDER == LITTLE_ENDIAN */ 100 /* Bit 0..15 */ 101 unsigned short TPSC0:1; 102 unsigned short TPSC1:1; 103 unsigned short TPSC2:1; 104 unsigned short CKEG0:1; 105 unsigned short CKEG1:1; 106 unsigned short UNIE :1; 107 unsigned short :2; 108 unsigned short UNF :1; 109 unsigned short :7; 110 #endif 111 } BIT; 112 } TCR0; 113 unsigned short dummy2; 114 115 /* Timer COnstant Register 1 (0xFFFFFEA0) */ 116 unsigned int TCOR1; 117 118 /* Timer CouNTer 1 (0xFFFFFEA4) */ 119 unsigned int TCNT1; 120 121 /* Timer Control Register 1 (0xFFFFFEA8) */ 122 union { 123 unsigned short WORD; /* Word Access */ 124 struct { /* Bit Access */ 125 #if BYTE_ORDER == BIG_ENDIAN 126 /* Bit 15..0 */ 127 unsigned short :7; 128 unsigned short UNF :1; 129 unsigned short :2; 130 unsigned short UNIE :1; 131 unsigned short CKEG1:1; 132 unsigned short CKEG0:1; 133 unsigned short TPSC2:1; 134 unsigned short TPSC1:1; 135 unsigned short TPSC0:1; 136 #else /* BYTE_ORDER == LITTLE_ENDIAN */ 137 /* Bit 0..15 */ 138 unsigned short TPSC0:1; 139 unsigned short TPSC1:1; 140 unsigned short TPSC2:1; 141 unsigned short CKEG0:1; 142 unsigned short CKEG1:1; 143 unsigned short UNIE :1; 144 unsigned short :2; 145 unsigned short UNF :1; 146 unsigned short :7; 147 #endif 148 } BIT; 149 } TCR1; 150 unsigned short dummy3; 151 152 /* Timer COnstant Register 2 (0xFFFFFEAC) */ 153 unsigned int TCOR2; 154 155 /* Timer CouNTer 2 (0xFFFFFEB0) */ 156 unsigned int TCNT2; 157 158 /* Timer Control Register 2 (0xFFFFFEB4) */ 159 union { 160 unsigned short WORD; /* Word Access */ 161 struct { /* Bit Access */ 162 #if BYTE_ORDER == BIG_ENDIAN 163 /* Bit 15..0 */ 164 unsigned short :5; 165 unsigned short ICPF1:1; 166 unsigned short ICPF0:1; 167 unsigned short UNF :1; 168 unsigned short ICPE :2; 169 unsigned short UNIE :1; 170 unsigned short CKEG1:1; 171 unsigned short CKEG0:1; 172 unsigned short TPSC2:1; 173 unsigned short TPSC1:1; 174 unsigned short TPSC0:1; 175 #else /* BYTE_ORDER == LITTLE_ENDIAN */ 176 /* Bit 0..15 */ 177 unsigned short TPSC0:1; 178 unsigned short TPSC1:1; 179 unsigned short TPSC2:1; 180 unsigned short CKEG0:1; 181 unsigned short CKEG1:1; 182 unsigned short UNIE :1; 183 unsigned short ICPE :2; 184 unsigned short UNF :1; 185 unsigned short ICPF0:1; 186 unsigned short ICPF1:1; 187 unsigned short :5; 188 #endif 189 } BIT; 190 } TCR2; 191 192 /* Input CaPture Register 2 (0xFFFFFEB8) */ 193 unsigned int TCPR2; 194 }; 195 196 #if !defined(SH4) 197 198 /* SH3 definition */ 199 200 /* TMU Address */ 201 #define SHREG_TMU (*(volatile struct sh3_tmu *) 0xFFFFFE90) 202 203 #else 204 205 /* SH4 address definition */ 206 207 /* TMU Address */ 208 #define SHREG_TMU (*(volatile struct sh3_tmu *) 0xffd80000) 209 210 #endif 211 212 #define TOCR_TCOE 0x01 213 214 #define TSTR_STR2 0x04 215 #define TSTR_STR1 0x02 216 #define TSTR_STR0 0x01 217 218 #define TCR_ICPF 0x0200 219 #define TCR_UNF 0x0100 220 #define TCR_ICPE1 0x0080 221 #define TCR_ICPE0 0x0040 222 #define TCR_UNIE 0x0020 223 #define TCR_CKEG1 0x0010 224 #define TCR_CKEG0 0x0008 225 #define TCR_TPSC2 0x0004 226 #define TCR_TPSC1 0x0002 227 #define TCR_TPSC0 0x0001 228 229 #endif /* !_SH3_TMUREG_H_ */ 230
Indexes created Fri Sep 26 20:09:58 GMT 2025