tmureg.h revision 1.6
1 /* $NetBSD: tmureg.h,v 1.6 2002/02/28 01:56:58 uch Exp $ */ 2 3 /*- 4 * Copyright (C) 1999 SAITOH Masanobu. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef _SH3_TMUREG_H_ 30 #define _SH3_TMUREG_H_ 31 #include <sh3/devreg.h> 32 33 /* 34 * TMU 35 */ 36 #define SH3_TOCR 0xfffffe90 37 #define SH3_TSTR 0xfffffe92 38 #define SH3_TCOR0 0xfffffe94 39 #define SH3_TCNT0 0xfffffe98 40 #define SH3_TCR0 0xfffffe9c 41 #define SH3_TCOR1 0xfffffea0 42 #define SH3_TCNT1 0xfffffea4 43 #define SH3_TCR1 0xfffffea8 44 #define SH3_TCOR2 0xfffffeac 45 #define SH3_TCNT2 0xfffffeb0 46 #define SH3_TCR2 0xfffffeb4 47 #define SH3_TCPR2 0xfffffeb8 48 49 #define SH4_TOCR 0xffd80000 50 #define SH4_TSTR 0xffd80004 51 #define SH4_TCOR0 0xffd80008 52 #define SH4_TCNT0 0xffd8000c 53 #define SH4_TCR0 0xffd80010 54 #define SH4_TCOR1 0xffd80014 55 #define SH4_TCNT1 0xffd80018 56 #define SH4_TCR1 0xffd8001c 57 #define SH4_TCOR2 0xffd80020 58 #define SH4_TCNT2 0xffd80024 59 #define SH4_TCR2 0xffd80028 60 #define SH4_TCPR2 0xffd8002c 61 62 #define TOCR_TCOE 0x01 63 #define TSTR_STR2 0x04 64 #define TSTR_STR1 0x02 65 #define TSTR_STR0 0x01 66 #define TCR_ICPF 0x0200 67 #define TCR_UNF 0x0100 68 #define TCR_ICPE1 0x0080 69 #define TCR_ICPE0 0x0040 70 #define TCR_UNIE 0x0020 71 #define TCR_CKEG1 0x0010 72 #define TCR_CKEG0 0x0008 73 #define TCR_TPSC2 0x0004 74 #define TCR_TPSC1 0x0002 75 #define TCR_TPSC0 0x0001 76 #define TCR_TPSC_P4 0x0000 77 #define TCR_TPSC_P16 0x0001 78 #define TCR_TPSC_P64 0x0002 79 #define TCR_TPSC_P256 0x0003 80 #define SH3_TCR_TPSC_RTC 0x0004 81 #define SH3_TCR_TPSC_TCLK 0x0005 82 #define SH4_TCR_TPSC_P512 0x0004 83 #define SH4_TCR_TPSC_RTC 0x0006 84 #define SH4_TCR_TPSC_TCLK 0x0007 85 86 #ifndef _LOCORE 87 #if defined(SH3) && defined(SH4) 88 extern u_int32_t __sh_TOCR; 89 extern u_int32_t __sh_TSTR; 90 extern u_int32_t __sh_TCOR0; 91 extern u_int32_t __sh_TCNT0; 92 extern u_int32_t __sh_TCR0; 93 extern u_int32_t __sh_TCOR1; 94 extern u_int32_t __sh_TCNT1; 95 extern u_int32_t __sh_TCR1; 96 extern u_int32_t __sh_TCOR2; 97 extern u_int32_t __sh_TCNT2; 98 extern u_int32_t __sh_TCR2; 99 extern u_int32_t __sh_TCPR2; 100 #endif /* SH3 && SH4 */ 101 #endif /* !_LOCORE */ 102 103 #endif /* !_SH3_TMUREG_H_ */ 104
Indexes created Fri Sep 26 20:09:58 GMT 2025