cgfourteenreg.h revision 1.1
1 /* $NetBSD: cgfourteenreg.h,v 1.1 1996/09/30 22:41:02 abrown Exp $ */ 2 3 /* 4 * Copyright (c) 1996 5 * The President and Fellows of Harvard College. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Harvard University and 18 * its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36 /* 37 * Register/dac/clut/cursor definitions for cgfourteen frame buffer 38 */ 39 40 /* Locations of control registers in cg14 register set */ 41 #define CG14_OFFSET_CURS 0x1000 42 #define CG14_OFFSET_DAC 0x2000 43 #define CG14_OFFSET_XLUT 0x3000 44 #define CG14_OFFSET_CLUT1 0x4000 45 #define CG14_OFFSET_CLUT2 0x5000 46 #define CG14_OFFSET_CLUT3 0x6000 47 #define CG14_OFFSET_CLUTINCR 0xf000 48 49 /* Main control register set */ 50 struct cg14ctl { 51 volatile u_int8_t ctl_mctl; /* main control register */ 52 #define CG14_MCTL_ENABLEINTR 0x80 /* interrupts */ 53 #define CG14_MCTL_ENABLEVID 0x40 /* enable video */ 54 #define CG14_MCTL_PIXMODE_MASK 0x30 55 #define CG14_MCTL_PIXMODE_8 0x00 /* data is 16 8-bit pixels */ 56 #define CG14_MCTL_PIXMODE_16 0x20 /* data is 8 16-bit pixels */ 57 #define CG14_MCTL_PIXMODE_32 0x30 /* data is 4 32-bit pixels */ 58 #define CG14_MCTL_PIXMODE_SHIFT 4 59 #define CG14_MCTL_TMR 0x0c 60 #define CG14_MCTL_ENABLETMR 0x02 61 #define CG14_MCTL_rev0RESET 0x01 62 #define CG14_MCTL_POWERCTL 0x01 63 64 volatile u_int8_t ctl_ppr; /* packed pixel register */ 65 volatile u_int8_t ctl_tmsr0; /* test status reg. 0 */ 66 volatile u_int8_t ctl_tmsr1; /* test status reg. 1 */ 67 volatile u_int8_t ctl_msr; /* master status register */ 68 volatile u_int8_t ctl_fsr; /* fault status register */ 69 volatile u_int8_t ctl_rsr; /* revision status register */ 70 #define CG14_RSR_REVMASK 0xf0 /* mask to get revision */ 71 #define CG14_RSR_IMPLMASK 0x0f /* mask to get impl. code */ 72 volatile u_int8_t ctl_ccr; /* clock control register */ 73 /* XXX etc. */ 74 }; 75 76 /* Hardware cursor map */ 77 #define CG14_CURS_SIZE 32 78 struct cg14curs { 79 volatile u_int32_t curs_plane0[CG14_CURS_SIZE]; /* plane 0 */ 80 volatile u_int32_t curs_plane1[CG14_CURS_SIZE]; 81 volatile u_int8_t curs_ctl; /* control register */ 82 #define CG14_CURS_ENABLE 0x4 83 #define CG14_CURS_DOUBLEBUFFER 0x2 /* use X-channel for curs */ 84 volatile u_int8_t pad0[3]; 85 volatile u_int16_t curs_x; /* x position */ 86 volatile u_int16_t curs_y; /* y position */ 87 volatile u_int32_t curs_color1; /* color register 1 */ 88 volatile u_int32_t curs_color2; /* color register 2 */ 89 volatile u_int32_t pad[444]; /* pad to 2KB boundary */ 90 volatile u_int32_t curs_plane0incr[CG14_CURS_SIZE]; /* autoincr */ 91 volatile u_int32_t curs_plane1incr[CG14_CURS_SIZE]; /* autoincr */ 92 }; 93 94 /* DAC */ 95 struct cg14dac { 96 volatile u_int8_t dac_addr; /* address register */ 97 volatile u_int8_t pad0[255]; 98 volatile u_int8_t dac_gammalut; /* gamma LUT */ 99 volatile u_int8_t pad1[255]; 100 volatile u_int8_t dac_regsel; /* register select */ 101 volatile u_int8_t pad2[255]; 102 volatile u_int8_t dac_mode; /* mode register */ 103 }; 104 105 #define CG14_CLUT_SIZE 256 106 107 /* XLUT registers */ 108 struct cg14xlut { 109 volatile u_int8_t xlut_lut[CG14_CLUT_SIZE]; /* the LUT */ 110 volatile u_int8_t xlut_lutd[CG14_CLUT_SIZE]; /* ??? */ 111 volatile u_int8_t pad0[0x600]; 112 volatile u_int8_t xlut_lutinc[CG14_CLUT_SIZE]; /* autoincrLUT*/ 113 volatile u_int8_t xlut_lutincd[CG14_CLUT_SIZE]; 114 }; 115 116 /* Color Look-Up Table (CLUT) */ 117 struct cg14clut { 118 volatile u_int32_t clut_lut[CG14_CLUT_SIZE]; /* the LUT */ 119 volatile u_int32_t clut_lutd[CG14_CLUT_SIZE]; /* ??? */ 120 volatile u_int32_t clut_lutinc[CG14_CLUT_SIZE]; /* autoincr */ 121 volatile u_int32_t clut_lutincd[CG14_CLUT_SIZE]; 122 }; 123
Indexes created Tue Sep 30 20:09:53 GMT 2025