esp_obio.c revision 1.1
1 /* $NetBSD: esp_obio.c,v 1.1 1998/08/29 20:49:37 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum; Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center; Paul Kranenburg. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #include <sys/types.h> 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/errno.h> 45 #include <sys/device.h> 46 #include <sys/buf.h> 47 48 #include <dev/scsipi/scsi_all.h> 49 #include <dev/scsipi/scsipi_all.h> 50 #include <dev/scsipi/scsiconf.h> 51 #include <dev/scsipi/scsi_message.h> 52 53 #include <machine/bus.h> 54 #include <machine/autoconf.h> 55 #include <machine/cpu.h> 56 57 #include <dev/ic/lsi64854reg.h> 58 #include <dev/ic/lsi64854var.h> 59 60 #include <dev/ic/ncr53c9xreg.h> 61 #include <dev/ic/ncr53c9xvar.h> 62 63 #include <dev/sbus/sbusvar.h> 64 65 struct esp_softc { 66 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 67 bus_space_tag_t sc_bustag; 68 bus_dma_tag_t sc_dmatag; 69 bus_space_handle_t sc_reg; /* the registers */ 70 struct lsi64854_softc *sc_dma; /* pointer to my dma */ 71 }; 72 73 74 void espattach_obio __P((struct device *, struct device *, void *)); 75 int espmatch_obio __P((struct device *, struct cfdata *, void *)); 76 77 /* Linkup to the rest of the kernel */ 78 struct cfattach esp_obio_ca = { 79 sizeof(struct esp_softc), espmatch_obio, espattach_obio 80 }; 81 82 static struct scsipi_adapter esp_obio_switch = { 83 ncr53c9x_scsi_cmd, 84 minphys, /* no max at this level; handled by DMA code */ 85 NULL, 86 NULL, 87 }; 88 89 static struct scsipi_device esp_obio_dev = { 90 NULL, /* Use default error handler */ 91 NULL, /* have a queue, served by this */ 92 NULL, /* have no async handler */ 93 NULL, /* Use default 'done' routine */ 94 }; 95 96 /* 97 * Functions and the switch for the MI code. 98 */ 99 static u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 100 static void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 101 static int esp_dma_isintr __P((struct ncr53c9x_softc *)); 102 static void esp_dma_reset __P((struct ncr53c9x_softc *)); 103 static int esp_dma_intr __P((struct ncr53c9x_softc *)); 104 static int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 105 size_t *, int, size_t *)); 106 static void esp_dma_go __P((struct ncr53c9x_softc *)); 107 static void esp_dma_stop __P((struct ncr53c9x_softc *)); 108 static int esp_dma_isactive __P((struct ncr53c9x_softc *)); 109 110 static struct ncr53c9x_glue esp_obio_glue = { 111 esp_read_reg, 112 esp_write_reg, 113 esp_dma_isintr, 114 esp_dma_reset, 115 esp_dma_intr, 116 esp_dma_setup, 117 esp_dma_go, 118 esp_dma_stop, 119 esp_dma_isactive, 120 NULL, /* gl_clear_latched_intr */ 121 }; 122 123 int 124 espmatch_obio(parent, cf, aux) 125 struct device *parent; 126 struct cfdata *cf; 127 void *aux; 128 { 129 union obio_attach_args *uoba = aux; 130 struct obio4_attach_args *oba; 131 132 if (uoba->uoba_isobio4 == 0) 133 return (0); 134 135 oba = &uoba->uoba_oba4; 136 return (bus_space_probe(oba->oba_bustag, 0, oba->oba_paddr, 137 1, /* probe size */ 138 0, /* offset */ 139 0, /* flags */ 140 NULL, NULL)); 141 } 142 143 void 144 espattach_obio(parent, self, aux) 145 struct device *parent, *self; 146 void *aux; 147 { 148 union obio_attach_args *uoba = aux; 149 struct obio4_attach_args *oba = &uoba->uoba_oba4; 150 struct esp_softc *esc = (void *)self; 151 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 152 bus_space_handle_t bh; 153 154 esc->sc_bustag = oba->oba_bustag; 155 esc->sc_dmatag = oba->oba_dmatag; 156 157 sc->sc_id = 7; 158 sc->sc_freq = 24000000; 159 160 /* 161 * Find the DMA by poking around the dma device structures 162 */ 163 esc->sc_dma = (struct lsi64854_softc *) 164 getdevunit("dma", sc->sc_dev.dv_unit); 165 166 /* 167 * and a back pointer to us, for DMA 168 */ 169 if (esc->sc_dma) 170 esc->sc_dma->sc_ncr53c9x = sc; 171 else { 172 printf("\n"); 173 panic("espattach: no dma found"); 174 } 175 176 if (obio_bus_map(oba->oba_bustag, oba->oba_paddr, 177 0, /* offset */ 178 16, /* size (of ncr53c9xreg) */ 179 BUS_SPACE_MAP_LINEAR, 180 0, &bh) != 0) { 181 printf("%s @ obio: cannot map registers\n", self->dv_xname); 182 return; 183 } 184 185 esc->sc_reg = bh; 186 187 if (oba->oba_bp != NULL && strcmp(oba->oba_bp->name, "esp") == 0 && 188 oba->oba_bp->val[0] == -1 && 189 oba->oba_bp->val[1] == sc->sc_dev.dv_unit) 190 bootpath_store(1, oba->oba_bp + 1); 191 192 193 /* 194 * Set up glue for MI code early; we use some of it here. 195 */ 196 sc->sc_glue = &esp_obio_glue; 197 198 /* gimme Mhz */ 199 sc->sc_freq /= 1000000; 200 201 /* 202 * XXX More of this should be in ncr53c9x_attach(), but 203 * XXX should we really poke around the chip that much in 204 * XXX the MI code? Think about this more... 205 */ 206 207 /* 208 * It is necessary to try to load the 2nd config register here, 209 * to find out what rev the esp chip is, else the ncr53c9x_reset 210 * will not set up the defaults correctly. 211 */ 212 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 213 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 214 sc->sc_cfg3 = NCRCFG3_CDB; 215 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 216 217 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 218 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 219 sc->sc_rev = NCR_VARIANT_ESP100; 220 } else { 221 sc->sc_cfg2 = NCRCFG2_SCSI2; 222 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 223 sc->sc_cfg3 = 0; 224 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 225 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 226 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 227 if (NCR_READ_REG(sc, NCR_CFG3) != 228 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 229 sc->sc_rev = NCR_VARIANT_ESP100A; 230 } else { 231 /* NCRCFG2_FE enables > 64K transfers */ 232 sc->sc_cfg2 |= NCRCFG2_FE; 233 sc->sc_cfg3 = 0; 234 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 235 sc->sc_rev = NCR_VARIANT_ESP200; 236 } 237 } 238 239 /* 240 * XXX minsync and maxxfer _should_ be set up in MI code, 241 * XXX but it appears to have some dependency on what sort 242 * XXX of DMA we're hooked up to, etc. 243 */ 244 245 /* 246 * This is the value used to start sync negotiations 247 * Note that the NCR register "SYNCTP" is programmed 248 * in "clocks per byte", and has a minimum value of 4. 249 * The SCSI period used in negotiation is one-fourth 250 * of the time (in nanoseconds) needed to transfer one byte. 251 * Since the chip's clock is given in MHz, we have the following 252 * formula: 4 * period = (1000 / freq) * 4 253 */ 254 sc->sc_minsync = 1000 / sc->sc_freq; 255 256 /* 257 * Alas, we must now modify the value a bit, because it's 258 * only valid when can switch on FASTCLK and FASTSCSI bits 259 * in config register 3... 260 */ 261 switch (sc->sc_rev) { 262 case NCR_VARIANT_ESP100: 263 sc->sc_maxxfer = 64 * 1024; 264 sc->sc_minsync = 0; /* No synch on old chip? */ 265 break; 266 267 case NCR_VARIANT_ESP100A: 268 sc->sc_maxxfer = 64 * 1024; 269 /* Min clocks/byte is 5 */ 270 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 271 break; 272 273 case NCR_VARIANT_ESP200: 274 sc->sc_maxxfer = 16 * 1024 * 1024; 275 /* XXX - do actually set FAST* bits */ 276 break; 277 } 278 279 /* Establish interrupt channel */ 280 bus_intr_establish(esc->sc_bustag, 281 oba->oba_pri, 0, 282 (int(*)__P((void*)))ncr53c9x_intr, sc); 283 284 /* register interrupt stats */ 285 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 286 287 /* Do the common parts of attachment. */ 288 ncr53c9x_attach(sc, &esp_obio_switch, &esp_obio_dev); 289 290 /* Turn on target selection using the `dma' method */ 291 ncr53c9x_dmaselect = 1; 292 293 bootpath_store(1, NULL); 294 } 295 296 /* 297 * Glue functions. 298 */ 299 300 u_char 301 esp_read_reg(sc, reg) 302 struct ncr53c9x_softc *sc; 303 int reg; 304 { 305 struct esp_softc *esc = (struct esp_softc *)sc; 306 307 return (bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg * 4)); 308 } 309 310 void 311 esp_write_reg(sc, reg, v) 312 struct ncr53c9x_softc *sc; 313 int reg; 314 u_char v; 315 { 316 struct esp_softc *esc = (struct esp_softc *)sc; 317 318 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg * 4, v); 319 } 320 321 int 322 esp_dma_isintr(sc) 323 struct ncr53c9x_softc *sc; 324 { 325 struct esp_softc *esc = (struct esp_softc *)sc; 326 327 return (DMA_ISINTR(esc->sc_dma)); 328 } 329 330 void 331 esp_dma_reset(sc) 332 struct ncr53c9x_softc *sc; 333 { 334 struct esp_softc *esc = (struct esp_softc *)sc; 335 336 DMA_RESET(esc->sc_dma); 337 } 338 339 int 340 esp_dma_intr(sc) 341 struct ncr53c9x_softc *sc; 342 { 343 struct esp_softc *esc = (struct esp_softc *)sc; 344 345 return (DMA_INTR(esc->sc_dma)); 346 } 347 348 int 349 esp_dma_setup(sc, addr, len, datain, dmasize) 350 struct ncr53c9x_softc *sc; 351 caddr_t *addr; 352 size_t *len; 353 int datain; 354 size_t *dmasize; 355 { 356 struct esp_softc *esc = (struct esp_softc *)sc; 357 358 return (DMA_SETUP(esc->sc_dma, addr, len, datain, dmasize)); 359 } 360 361 void 362 esp_dma_go(sc) 363 struct ncr53c9x_softc *sc; 364 { 365 struct esp_softc *esc = (struct esp_softc *)sc; 366 367 DMA_GO(esc->sc_dma); 368 } 369 370 void 371 esp_dma_stop(sc) 372 struct ncr53c9x_softc *sc; 373 { 374 struct esp_softc *esc = (struct esp_softc *)sc; 375 u_int32_t csr; 376 377 csr = L64854_GCSR(esc->sc_dma); 378 csr &= ~D_EN_DMA; 379 L64854_SCSR(esc->sc_dma, csr); 380 } 381 382 int 383 esp_dma_isactive(sc) 384 struct ncr53c9x_softc *sc; 385 { 386 struct esp_softc *esc = (struct esp_softc *)sc; 387 388 return (DMA_ISACTIVE(esc->sc_dma)); 389 } 390
Indexes created Tue Sep 30 17:09:57 GMT 2025