esp_obio.c revision 1.10
1 /* $NetBSD: esp_obio.c,v 1.10 2001/04/25 17:53:22 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum; Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center; Paul Kranenburg. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #include <sys/types.h> 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/errno.h> 45 #include <sys/device.h> 46 #include <sys/buf.h> 47 48 #include <dev/scsipi/scsi_all.h> 49 #include <dev/scsipi/scsipi_all.h> 50 #include <dev/scsipi/scsiconf.h> 51 #include <dev/scsipi/scsi_message.h> 52 53 #include <machine/bus.h> 54 #include <machine/autoconf.h> 55 #include <machine/intr.h> 56 57 #include <dev/ic/lsi64854reg.h> 58 #include <dev/ic/lsi64854var.h> 59 60 #include <dev/ic/ncr53c9xreg.h> 61 #include <dev/ic/ncr53c9xvar.h> 62 63 #include <dev/sbus/sbusvar.h> 64 65 struct esp_softc { 66 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 67 bus_space_tag_t sc_bustag; 68 bus_dma_tag_t sc_dmatag; 69 bus_space_handle_t sc_reg; /* the registers */ 70 struct lsi64854_softc *sc_dma; /* pointer to my dma */ 71 }; 72 73 74 void espattach_obio __P((struct device *, struct device *, void *)); 75 int espmatch_obio __P((struct device *, struct cfdata *, void *)); 76 77 /* Linkup to the rest of the kernel */ 78 struct cfattach esp_obio_ca = { 79 sizeof(struct esp_softc), espmatch_obio, espattach_obio 80 }; 81 82 /* 83 * Functions and the switch for the MI code. 84 */ 85 static u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 86 static void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 87 static int esp_dma_isintr __P((struct ncr53c9x_softc *)); 88 static void esp_dma_reset __P((struct ncr53c9x_softc *)); 89 static int esp_dma_intr __P((struct ncr53c9x_softc *)); 90 static int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 91 size_t *, int, size_t *)); 92 static void esp_dma_go __P((struct ncr53c9x_softc *)); 93 static void esp_dma_stop __P((struct ncr53c9x_softc *)); 94 static int esp_dma_isactive __P((struct ncr53c9x_softc *)); 95 96 static struct ncr53c9x_glue esp_obio_glue = { 97 esp_read_reg, 98 esp_write_reg, 99 esp_dma_isintr, 100 esp_dma_reset, 101 esp_dma_intr, 102 esp_dma_setup, 103 esp_dma_go, 104 esp_dma_stop, 105 esp_dma_isactive, 106 NULL, /* gl_clear_latched_intr */ 107 }; 108 109 int 110 espmatch_obio(parent, cf, aux) 111 struct device *parent; 112 struct cfdata *cf; 113 void *aux; 114 { 115 union obio_attach_args *uoba = aux; 116 struct obio4_attach_args *oba; 117 118 if (uoba->uoba_isobio4 == 0) 119 return (0); 120 121 oba = &uoba->uoba_oba4; 122 return (bus_space_probe(oba->oba_bustag, 0, oba->oba_paddr, 123 1, /* probe size */ 124 0, /* offset */ 125 0, /* flags */ 126 NULL, NULL)); 127 } 128 129 void 130 espattach_obio(parent, self, aux) 131 struct device *parent, *self; 132 void *aux; 133 { 134 union obio_attach_args *uoba = aux; 135 struct obio4_attach_args *oba = &uoba->uoba_oba4; 136 struct esp_softc *esc = (void *)self; 137 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 138 139 esc->sc_bustag = oba->oba_bustag; 140 esc->sc_dmatag = oba->oba_dmatag; 141 142 sc->sc_id = 7; 143 sc->sc_freq = 24000000; 144 145 /* 146 * Find the DMA by poking around the dma device structures 147 */ 148 esc->sc_dma = (struct lsi64854_softc *) 149 getdevunit("dma", sc->sc_dev.dv_unit); 150 151 /* 152 * and a back pointer to us, for DMA 153 */ 154 if (esc->sc_dma) 155 esc->sc_dma->sc_client = sc; 156 else { 157 printf("\n"); 158 panic("espattach: no dma found"); 159 } 160 161 if (obio_bus_map(oba->oba_bustag, oba->oba_paddr, 162 0, /* offset */ 163 16, /* size (of ncr53c9xreg) */ 164 BUS_SPACE_MAP_LINEAR, 165 0, &esc->sc_reg) != 0) { 166 printf("%s @ obio: cannot map registers\n", self->dv_xname); 167 return; 168 } 169 170 /* 171 * Set up glue for MI code early; we use some of it here. 172 */ 173 sc->sc_glue = &esp_obio_glue; 174 175 /* gimme Mhz */ 176 sc->sc_freq /= 1000000; 177 178 /* 179 * XXX More of this should be in ncr53c9x_attach(), but 180 * XXX should we really poke around the chip that much in 181 * XXX the MI code? Think about this more... 182 */ 183 184 /* 185 * It is necessary to try to load the 2nd config register here, 186 * to find out what rev the esp chip is, else the ncr53c9x_reset 187 * will not set up the defaults correctly. 188 */ 189 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 190 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 191 sc->sc_cfg3 = NCRCFG3_CDB; 192 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 193 194 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 195 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 196 sc->sc_rev = NCR_VARIANT_ESP100; 197 } else { 198 sc->sc_cfg2 = NCRCFG2_SCSI2; 199 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 200 sc->sc_cfg3 = 0; 201 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 202 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 203 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 204 if (NCR_READ_REG(sc, NCR_CFG3) != 205 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 206 sc->sc_rev = NCR_VARIANT_ESP100A; 207 } else { 208 /* NCRCFG2_FE enables > 64K transfers */ 209 sc->sc_cfg2 |= NCRCFG2_FE; 210 sc->sc_cfg3 = 0; 211 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 212 sc->sc_rev = NCR_VARIANT_ESP200; 213 } 214 } 215 216 /* 217 * XXX minsync and maxxfer _should_ be set up in MI code, 218 * XXX but it appears to have some dependency on what sort 219 * XXX of DMA we're hooked up to, etc. 220 */ 221 222 /* 223 * This is the value used to start sync negotiations 224 * Note that the NCR register "SYNCTP" is programmed 225 * in "clocks per byte", and has a minimum value of 4. 226 * The SCSI period used in negotiation is one-fourth 227 * of the time (in nanoseconds) needed to transfer one byte. 228 * Since the chip's clock is given in MHz, we have the following 229 * formula: 4 * period = (1000 / freq) * 4 230 */ 231 sc->sc_minsync = 1000 / sc->sc_freq; 232 233 /* 234 * Alas, we must now modify the value a bit, because it's 235 * only valid when can switch on FASTCLK and FASTSCSI bits 236 * in config register 3... 237 */ 238 switch (sc->sc_rev) { 239 case NCR_VARIANT_ESP100: 240 sc->sc_maxxfer = 64 * 1024; 241 sc->sc_minsync = 0; /* No synch on old chip? */ 242 break; 243 244 case NCR_VARIANT_ESP100A: 245 sc->sc_maxxfer = 64 * 1024; 246 /* Min clocks/byte is 5 */ 247 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 248 break; 249 250 case NCR_VARIANT_ESP200: 251 sc->sc_maxxfer = 16 * 1024 * 1024; 252 /* XXX - do actually set FAST* bits */ 253 break; 254 } 255 256 /* Establish interrupt channel */ 257 bus_intr_establish(esc->sc_bustag, oba->oba_pri, IPL_BIO, 0, 258 ncr53c9x_intr, sc); 259 260 /* register interrupt stats */ 261 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 262 sc->sc_dev.dv_xname, "intr"); 263 264 /* Do the common parts of attachment. */ 265 sc->sc_adapter.adapt_minphys = minphys; 266 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 267 ncr53c9x_attach(sc); 268 sc->sc_features |= NCR_F_DMASELECT; 269 } 270 271 /* 272 * Glue functions. 273 */ 274 275 u_char 276 esp_read_reg(sc, reg) 277 struct ncr53c9x_softc *sc; 278 int reg; 279 { 280 struct esp_softc *esc = (struct esp_softc *)sc; 281 282 return (bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg * 4)); 283 } 284 285 void 286 esp_write_reg(sc, reg, v) 287 struct ncr53c9x_softc *sc; 288 int reg; 289 u_char v; 290 { 291 struct esp_softc *esc = (struct esp_softc *)sc; 292 293 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg * 4, v); 294 } 295 296 int 297 esp_dma_isintr(sc) 298 struct ncr53c9x_softc *sc; 299 { 300 struct esp_softc *esc = (struct esp_softc *)sc; 301 302 return (DMA_ISINTR(esc->sc_dma)); 303 } 304 305 void 306 esp_dma_reset(sc) 307 struct ncr53c9x_softc *sc; 308 { 309 struct esp_softc *esc = (struct esp_softc *)sc; 310 311 DMA_RESET(esc->sc_dma); 312 } 313 314 int 315 esp_dma_intr(sc) 316 struct ncr53c9x_softc *sc; 317 { 318 struct esp_softc *esc = (struct esp_softc *)sc; 319 320 return (DMA_INTR(esc->sc_dma)); 321 } 322 323 int 324 esp_dma_setup(sc, addr, len, datain, dmasize) 325 struct ncr53c9x_softc *sc; 326 caddr_t *addr; 327 size_t *len; 328 int datain; 329 size_t *dmasize; 330 { 331 struct esp_softc *esc = (struct esp_softc *)sc; 332 333 return (DMA_SETUP(esc->sc_dma, addr, len, datain, dmasize)); 334 } 335 336 void 337 esp_dma_go(sc) 338 struct ncr53c9x_softc *sc; 339 { 340 struct esp_softc *esc = (struct esp_softc *)sc; 341 342 DMA_GO(esc->sc_dma); 343 } 344 345 void 346 esp_dma_stop(sc) 347 struct ncr53c9x_softc *sc; 348 { 349 struct esp_softc *esc = (struct esp_softc *)sc; 350 u_int32_t csr; 351 352 csr = L64854_GCSR(esc->sc_dma); 353 csr &= ~D_EN_DMA; 354 L64854_SCSR(esc->sc_dma, csr); 355 } 356 357 int 358 esp_dma_isactive(sc) 359 struct ncr53c9x_softc *sc; 360 { 361 struct esp_softc *esc = (struct esp_softc *)sc; 362 363 return (DMA_ISACTIVE(esc->sc_dma)); 364 } 365
Indexes created Mon Sep 29 21:09:56 GMT 2025