esp_obio.c revision 1.15
1 /* $NetBSD: esp_obio.c,v 1.15 2002/12/10 13:44:49 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum; Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center; Paul Kranenburg. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #include <sys/types.h> 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/errno.h> 45 #include <sys/device.h> 46 #include <sys/buf.h> 47 48 #include <dev/scsipi/scsi_all.h> 49 #include <dev/scsipi/scsipi_all.h> 50 #include <dev/scsipi/scsiconf.h> 51 #include <dev/scsipi/scsi_message.h> 52 53 #include <machine/bus.h> 54 #include <machine/autoconf.h> 55 #include <machine/intr.h> 56 57 #include <dev/ic/lsi64854reg.h> 58 #include <dev/ic/lsi64854var.h> 59 60 #include <dev/ic/ncr53c9xreg.h> 61 #include <dev/ic/ncr53c9xvar.h> 62 63 #include <dev/sbus/sbusvar.h> 64 65 struct esp_softc { 66 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 67 bus_space_tag_t sc_bustag; 68 bus_dma_tag_t sc_dmatag; 69 bus_space_handle_t sc_reg; /* the registers */ 70 struct lsi64854_softc *sc_dma; /* pointer to my dma */ 71 }; 72 73 74 void espattach_obio __P((struct device *, struct device *, void *)); 75 int espmatch_obio __P((struct device *, struct cfdata *, void *)); 76 77 /* Linkup to the rest of the kernel */ 78 CFATTACH_DECL(esp_obio, sizeof(struct esp_softc), 79 espmatch_obio, espattach_obio, NULL, NULL); 80 81 /* 82 * Functions and the switch for the MI code. 83 */ 84 static u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 85 static void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 86 static int esp_dma_isintr __P((struct ncr53c9x_softc *)); 87 static void esp_dma_reset __P((struct ncr53c9x_softc *)); 88 static int esp_dma_intr __P((struct ncr53c9x_softc *)); 89 static int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 90 size_t *, int, size_t *)); 91 static void esp_dma_go __P((struct ncr53c9x_softc *)); 92 static void esp_dma_stop __P((struct ncr53c9x_softc *)); 93 static int esp_dma_isactive __P((struct ncr53c9x_softc *)); 94 95 static struct ncr53c9x_glue esp_obio_glue = { 96 esp_read_reg, 97 esp_write_reg, 98 esp_dma_isintr, 99 esp_dma_reset, 100 esp_dma_intr, 101 esp_dma_setup, 102 esp_dma_go, 103 esp_dma_stop, 104 esp_dma_isactive, 105 NULL, /* gl_clear_latched_intr */ 106 }; 107 108 int 109 espmatch_obio(parent, cf, aux) 110 struct device *parent; 111 struct cfdata *cf; 112 void *aux; 113 { 114 union obio_attach_args *uoba = aux; 115 struct obio4_attach_args *oba; 116 117 if (uoba->uoba_isobio4 == 0) 118 return (0); 119 120 oba = &uoba->uoba_oba4; 121 return (bus_space_probe(oba->oba_bustag, oba->oba_paddr, 122 1, /* probe size */ 123 0, /* offset */ 124 0, /* flags */ 125 NULL, NULL)); 126 } 127 128 void 129 espattach_obio(parent, self, aux) 130 struct device *parent, *self; 131 void *aux; 132 { 133 union obio_attach_args *uoba = aux; 134 struct obio4_attach_args *oba = &uoba->uoba_oba4; 135 struct esp_softc *esc = (void *)self; 136 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 137 138 esc->sc_bustag = oba->oba_bustag; 139 esc->sc_dmatag = oba->oba_dmatag; 140 141 sc->sc_id = 7; 142 sc->sc_freq = 24000000; 143 144 /* 145 * Find the DMA by poking around the dma device structures 146 */ 147 esc->sc_dma = (struct lsi64854_softc *) 148 getdevunit("dma", sc->sc_dev.dv_unit); 149 150 /* 151 * and a back pointer to us, for DMA 152 */ 153 if (esc->sc_dma) 154 esc->sc_dma->sc_client = sc; 155 else { 156 printf("\n"); 157 panic("espattach: no dma found"); 158 } 159 160 if (bus_space_map(oba->oba_bustag, oba->oba_paddr, 161 16, /* size (of ncr53c9xreg) */ 162 BUS_SPACE_MAP_LINEAR, 163 &esc->sc_reg) != 0) { 164 printf("%s @ obio: cannot map registers\n", self->dv_xname); 165 return; 166 } 167 168 /* 169 * Set up glue for MI code early; we use some of it here. 170 */ 171 sc->sc_glue = &esp_obio_glue; 172 173 /* gimme Mhz */ 174 sc->sc_freq /= 1000000; 175 176 /* 177 * XXX More of this should be in ncr53c9x_attach(), but 178 * XXX should we really poke around the chip that much in 179 * XXX the MI code? Think about this more... 180 */ 181 182 /* 183 * It is necessary to try to load the 2nd config register here, 184 * to find out what rev the esp chip is, else the ncr53c9x_reset 185 * will not set up the defaults correctly. 186 */ 187 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 188 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 189 sc->sc_cfg3 = NCRCFG3_CDB; 190 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 191 192 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 193 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 194 sc->sc_rev = NCR_VARIANT_ESP100; 195 } else { 196 sc->sc_cfg2 = NCRCFG2_SCSI2; 197 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 198 sc->sc_cfg3 = 0; 199 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 200 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 201 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 202 if (NCR_READ_REG(sc, NCR_CFG3) != 203 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 204 sc->sc_rev = NCR_VARIANT_ESP100A; 205 } else { 206 /* NCRCFG2_FE enables > 64K transfers */ 207 sc->sc_cfg2 |= NCRCFG2_FE; 208 sc->sc_cfg3 = 0; 209 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 210 sc->sc_rev = NCR_VARIANT_ESP200; 211 } 212 } 213 214 /* 215 * XXX minsync and maxxfer _should_ be set up in MI code, 216 * XXX but it appears to have some dependency on what sort 217 * XXX of DMA we're hooked up to, etc. 218 */ 219 220 /* 221 * This is the value used to start sync negotiations 222 * Note that the NCR register "SYNCTP" is programmed 223 * in "clocks per byte", and has a minimum value of 4. 224 * The SCSI period used in negotiation is one-fourth 225 * of the time (in nanoseconds) needed to transfer one byte. 226 * Since the chip's clock is given in MHz, we have the following 227 * formula: 4 * period = (1000 / freq) * 4 228 */ 229 sc->sc_minsync = 1000 / sc->sc_freq; 230 231 /* 232 * Alas, we must now modify the value a bit, because it's 233 * only valid when can switch on FASTCLK and FASTSCSI bits 234 * in config register 3... 235 */ 236 switch (sc->sc_rev) { 237 case NCR_VARIANT_ESP100: 238 sc->sc_maxxfer = 64 * 1024; 239 sc->sc_minsync = 0; /* No synch on old chip? */ 240 break; 241 242 case NCR_VARIANT_ESP100A: 243 sc->sc_maxxfer = 64 * 1024; 244 /* Min clocks/byte is 5 */ 245 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 246 break; 247 248 case NCR_VARIANT_ESP200: 249 sc->sc_maxxfer = 16 * 1024 * 1024; 250 /* XXX - do actually set FAST* bits */ 251 break; 252 } 253 254 /* Establish interrupt channel */ 255 bus_intr_establish(esc->sc_bustag, oba->oba_pri, IPL_BIO, 256 ncr53c9x_intr, sc); 257 258 /* register interrupt stats */ 259 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 260 sc->sc_dev.dv_xname, "intr"); 261 262 /* Do the common parts of attachment. */ 263 sc->sc_adapter.adapt_minphys = minphys; 264 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 265 ncr53c9x_attach(sc); 266 sc->sc_features |= NCR_F_DMASELECT; 267 } 268 269 /* 270 * Glue functions. 271 */ 272 273 u_char 274 esp_read_reg(sc, reg) 275 struct ncr53c9x_softc *sc; 276 int reg; 277 { 278 struct esp_softc *esc = (struct esp_softc *)sc; 279 280 return (bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg * 4)); 281 } 282 283 void 284 esp_write_reg(sc, reg, v) 285 struct ncr53c9x_softc *sc; 286 int reg; 287 u_char v; 288 { 289 struct esp_softc *esc = (struct esp_softc *)sc; 290 291 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg * 4, v); 292 } 293 294 int 295 esp_dma_isintr(sc) 296 struct ncr53c9x_softc *sc; 297 { 298 struct esp_softc *esc = (struct esp_softc *)sc; 299 300 return (DMA_ISINTR(esc->sc_dma)); 301 } 302 303 void 304 esp_dma_reset(sc) 305 struct ncr53c9x_softc *sc; 306 { 307 struct esp_softc *esc = (struct esp_softc *)sc; 308 309 DMA_RESET(esc->sc_dma); 310 } 311 312 int 313 esp_dma_intr(sc) 314 struct ncr53c9x_softc *sc; 315 { 316 struct esp_softc *esc = (struct esp_softc *)sc; 317 318 return (DMA_INTR(esc->sc_dma)); 319 } 320 321 int 322 esp_dma_setup(sc, addr, len, datain, dmasize) 323 struct ncr53c9x_softc *sc; 324 caddr_t *addr; 325 size_t *len; 326 int datain; 327 size_t *dmasize; 328 { 329 struct esp_softc *esc = (struct esp_softc *)sc; 330 331 return (DMA_SETUP(esc->sc_dma, addr, len, datain, dmasize)); 332 } 333 334 void 335 esp_dma_go(sc) 336 struct ncr53c9x_softc *sc; 337 { 338 struct esp_softc *esc = (struct esp_softc *)sc; 339 340 DMA_GO(esc->sc_dma); 341 } 342 343 void 344 esp_dma_stop(sc) 345 struct ncr53c9x_softc *sc; 346 { 347 struct esp_softc *esc = (struct esp_softc *)sc; 348 u_int32_t csr; 349 350 csr = L64854_GCSR(esc->sc_dma); 351 csr &= ~D_EN_DMA; 352 L64854_SCSR(esc->sc_dma, csr); 353 } 354 355 int 356 esp_dma_isactive(sc) 357 struct ncr53c9x_softc *sc; 358 { 359 struct esp_softc *esc = (struct esp_softc *)sc; 360 361 return (DMA_ISACTIVE(esc->sc_dma)); 362 } 363
Indexes created Tue Sep 30 07:10:03 GMT 2025