esp_obio.c revision 1.2
1 /* $NetBSD: esp_obio.c,v 1.2 1998/08/29 21:43:46 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum; Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center; Paul Kranenburg. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #include <sys/types.h> 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/errno.h> 45 #include <sys/device.h> 46 #include <sys/buf.h> 47 48 #include <dev/scsipi/scsi_all.h> 49 #include <dev/scsipi/scsipi_all.h> 50 #include <dev/scsipi/scsiconf.h> 51 #include <dev/scsipi/scsi_message.h> 52 53 #include <machine/bus.h> 54 #include <machine/autoconf.h> 55 #include <machine/cpu.h> 56 57 #include <dev/ic/lsi64854reg.h> 58 #include <dev/ic/lsi64854var.h> 59 60 #include <dev/ic/ncr53c9xreg.h> 61 #include <dev/ic/ncr53c9xvar.h> 62 63 #include <dev/sbus/sbusvar.h> 64 65 struct esp_softc { 66 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 67 bus_space_tag_t sc_bustag; 68 bus_dma_tag_t sc_dmatag; 69 bus_space_handle_t sc_reg; /* the registers */ 70 struct lsi64854_softc *sc_dma; /* pointer to my dma */ 71 }; 72 73 74 void espattach_obio __P((struct device *, struct device *, void *)); 75 int espmatch_obio __P((struct device *, struct cfdata *, void *)); 76 77 /* Linkup to the rest of the kernel */ 78 struct cfattach esp_obio_ca = { 79 sizeof(struct esp_softc), espmatch_obio, espattach_obio 80 }; 81 82 static struct scsipi_adapter esp_obio_switch = { 83 ncr53c9x_scsi_cmd, 84 minphys, /* no max at this level; handled by DMA code */ 85 NULL, 86 NULL, 87 }; 88 89 static struct scsipi_device esp_obio_dev = { 90 NULL, /* Use default error handler */ 91 NULL, /* have a queue, served by this */ 92 NULL, /* have no async handler */ 93 NULL, /* Use default 'done' routine */ 94 }; 95 96 /* 97 * Functions and the switch for the MI code. 98 */ 99 static u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 100 static void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 101 static int esp_dma_isintr __P((struct ncr53c9x_softc *)); 102 static void esp_dma_reset __P((struct ncr53c9x_softc *)); 103 static int esp_dma_intr __P((struct ncr53c9x_softc *)); 104 static int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 105 size_t *, int, size_t *)); 106 static void esp_dma_go __P((struct ncr53c9x_softc *)); 107 static void esp_dma_stop __P((struct ncr53c9x_softc *)); 108 static int esp_dma_isactive __P((struct ncr53c9x_softc *)); 109 110 static struct ncr53c9x_glue esp_obio_glue = { 111 esp_read_reg, 112 esp_write_reg, 113 esp_dma_isintr, 114 esp_dma_reset, 115 esp_dma_intr, 116 esp_dma_setup, 117 esp_dma_go, 118 esp_dma_stop, 119 esp_dma_isactive, 120 NULL, /* gl_clear_latched_intr */ 121 }; 122 123 int 124 espmatch_obio(parent, cf, aux) 125 struct device *parent; 126 struct cfdata *cf; 127 void *aux; 128 { 129 union obio_attach_args *uoba = aux; 130 struct obio4_attach_args *oba; 131 132 if (uoba->uoba_isobio4 == 0) 133 return (0); 134 135 oba = &uoba->uoba_oba4; 136 return (bus_space_probe(oba->oba_bustag, 0, oba->oba_paddr, 137 1, /* probe size */ 138 0, /* offset */ 139 0, /* flags */ 140 NULL, NULL)); 141 } 142 143 void 144 espattach_obio(parent, self, aux) 145 struct device *parent, *self; 146 void *aux; 147 { 148 union obio_attach_args *uoba = aux; 149 struct obio4_attach_args *oba = &uoba->uoba_oba4; 150 struct esp_softc *esc = (void *)self; 151 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 152 153 esc->sc_bustag = oba->oba_bustag; 154 esc->sc_dmatag = oba->oba_dmatag; 155 156 sc->sc_id = 7; 157 sc->sc_freq = 24000000; 158 159 /* 160 * Find the DMA by poking around the dma device structures 161 */ 162 esc->sc_dma = (struct lsi64854_softc *) 163 getdevunit("dma", sc->sc_dev.dv_unit); 164 165 /* 166 * and a back pointer to us, for DMA 167 */ 168 if (esc->sc_dma) 169 esc->sc_dma->sc_client = sc; 170 else { 171 printf("\n"); 172 panic("espattach: no dma found"); 173 } 174 175 if (obio_bus_map(oba->oba_bustag, oba->oba_paddr, 176 0, /* offset */ 177 16, /* size (of ncr53c9xreg) */ 178 BUS_SPACE_MAP_LINEAR, 179 0, &esc->sc_reg) != 0) { 180 printf("%s @ obio: cannot map registers\n", self->dv_xname); 181 return; 182 } 183 184 if (oba->oba_bp != NULL && strcmp(oba->oba_bp->name, "esp") == 0 && 185 oba->oba_bp->val[0] == -1 && 186 oba->oba_bp->val[1] == sc->sc_dev.dv_unit) 187 bootpath_store(1, oba->oba_bp + 1); 188 189 190 /* 191 * Set up glue for MI code early; we use some of it here. 192 */ 193 sc->sc_glue = &esp_obio_glue; 194 195 /* gimme Mhz */ 196 sc->sc_freq /= 1000000; 197 198 /* 199 * XXX More of this should be in ncr53c9x_attach(), but 200 * XXX should we really poke around the chip that much in 201 * XXX the MI code? Think about this more... 202 */ 203 204 /* 205 * It is necessary to try to load the 2nd config register here, 206 * to find out what rev the esp chip is, else the ncr53c9x_reset 207 * will not set up the defaults correctly. 208 */ 209 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 210 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 211 sc->sc_cfg3 = NCRCFG3_CDB; 212 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 213 214 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 215 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 216 sc->sc_rev = NCR_VARIANT_ESP100; 217 } else { 218 sc->sc_cfg2 = NCRCFG2_SCSI2; 219 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 220 sc->sc_cfg3 = 0; 221 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 222 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 223 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 224 if (NCR_READ_REG(sc, NCR_CFG3) != 225 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 226 sc->sc_rev = NCR_VARIANT_ESP100A; 227 } else { 228 /* NCRCFG2_FE enables > 64K transfers */ 229 sc->sc_cfg2 |= NCRCFG2_FE; 230 sc->sc_cfg3 = 0; 231 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 232 sc->sc_rev = NCR_VARIANT_ESP200; 233 } 234 } 235 236 /* 237 * XXX minsync and maxxfer _should_ be set up in MI code, 238 * XXX but it appears to have some dependency on what sort 239 * XXX of DMA we're hooked up to, etc. 240 */ 241 242 /* 243 * This is the value used to start sync negotiations 244 * Note that the NCR register "SYNCTP" is programmed 245 * in "clocks per byte", and has a minimum value of 4. 246 * The SCSI period used in negotiation is one-fourth 247 * of the time (in nanoseconds) needed to transfer one byte. 248 * Since the chip's clock is given in MHz, we have the following 249 * formula: 4 * period = (1000 / freq) * 4 250 */ 251 sc->sc_minsync = 1000 / sc->sc_freq; 252 253 /* 254 * Alas, we must now modify the value a bit, because it's 255 * only valid when can switch on FASTCLK and FASTSCSI bits 256 * in config register 3... 257 */ 258 switch (sc->sc_rev) { 259 case NCR_VARIANT_ESP100: 260 sc->sc_maxxfer = 64 * 1024; 261 sc->sc_minsync = 0; /* No synch on old chip? */ 262 break; 263 264 case NCR_VARIANT_ESP100A: 265 sc->sc_maxxfer = 64 * 1024; 266 /* Min clocks/byte is 5 */ 267 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 268 break; 269 270 case NCR_VARIANT_ESP200: 271 sc->sc_maxxfer = 16 * 1024 * 1024; 272 /* XXX - do actually set FAST* bits */ 273 break; 274 } 275 276 /* Establish interrupt channel */ 277 bus_intr_establish(esc->sc_bustag, 278 oba->oba_pri, 0, 279 (int(*)__P((void*)))ncr53c9x_intr, sc); 280 281 /* register interrupt stats */ 282 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 283 284 /* Do the common parts of attachment. */ 285 ncr53c9x_attach(sc, &esp_obio_switch, &esp_obio_dev); 286 287 /* Turn on target selection using the `dma' method */ 288 ncr53c9x_dmaselect = 1; 289 290 bootpath_store(1, NULL); 291 } 292 293 /* 294 * Glue functions. 295 */ 296 297 u_char 298 esp_read_reg(sc, reg) 299 struct ncr53c9x_softc *sc; 300 int reg; 301 { 302 struct esp_softc *esc = (struct esp_softc *)sc; 303 304 return (bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg * 4)); 305 } 306 307 void 308 esp_write_reg(sc, reg, v) 309 struct ncr53c9x_softc *sc; 310 int reg; 311 u_char v; 312 { 313 struct esp_softc *esc = (struct esp_softc *)sc; 314 315 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg * 4, v); 316 } 317 318 int 319 esp_dma_isintr(sc) 320 struct ncr53c9x_softc *sc; 321 { 322 struct esp_softc *esc = (struct esp_softc *)sc; 323 324 return (DMA_ISINTR(esc->sc_dma)); 325 } 326 327 void 328 esp_dma_reset(sc) 329 struct ncr53c9x_softc *sc; 330 { 331 struct esp_softc *esc = (struct esp_softc *)sc; 332 333 DMA_RESET(esc->sc_dma); 334 } 335 336 int 337 esp_dma_intr(sc) 338 struct ncr53c9x_softc *sc; 339 { 340 struct esp_softc *esc = (struct esp_softc *)sc; 341 342 return (DMA_INTR(esc->sc_dma)); 343 } 344 345 int 346 esp_dma_setup(sc, addr, len, datain, dmasize) 347 struct ncr53c9x_softc *sc; 348 caddr_t *addr; 349 size_t *len; 350 int datain; 351 size_t *dmasize; 352 { 353 struct esp_softc *esc = (struct esp_softc *)sc; 354 355 return (DMA_SETUP(esc->sc_dma, addr, len, datain, dmasize)); 356 } 357 358 void 359 esp_dma_go(sc) 360 struct ncr53c9x_softc *sc; 361 { 362 struct esp_softc *esc = (struct esp_softc *)sc; 363 364 DMA_GO(esc->sc_dma); 365 } 366 367 void 368 esp_dma_stop(sc) 369 struct ncr53c9x_softc *sc; 370 { 371 struct esp_softc *esc = (struct esp_softc *)sc; 372 u_int32_t csr; 373 374 csr = L64854_GCSR(esc->sc_dma); 375 csr &= ~D_EN_DMA; 376 L64854_SCSR(esc->sc_dma, csr); 377 } 378 379 int 380 esp_dma_isactive(sc) 381 struct ncr53c9x_softc *sc; 382 { 383 struct esp_softc *esc = (struct esp_softc *)sc; 384 385 return (DMA_ISACTIVE(esc->sc_dma)); 386 } 387
Indexes created Tue Sep 30 11:09:46 GMT 2025