esp_obio.c revision 1.22
1 /* $NetBSD: esp_obio.c,v 1.22 2008/04/13 04:55:53 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum; Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center; Paul Kranenburg. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: esp_obio.c,v 1.22 2008/04/13 04:55:53 tsutsui Exp $"); 42 43 #include <sys/types.h> 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/kernel.h> 47 #include <sys/errno.h> 48 #include <sys/device.h> 49 #include <sys/buf.h> 50 51 #include <dev/scsipi/scsi_all.h> 52 #include <dev/scsipi/scsipi_all.h> 53 #include <dev/scsipi/scsiconf.h> 54 #include <dev/scsipi/scsi_message.h> 55 56 #include <machine/bus.h> 57 #include <machine/autoconf.h> 58 #include <machine/intr.h> 59 60 #include <dev/ic/lsi64854reg.h> 61 #include <dev/ic/lsi64854var.h> 62 63 #include <dev/ic/ncr53c9xreg.h> 64 #include <dev/ic/ncr53c9xvar.h> 65 66 #include <dev/sbus/sbusvar.h> 67 68 struct esp_softc { 69 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 70 bus_space_tag_t sc_bustag; 71 bus_dma_tag_t sc_dmatag; 72 bus_space_handle_t sc_reg; /* the registers */ 73 struct lsi64854_softc *sc_dma; /* pointer to my dma */ 74 }; 75 76 77 int espmatch_obio(device_t, cfdata_t, void *); 78 void espattach_obio(device_t, device_t, void *); 79 80 /* Linkup to the rest of the kernel */ 81 CFATTACH_DECL_NEW(esp_obio, sizeof(struct esp_softc), 82 espmatch_obio, espattach_obio, NULL, NULL); 83 84 /* 85 * Functions and the switch for the MI code. 86 */ 87 static uint8_t esp_read_reg(struct ncr53c9x_softc *, int); 88 static void esp_write_reg(struct ncr53c9x_softc *, int, uint8_t); 89 static int esp_dma_isintr(struct ncr53c9x_softc *); 90 static void esp_dma_reset(struct ncr53c9x_softc *); 91 static int esp_dma_intr(struct ncr53c9x_softc *); 92 static int esp_dma_setup(struct ncr53c9x_softc *, uint8_t **, 93 size_t *, int, size_t *); 94 static void esp_dma_go(struct ncr53c9x_softc *); 95 static void esp_dma_stop(struct ncr53c9x_softc *); 96 static int esp_dma_isactive(struct ncr53c9x_softc *); 97 98 static struct ncr53c9x_glue esp_obio_glue = { 99 esp_read_reg, 100 esp_write_reg, 101 esp_dma_isintr, 102 esp_dma_reset, 103 esp_dma_intr, 104 esp_dma_setup, 105 esp_dma_go, 106 esp_dma_stop, 107 esp_dma_isactive, 108 NULL, /* gl_clear_latched_intr */ 109 }; 110 111 int 112 espmatch_obio(device_t parent, cfdata_t cf, void *aux) 113 { 114 union obio_attach_args *uoba = aux; 115 struct obio4_attach_args *oba; 116 117 if (uoba->uoba_isobio4 == 0) 118 return 0; 119 120 oba = &uoba->uoba_oba4; 121 return bus_space_probe(oba->oba_bustag, oba->oba_paddr, 122 1, /* probe size */ 123 0, /* offset */ 124 0, /* flags */ 125 NULL, NULL); 126 } 127 128 void 129 espattach_obio(device_t parent, device_t self, void *aux) 130 { 131 struct esp_softc *esc = device_private(self); 132 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 133 union obio_attach_args *uoba = aux; 134 struct obio4_attach_args *oba = &uoba->uoba_oba4; 135 device_t dma_dev; 136 137 sc->sc_dev = self; 138 139 esc->sc_bustag = oba->oba_bustag; 140 esc->sc_dmatag = oba->oba_dmatag; 141 142 sc->sc_id = 7; 143 sc->sc_freq = 24000000; 144 145 /* 146 * Find the DMA by poking around the dma device structures and 147 * set the reverse pointer. 148 */ 149 dma_dev = device_find_by_driver_unit("dma", device_unit(self)); 150 if (dma_dev == NULL) 151 panic("%s: no corresponding DMA device", device_xname(self)); 152 esc->sc_dma = device_private(dma_dev); 153 esc->sc_dma->sc_client = sc; 154 155 if (bus_space_map(oba->oba_bustag, oba->oba_paddr, 156 16, /* size (of ncr53c9xreg) */ 157 BUS_SPACE_MAP_LINEAR, 158 &esc->sc_reg) != 0) { 159 aprint_error(": cannot map registers\n"); 160 return; 161 } 162 163 /* 164 * Set up glue for MI code early; we use some of it here. 165 */ 166 sc->sc_glue = &esp_obio_glue; 167 168 /* gimme MHz */ 169 sc->sc_freq /= 1000000; 170 171 /* 172 * XXX More of this should be in ncr53c9x_attach(), but 173 * XXX should we really poke around the chip that much in 174 * XXX the MI code? Think about this more... 175 */ 176 177 /* 178 * It is necessary to try to load the 2nd config register here, 179 * to find out what rev the esp chip is, else the ncr53c9x_reset 180 * will not set up the defaults correctly. 181 */ 182 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 183 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 184 sc->sc_cfg3 = NCRCFG3_CDB; 185 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 186 187 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 188 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 189 sc->sc_rev = NCR_VARIANT_ESP100; 190 } else { 191 sc->sc_cfg2 = NCRCFG2_SCSI2; 192 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 193 sc->sc_cfg3 = 0; 194 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 195 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 196 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 197 if (NCR_READ_REG(sc, NCR_CFG3) != 198 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 199 sc->sc_rev = NCR_VARIANT_ESP100A; 200 } else { 201 /* NCRCFG2_FE enables > 64K transfers */ 202 sc->sc_cfg2 |= NCRCFG2_FE; 203 sc->sc_cfg3 = 0; 204 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 205 sc->sc_rev = NCR_VARIANT_ESP200; 206 } 207 } 208 209 /* 210 * XXX minsync and maxxfer _should_ be set up in MI code, 211 * XXX but it appears to have some dependency on what sort 212 * XXX of DMA we're hooked up to, etc. 213 */ 214 215 /* 216 * This is the value used to start sync negotiations 217 * Note that the NCR register "SYNCTP" is programmed 218 * in "clocks per byte", and has a minimum value of 4. 219 * The SCSI period used in negotiation is one-fourth 220 * of the time (in nanoseconds) needed to transfer one byte. 221 * Since the chip's clock is given in MHz, we have the following 222 * formula: 4 * period = (1000 / freq) * 4 223 */ 224 sc->sc_minsync = 1000 / sc->sc_freq; 225 226 /* 227 * Alas, we must now modify the value a bit, because it's 228 * only valid when can switch on FASTCLK and FASTSCSI bits 229 * in config register 3... 230 */ 231 switch (sc->sc_rev) { 232 case NCR_VARIANT_ESP100: 233 sc->sc_maxxfer = 64 * 1024; 234 sc->sc_minsync = 0; /* No synch on old chip? */ 235 break; 236 237 case NCR_VARIANT_ESP100A: 238 sc->sc_maxxfer = 64 * 1024; 239 /* Min clocks/byte is 5 */ 240 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 241 break; 242 243 case NCR_VARIANT_ESP200: 244 sc->sc_maxxfer = 16 * 1024 * 1024; 245 /* XXX - do actually set FAST* bits */ 246 break; 247 } 248 249 /* Establish interrupt channel */ 250 bus_intr_establish(esc->sc_bustag, oba->oba_pri, IPL_BIO, 251 ncr53c9x_intr, sc); 252 253 /* register interrupt stats */ 254 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 255 device_xname(self), "intr"); 256 257 /* Do the common parts of attachment. */ 258 sc->sc_adapter.adapt_minphys = minphys; 259 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 260 ncr53c9x_attach(sc); 261 sc->sc_features |= NCR_F_DMASELECT; 262 } 263 264 /* 265 * Glue functions. 266 */ 267 268 static uint8_t 269 esp_read_reg(struct ncr53c9x_softc *sc, int reg) 270 { 271 struct esp_softc *esc = (struct esp_softc *)sc; 272 273 return bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg * 4); 274 } 275 276 static void 277 esp_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t v) 278 { 279 struct esp_softc *esc = (struct esp_softc *)sc; 280 281 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg * 4, v); 282 } 283 284 static int 285 esp_dma_isintr(struct ncr53c9x_softc *sc) 286 { 287 struct esp_softc *esc = (struct esp_softc *)sc; 288 289 return DMA_ISINTR(esc->sc_dma); 290 } 291 292 static void 293 esp_dma_reset(struct ncr53c9x_softc *sc) 294 { 295 struct esp_softc *esc = (struct esp_softc *)sc; 296 297 DMA_RESET(esc->sc_dma); 298 } 299 300 static int 301 esp_dma_intr(struct ncr53c9x_softc *sc) 302 { 303 struct esp_softc *esc = (struct esp_softc *)sc; 304 305 return DMA_INTR(esc->sc_dma); 306 } 307 308 static int 309 esp_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len, 310 int datain, size_t *dmasize) 311 { 312 struct esp_softc *esc = (struct esp_softc *)sc; 313 314 return DMA_SETUP(esc->sc_dma, addr, len, datain, dmasize); 315 } 316 317 static void 318 esp_dma_go(struct ncr53c9x_softc *sc) 319 { 320 struct esp_softc *esc = (struct esp_softc *)sc; 321 322 DMA_GO(esc->sc_dma); 323 } 324 325 static void 326 esp_dma_stop(struct ncr53c9x_softc *sc) 327 { 328 struct esp_softc *esc = (struct esp_softc *)sc; 329 uint32_t csr; 330 331 csr = L64854_GCSR(esc->sc_dma); 332 csr &= ~D_EN_DMA; 333 L64854_SCSR(esc->sc_dma, csr); 334 } 335 336 static int 337 esp_dma_isactive(struct ncr53c9x_softc *sc) 338 { 339 struct esp_softc *esc = (struct esp_softc *)sc; 340 341 return DMA_ISACTIVE(esc->sc_dma); 342 } 343
Indexes created Mon Sep 29 21:09:56 GMT 2025