esp_obio.c revision 1.3
1 /* $NetBSD: esp_obio.c,v 1.3 1998/10/10 00:28:39 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum; Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center; Paul Kranenburg. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #include <sys/types.h> 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/errno.h> 45 #include <sys/device.h> 46 #include <sys/buf.h> 47 48 #include <dev/scsipi/scsi_all.h> 49 #include <dev/scsipi/scsipi_all.h> 50 #include <dev/scsipi/scsiconf.h> 51 #include <dev/scsipi/scsi_message.h> 52 53 #include <machine/bus.h> 54 #include <machine/autoconf.h> 55 #include <machine/cpu.h> 56 57 #include <dev/ic/lsi64854reg.h> 58 #include <dev/ic/lsi64854var.h> 59 60 #include <dev/ic/ncr53c9xreg.h> 61 #include <dev/ic/ncr53c9xvar.h> 62 63 #include <dev/sbus/sbusvar.h> 64 65 struct esp_softc { 66 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 67 bus_space_tag_t sc_bustag; 68 bus_dma_tag_t sc_dmatag; 69 bus_space_handle_t sc_reg; /* the registers */ 70 struct lsi64854_softc *sc_dma; /* pointer to my dma */ 71 }; 72 73 74 void espattach_obio __P((struct device *, struct device *, void *)); 75 int espmatch_obio __P((struct device *, struct cfdata *, void *)); 76 77 /* Linkup to the rest of the kernel */ 78 struct cfattach esp_obio_ca = { 79 sizeof(struct esp_softc), espmatch_obio, espattach_obio 80 }; 81 82 static struct scsipi_adapter esp_obio_switch = { 83 ncr53c9x_scsi_cmd, 84 minphys, /* no max at this level; handled by DMA code */ 85 NULL, /* scsipi_ioctl */ 86 }; 87 88 static struct scsipi_device esp_obio_dev = { 89 NULL, /* Use default error handler */ 90 NULL, /* have a queue, served by this */ 91 NULL, /* have no async handler */ 92 NULL, /* Use default 'done' routine */ 93 }; 94 95 /* 96 * Functions and the switch for the MI code. 97 */ 98 static u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 99 static void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 100 static int esp_dma_isintr __P((struct ncr53c9x_softc *)); 101 static void esp_dma_reset __P((struct ncr53c9x_softc *)); 102 static int esp_dma_intr __P((struct ncr53c9x_softc *)); 103 static int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 104 size_t *, int, size_t *)); 105 static void esp_dma_go __P((struct ncr53c9x_softc *)); 106 static void esp_dma_stop __P((struct ncr53c9x_softc *)); 107 static int esp_dma_isactive __P((struct ncr53c9x_softc *)); 108 109 static struct ncr53c9x_glue esp_obio_glue = { 110 esp_read_reg, 111 esp_write_reg, 112 esp_dma_isintr, 113 esp_dma_reset, 114 esp_dma_intr, 115 esp_dma_setup, 116 esp_dma_go, 117 esp_dma_stop, 118 esp_dma_isactive, 119 NULL, /* gl_clear_latched_intr */ 120 }; 121 122 int 123 espmatch_obio(parent, cf, aux) 124 struct device *parent; 125 struct cfdata *cf; 126 void *aux; 127 { 128 union obio_attach_args *uoba = aux; 129 struct obio4_attach_args *oba; 130 131 if (uoba->uoba_isobio4 == 0) 132 return (0); 133 134 oba = &uoba->uoba_oba4; 135 return (bus_space_probe(oba->oba_bustag, 0, oba->oba_paddr, 136 1, /* probe size */ 137 0, /* offset */ 138 0, /* flags */ 139 NULL, NULL)); 140 } 141 142 void 143 espattach_obio(parent, self, aux) 144 struct device *parent, *self; 145 void *aux; 146 { 147 union obio_attach_args *uoba = aux; 148 struct obio4_attach_args *oba = &uoba->uoba_oba4; 149 struct esp_softc *esc = (void *)self; 150 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 151 152 esc->sc_bustag = oba->oba_bustag; 153 esc->sc_dmatag = oba->oba_dmatag; 154 155 sc->sc_id = 7; 156 sc->sc_freq = 24000000; 157 158 /* 159 * Find the DMA by poking around the dma device structures 160 */ 161 esc->sc_dma = (struct lsi64854_softc *) 162 getdevunit("dma", sc->sc_dev.dv_unit); 163 164 /* 165 * and a back pointer to us, for DMA 166 */ 167 if (esc->sc_dma) 168 esc->sc_dma->sc_client = sc; 169 else { 170 printf("\n"); 171 panic("espattach: no dma found"); 172 } 173 174 if (obio_bus_map(oba->oba_bustag, oba->oba_paddr, 175 0, /* offset */ 176 16, /* size (of ncr53c9xreg) */ 177 BUS_SPACE_MAP_LINEAR, 178 0, &esc->sc_reg) != 0) { 179 printf("%s @ obio: cannot map registers\n", self->dv_xname); 180 return; 181 } 182 183 if (oba->oba_bp != NULL && strcmp(oba->oba_bp->name, "esp") == 0 && 184 oba->oba_bp->val[0] == -1 && 185 oba->oba_bp->val[1] == sc->sc_dev.dv_unit) 186 bootpath_store(1, oba->oba_bp + 1); 187 188 189 /* 190 * Set up glue for MI code early; we use some of it here. 191 */ 192 sc->sc_glue = &esp_obio_glue; 193 194 /* gimme Mhz */ 195 sc->sc_freq /= 1000000; 196 197 /* 198 * XXX More of this should be in ncr53c9x_attach(), but 199 * XXX should we really poke around the chip that much in 200 * XXX the MI code? Think about this more... 201 */ 202 203 /* 204 * It is necessary to try to load the 2nd config register here, 205 * to find out what rev the esp chip is, else the ncr53c9x_reset 206 * will not set up the defaults correctly. 207 */ 208 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 209 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 210 sc->sc_cfg3 = NCRCFG3_CDB; 211 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 212 213 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 214 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 215 sc->sc_rev = NCR_VARIANT_ESP100; 216 } else { 217 sc->sc_cfg2 = NCRCFG2_SCSI2; 218 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 219 sc->sc_cfg3 = 0; 220 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 221 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 222 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 223 if (NCR_READ_REG(sc, NCR_CFG3) != 224 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 225 sc->sc_rev = NCR_VARIANT_ESP100A; 226 } else { 227 /* NCRCFG2_FE enables > 64K transfers */ 228 sc->sc_cfg2 |= NCRCFG2_FE; 229 sc->sc_cfg3 = 0; 230 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 231 sc->sc_rev = NCR_VARIANT_ESP200; 232 } 233 } 234 235 /* 236 * XXX minsync and maxxfer _should_ be set up in MI code, 237 * XXX but it appears to have some dependency on what sort 238 * XXX of DMA we're hooked up to, etc. 239 */ 240 241 /* 242 * This is the value used to start sync negotiations 243 * Note that the NCR register "SYNCTP" is programmed 244 * in "clocks per byte", and has a minimum value of 4. 245 * The SCSI period used in negotiation is one-fourth 246 * of the time (in nanoseconds) needed to transfer one byte. 247 * Since the chip's clock is given in MHz, we have the following 248 * formula: 4 * period = (1000 / freq) * 4 249 */ 250 sc->sc_minsync = 1000 / sc->sc_freq; 251 252 /* 253 * Alas, we must now modify the value a bit, because it's 254 * only valid when can switch on FASTCLK and FASTSCSI bits 255 * in config register 3... 256 */ 257 switch (sc->sc_rev) { 258 case NCR_VARIANT_ESP100: 259 sc->sc_maxxfer = 64 * 1024; 260 sc->sc_minsync = 0; /* No synch on old chip? */ 261 break; 262 263 case NCR_VARIANT_ESP100A: 264 sc->sc_maxxfer = 64 * 1024; 265 /* Min clocks/byte is 5 */ 266 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 267 break; 268 269 case NCR_VARIANT_ESP200: 270 sc->sc_maxxfer = 16 * 1024 * 1024; 271 /* XXX - do actually set FAST* bits */ 272 break; 273 } 274 275 /* Establish interrupt channel */ 276 bus_intr_establish(esc->sc_bustag, 277 oba->oba_pri, 0, 278 (int(*)__P((void*)))ncr53c9x_intr, sc); 279 280 /* register interrupt stats */ 281 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 282 283 /* Do the common parts of attachment. */ 284 ncr53c9x_attach(sc, &esp_obio_switch, &esp_obio_dev); 285 286 /* Turn on target selection using the `dma' method */ 287 ncr53c9x_dmaselect = 1; 288 289 bootpath_store(1, NULL); 290 } 291 292 /* 293 * Glue functions. 294 */ 295 296 u_char 297 esp_read_reg(sc, reg) 298 struct ncr53c9x_softc *sc; 299 int reg; 300 { 301 struct esp_softc *esc = (struct esp_softc *)sc; 302 303 return (bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg * 4)); 304 } 305 306 void 307 esp_write_reg(sc, reg, v) 308 struct ncr53c9x_softc *sc; 309 int reg; 310 u_char v; 311 { 312 struct esp_softc *esc = (struct esp_softc *)sc; 313 314 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg * 4, v); 315 } 316 317 int 318 esp_dma_isintr(sc) 319 struct ncr53c9x_softc *sc; 320 { 321 struct esp_softc *esc = (struct esp_softc *)sc; 322 323 return (DMA_ISINTR(esc->sc_dma)); 324 } 325 326 void 327 esp_dma_reset(sc) 328 struct ncr53c9x_softc *sc; 329 { 330 struct esp_softc *esc = (struct esp_softc *)sc; 331 332 DMA_RESET(esc->sc_dma); 333 } 334 335 int 336 esp_dma_intr(sc) 337 struct ncr53c9x_softc *sc; 338 { 339 struct esp_softc *esc = (struct esp_softc *)sc; 340 341 return (DMA_INTR(esc->sc_dma)); 342 } 343 344 int 345 esp_dma_setup(sc, addr, len, datain, dmasize) 346 struct ncr53c9x_softc *sc; 347 caddr_t *addr; 348 size_t *len; 349 int datain; 350 size_t *dmasize; 351 { 352 struct esp_softc *esc = (struct esp_softc *)sc; 353 354 return (DMA_SETUP(esc->sc_dma, addr, len, datain, dmasize)); 355 } 356 357 void 358 esp_dma_go(sc) 359 struct ncr53c9x_softc *sc; 360 { 361 struct esp_softc *esc = (struct esp_softc *)sc; 362 363 DMA_GO(esc->sc_dma); 364 } 365 366 void 367 esp_dma_stop(sc) 368 struct ncr53c9x_softc *sc; 369 { 370 struct esp_softc *esc = (struct esp_softc *)sc; 371 u_int32_t csr; 372 373 csr = L64854_GCSR(esc->sc_dma); 374 csr &= ~D_EN_DMA; 375 L64854_SCSR(esc->sc_dma, csr); 376 } 377 378 int 379 esp_dma_isactive(sc) 380 struct ncr53c9x_softc *sc; 381 { 382 struct esp_softc *esc = (struct esp_softc *)sc; 383 384 return (DMA_ISACTIVE(esc->sc_dma)); 385 } 386
Indexes created Sat Oct 11 14:09:46 GMT 2025