esp_obio.c revision 1.4
1 /* $NetBSD: esp_obio.c,v 1.4 1998/11/19 21:49:17 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum; Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center; Paul Kranenburg. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #include <sys/types.h> 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/errno.h> 45 #include <sys/device.h> 46 #include <sys/buf.h> 47 48 #include <dev/scsipi/scsi_all.h> 49 #include <dev/scsipi/scsipi_all.h> 50 #include <dev/scsipi/scsiconf.h> 51 #include <dev/scsipi/scsi_message.h> 52 53 #include <machine/bus.h> 54 #include <machine/autoconf.h> 55 #include <machine/cpu.h> 56 57 #include <dev/ic/lsi64854reg.h> 58 #include <dev/ic/lsi64854var.h> 59 60 #include <dev/ic/ncr53c9xreg.h> 61 #include <dev/ic/ncr53c9xvar.h> 62 63 #include <dev/sbus/sbusvar.h> 64 65 struct esp_softc { 66 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 67 bus_space_tag_t sc_bustag; 68 bus_dma_tag_t sc_dmatag; 69 bus_space_handle_t sc_reg; /* the registers */ 70 struct lsi64854_softc *sc_dma; /* pointer to my dma */ 71 }; 72 73 74 void espattach_obio __P((struct device *, struct device *, void *)); 75 int espmatch_obio __P((struct device *, struct cfdata *, void *)); 76 77 /* Linkup to the rest of the kernel */ 78 struct cfattach esp_obio_ca = { 79 sizeof(struct esp_softc), espmatch_obio, espattach_obio 80 }; 81 82 static struct scsipi_device esp_obio_dev = { 83 NULL, /* Use default error handler */ 84 NULL, /* have a queue, served by this */ 85 NULL, /* have no async handler */ 86 NULL, /* Use default 'done' routine */ 87 }; 88 89 /* 90 * Functions and the switch for the MI code. 91 */ 92 static u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 93 static void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 94 static int esp_dma_isintr __P((struct ncr53c9x_softc *)); 95 static void esp_dma_reset __P((struct ncr53c9x_softc *)); 96 static int esp_dma_intr __P((struct ncr53c9x_softc *)); 97 static int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 98 size_t *, int, size_t *)); 99 static void esp_dma_go __P((struct ncr53c9x_softc *)); 100 static void esp_dma_stop __P((struct ncr53c9x_softc *)); 101 static int esp_dma_isactive __P((struct ncr53c9x_softc *)); 102 103 static struct ncr53c9x_glue esp_obio_glue = { 104 esp_read_reg, 105 esp_write_reg, 106 esp_dma_isintr, 107 esp_dma_reset, 108 esp_dma_intr, 109 esp_dma_setup, 110 esp_dma_go, 111 esp_dma_stop, 112 esp_dma_isactive, 113 NULL, /* gl_clear_latched_intr */ 114 }; 115 116 int 117 espmatch_obio(parent, cf, aux) 118 struct device *parent; 119 struct cfdata *cf; 120 void *aux; 121 { 122 union obio_attach_args *uoba = aux; 123 struct obio4_attach_args *oba; 124 125 if (uoba->uoba_isobio4 == 0) 126 return (0); 127 128 oba = &uoba->uoba_oba4; 129 return (bus_space_probe(oba->oba_bustag, 0, oba->oba_paddr, 130 1, /* probe size */ 131 0, /* offset */ 132 0, /* flags */ 133 NULL, NULL)); 134 } 135 136 void 137 espattach_obio(parent, self, aux) 138 struct device *parent, *self; 139 void *aux; 140 { 141 union obio_attach_args *uoba = aux; 142 struct obio4_attach_args *oba = &uoba->uoba_oba4; 143 struct esp_softc *esc = (void *)self; 144 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 145 146 esc->sc_bustag = oba->oba_bustag; 147 esc->sc_dmatag = oba->oba_dmatag; 148 149 sc->sc_id = 7; 150 sc->sc_freq = 24000000; 151 152 /* 153 * Find the DMA by poking around the dma device structures 154 */ 155 esc->sc_dma = (struct lsi64854_softc *) 156 getdevunit("dma", sc->sc_dev.dv_unit); 157 158 /* 159 * and a back pointer to us, for DMA 160 */ 161 if (esc->sc_dma) 162 esc->sc_dma->sc_client = sc; 163 else { 164 printf("\n"); 165 panic("espattach: no dma found"); 166 } 167 168 if (obio_bus_map(oba->oba_bustag, oba->oba_paddr, 169 0, /* offset */ 170 16, /* size (of ncr53c9xreg) */ 171 BUS_SPACE_MAP_LINEAR, 172 0, &esc->sc_reg) != 0) { 173 printf("%s @ obio: cannot map registers\n", self->dv_xname); 174 return; 175 } 176 177 if (oba->oba_bp != NULL && strcmp(oba->oba_bp->name, "esp") == 0 && 178 oba->oba_bp->val[0] == -1 && 179 oba->oba_bp->val[1] == sc->sc_dev.dv_unit) 180 bootpath_store(1, oba->oba_bp + 1); 181 182 183 /* 184 * Set up glue for MI code early; we use some of it here. 185 */ 186 sc->sc_glue = &esp_obio_glue; 187 188 /* gimme Mhz */ 189 sc->sc_freq /= 1000000; 190 191 /* 192 * XXX More of this should be in ncr53c9x_attach(), but 193 * XXX should we really poke around the chip that much in 194 * XXX the MI code? Think about this more... 195 */ 196 197 /* 198 * It is necessary to try to load the 2nd config register here, 199 * to find out what rev the esp chip is, else the ncr53c9x_reset 200 * will not set up the defaults correctly. 201 */ 202 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 203 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 204 sc->sc_cfg3 = NCRCFG3_CDB; 205 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 206 207 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 208 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 209 sc->sc_rev = NCR_VARIANT_ESP100; 210 } else { 211 sc->sc_cfg2 = NCRCFG2_SCSI2; 212 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 213 sc->sc_cfg3 = 0; 214 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 215 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 216 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 217 if (NCR_READ_REG(sc, NCR_CFG3) != 218 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 219 sc->sc_rev = NCR_VARIANT_ESP100A; 220 } else { 221 /* NCRCFG2_FE enables > 64K transfers */ 222 sc->sc_cfg2 |= NCRCFG2_FE; 223 sc->sc_cfg3 = 0; 224 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 225 sc->sc_rev = NCR_VARIANT_ESP200; 226 } 227 } 228 229 /* 230 * XXX minsync and maxxfer _should_ be set up in MI code, 231 * XXX but it appears to have some dependency on what sort 232 * XXX of DMA we're hooked up to, etc. 233 */ 234 235 /* 236 * This is the value used to start sync negotiations 237 * Note that the NCR register "SYNCTP" is programmed 238 * in "clocks per byte", and has a minimum value of 4. 239 * The SCSI period used in negotiation is one-fourth 240 * of the time (in nanoseconds) needed to transfer one byte. 241 * Since the chip's clock is given in MHz, we have the following 242 * formula: 4 * period = (1000 / freq) * 4 243 */ 244 sc->sc_minsync = 1000 / sc->sc_freq; 245 246 /* 247 * Alas, we must now modify the value a bit, because it's 248 * only valid when can switch on FASTCLK and FASTSCSI bits 249 * in config register 3... 250 */ 251 switch (sc->sc_rev) { 252 case NCR_VARIANT_ESP100: 253 sc->sc_maxxfer = 64 * 1024; 254 sc->sc_minsync = 0; /* No synch on old chip? */ 255 break; 256 257 case NCR_VARIANT_ESP100A: 258 sc->sc_maxxfer = 64 * 1024; 259 /* Min clocks/byte is 5 */ 260 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 261 break; 262 263 case NCR_VARIANT_ESP200: 264 sc->sc_maxxfer = 16 * 1024 * 1024; 265 /* XXX - do actually set FAST* bits */ 266 break; 267 } 268 269 /* Establish interrupt channel */ 270 bus_intr_establish(esc->sc_bustag, 271 oba->oba_pri, 0, 272 (int(*)__P((void*)))ncr53c9x_intr, sc); 273 274 /* register interrupt stats */ 275 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 276 277 /* Do the common parts of attachment. */ 278 sc->sc_adapter.scsipi_cmd = ncr53c9x_scsi_cmd; 279 sc->sc_adapter.scsipi_minphys = minphys; 280 ncr53c9x_attach(sc, &esp_obio_dev); 281 282 /* Turn on target selection using the `dma' method */ 283 ncr53c9x_dmaselect = 1; 284 285 bootpath_store(1, NULL); 286 } 287 288 /* 289 * Glue functions. 290 */ 291 292 u_char 293 esp_read_reg(sc, reg) 294 struct ncr53c9x_softc *sc; 295 int reg; 296 { 297 struct esp_softc *esc = (struct esp_softc *)sc; 298 299 return (bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg * 4)); 300 } 301 302 void 303 esp_write_reg(sc, reg, v) 304 struct ncr53c9x_softc *sc; 305 int reg; 306 u_char v; 307 { 308 struct esp_softc *esc = (struct esp_softc *)sc; 309 310 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg * 4, v); 311 } 312 313 int 314 esp_dma_isintr(sc) 315 struct ncr53c9x_softc *sc; 316 { 317 struct esp_softc *esc = (struct esp_softc *)sc; 318 319 return (DMA_ISINTR(esc->sc_dma)); 320 } 321 322 void 323 esp_dma_reset(sc) 324 struct ncr53c9x_softc *sc; 325 { 326 struct esp_softc *esc = (struct esp_softc *)sc; 327 328 DMA_RESET(esc->sc_dma); 329 } 330 331 int 332 esp_dma_intr(sc) 333 struct ncr53c9x_softc *sc; 334 { 335 struct esp_softc *esc = (struct esp_softc *)sc; 336 337 return (DMA_INTR(esc->sc_dma)); 338 } 339 340 int 341 esp_dma_setup(sc, addr, len, datain, dmasize) 342 struct ncr53c9x_softc *sc; 343 caddr_t *addr; 344 size_t *len; 345 int datain; 346 size_t *dmasize; 347 { 348 struct esp_softc *esc = (struct esp_softc *)sc; 349 350 return (DMA_SETUP(esc->sc_dma, addr, len, datain, dmasize)); 351 } 352 353 void 354 esp_dma_go(sc) 355 struct ncr53c9x_softc *sc; 356 { 357 struct esp_softc *esc = (struct esp_softc *)sc; 358 359 DMA_GO(esc->sc_dma); 360 } 361 362 void 363 esp_dma_stop(sc) 364 struct ncr53c9x_softc *sc; 365 { 366 struct esp_softc *esc = (struct esp_softc *)sc; 367 u_int32_t csr; 368 369 csr = L64854_GCSR(esc->sc_dma); 370 csr &= ~D_EN_DMA; 371 L64854_SCSR(esc->sc_dma, csr); 372 } 373 374 int 375 esp_dma_isactive(sc) 376 struct ncr53c9x_softc *sc; 377 { 378 struct esp_softc *esc = (struct esp_softc *)sc; 379 380 return (DMA_ISACTIVE(esc->sc_dma)); 381 } 382
Indexes created Tue Sep 30 17:09:57 GMT 2025