esp_obio.c revision 1.6
1 /* $NetBSD: esp_obio.c,v 1.6 2000/06/04 19:15:01 cgd Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum; Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center; Paul Kranenburg. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #include <sys/types.h> 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/errno.h> 45 #include <sys/device.h> 46 #include <sys/buf.h> 47 48 #include <dev/scsipi/scsi_all.h> 49 #include <dev/scsipi/scsipi_all.h> 50 #include <dev/scsipi/scsiconf.h> 51 #include <dev/scsipi/scsi_message.h> 52 53 #include <machine/bus.h> 54 #include <machine/autoconf.h> 55 #include <machine/cpu.h> 56 57 #include <dev/ic/lsi64854reg.h> 58 #include <dev/ic/lsi64854var.h> 59 60 #include <dev/ic/ncr53c9xreg.h> 61 #include <dev/ic/ncr53c9xvar.h> 62 63 #include <dev/sbus/sbusvar.h> 64 65 struct esp_softc { 66 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 67 bus_space_tag_t sc_bustag; 68 bus_dma_tag_t sc_dmatag; 69 bus_space_handle_t sc_reg; /* the registers */ 70 struct lsi64854_softc *sc_dma; /* pointer to my dma */ 71 }; 72 73 74 void espattach_obio __P((struct device *, struct device *, void *)); 75 int espmatch_obio __P((struct device *, struct cfdata *, void *)); 76 77 /* Linkup to the rest of the kernel */ 78 struct cfattach esp_obio_ca = { 79 sizeof(struct esp_softc), espmatch_obio, espattach_obio 80 }; 81 82 static struct scsipi_device esp_obio_dev = { 83 NULL, /* Use default error handler */ 84 NULL, /* have a queue, served by this */ 85 NULL, /* have no async handler */ 86 NULL, /* Use default 'done' routine */ 87 }; 88 89 /* 90 * Functions and the switch for the MI code. 91 */ 92 static u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 93 static void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 94 static int esp_dma_isintr __P((struct ncr53c9x_softc *)); 95 static void esp_dma_reset __P((struct ncr53c9x_softc *)); 96 static int esp_dma_intr __P((struct ncr53c9x_softc *)); 97 static int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 98 size_t *, int, size_t *)); 99 static void esp_dma_go __P((struct ncr53c9x_softc *)); 100 static void esp_dma_stop __P((struct ncr53c9x_softc *)); 101 static int esp_dma_isactive __P((struct ncr53c9x_softc *)); 102 103 static struct ncr53c9x_glue esp_obio_glue = { 104 esp_read_reg, 105 esp_write_reg, 106 esp_dma_isintr, 107 esp_dma_reset, 108 esp_dma_intr, 109 esp_dma_setup, 110 esp_dma_go, 111 esp_dma_stop, 112 esp_dma_isactive, 113 NULL, /* gl_clear_latched_intr */ 114 }; 115 116 int 117 espmatch_obio(parent, cf, aux) 118 struct device *parent; 119 struct cfdata *cf; 120 void *aux; 121 { 122 union obio_attach_args *uoba = aux; 123 struct obio4_attach_args *oba; 124 125 if (uoba->uoba_isobio4 == 0) 126 return (0); 127 128 oba = &uoba->uoba_oba4; 129 return (bus_space_probe(oba->oba_bustag, 0, oba->oba_paddr, 130 1, /* probe size */ 131 0, /* offset */ 132 0, /* flags */ 133 NULL, NULL)); 134 } 135 136 void 137 espattach_obio(parent, self, aux) 138 struct device *parent, *self; 139 void *aux; 140 { 141 union obio_attach_args *uoba = aux; 142 struct obio4_attach_args *oba = &uoba->uoba_oba4; 143 struct esp_softc *esc = (void *)self; 144 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 145 146 esc->sc_bustag = oba->oba_bustag; 147 esc->sc_dmatag = oba->oba_dmatag; 148 149 sc->sc_id = 7; 150 sc->sc_freq = 24000000; 151 152 /* 153 * Find the DMA by poking around the dma device structures 154 */ 155 esc->sc_dma = (struct lsi64854_softc *) 156 getdevunit("dma", sc->sc_dev.dv_unit); 157 158 /* 159 * and a back pointer to us, for DMA 160 */ 161 if (esc->sc_dma) 162 esc->sc_dma->sc_client = sc; 163 else { 164 printf("\n"); 165 panic("espattach: no dma found"); 166 } 167 168 if (obio_bus_map(oba->oba_bustag, oba->oba_paddr, 169 0, /* offset */ 170 16, /* size (of ncr53c9xreg) */ 171 BUS_SPACE_MAP_LINEAR, 172 0, &esc->sc_reg) != 0) { 173 printf("%s @ obio: cannot map registers\n", self->dv_xname); 174 return; 175 } 176 177 /* 178 * Set up glue for MI code early; we use some of it here. 179 */ 180 sc->sc_glue = &esp_obio_glue; 181 182 /* gimme Mhz */ 183 sc->sc_freq /= 1000000; 184 185 /* 186 * XXX More of this should be in ncr53c9x_attach(), but 187 * XXX should we really poke around the chip that much in 188 * XXX the MI code? Think about this more... 189 */ 190 191 /* 192 * It is necessary to try to load the 2nd config register here, 193 * to find out what rev the esp chip is, else the ncr53c9x_reset 194 * will not set up the defaults correctly. 195 */ 196 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 197 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 198 sc->sc_cfg3 = NCRCFG3_CDB; 199 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 200 201 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 202 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 203 sc->sc_rev = NCR_VARIANT_ESP100; 204 } else { 205 sc->sc_cfg2 = NCRCFG2_SCSI2; 206 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 207 sc->sc_cfg3 = 0; 208 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 209 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 210 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 211 if (NCR_READ_REG(sc, NCR_CFG3) != 212 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 213 sc->sc_rev = NCR_VARIANT_ESP100A; 214 } else { 215 /* NCRCFG2_FE enables > 64K transfers */ 216 sc->sc_cfg2 |= NCRCFG2_FE; 217 sc->sc_cfg3 = 0; 218 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 219 sc->sc_rev = NCR_VARIANT_ESP200; 220 } 221 } 222 223 /* 224 * XXX minsync and maxxfer _should_ be set up in MI code, 225 * XXX but it appears to have some dependency on what sort 226 * XXX of DMA we're hooked up to, etc. 227 */ 228 229 /* 230 * This is the value used to start sync negotiations 231 * Note that the NCR register "SYNCTP" is programmed 232 * in "clocks per byte", and has a minimum value of 4. 233 * The SCSI period used in negotiation is one-fourth 234 * of the time (in nanoseconds) needed to transfer one byte. 235 * Since the chip's clock is given in MHz, we have the following 236 * formula: 4 * period = (1000 / freq) * 4 237 */ 238 sc->sc_minsync = 1000 / sc->sc_freq; 239 240 /* 241 * Alas, we must now modify the value a bit, because it's 242 * only valid when can switch on FASTCLK and FASTSCSI bits 243 * in config register 3... 244 */ 245 switch (sc->sc_rev) { 246 case NCR_VARIANT_ESP100: 247 sc->sc_maxxfer = 64 * 1024; 248 sc->sc_minsync = 0; /* No synch on old chip? */ 249 break; 250 251 case NCR_VARIANT_ESP100A: 252 sc->sc_maxxfer = 64 * 1024; 253 /* Min clocks/byte is 5 */ 254 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 255 break; 256 257 case NCR_VARIANT_ESP200: 258 sc->sc_maxxfer = 16 * 1024 * 1024; 259 /* XXX - do actually set FAST* bits */ 260 break; 261 } 262 263 /* Establish interrupt channel */ 264 bus_intr_establish(esc->sc_bustag, 265 oba->oba_pri, 0, 266 (int(*)__P((void*)))ncr53c9x_intr, sc); 267 268 /* register interrupt stats */ 269 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 270 sc->sc_dev.dv_xname, "intr"); 271 272 /* Do the common parts of attachment. */ 273 sc->sc_adapter.scsipi_cmd = ncr53c9x_scsi_cmd; 274 sc->sc_adapter.scsipi_minphys = minphys; 275 ncr53c9x_attach(sc, &esp_obio_dev); 276 277 /* Turn on target selection using the `dma' method */ 278 ncr53c9x_dmaselect = 1; 279 } 280 281 /* 282 * Glue functions. 283 */ 284 285 u_char 286 esp_read_reg(sc, reg) 287 struct ncr53c9x_softc *sc; 288 int reg; 289 { 290 struct esp_softc *esc = (struct esp_softc *)sc; 291 292 return (bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg * 4)); 293 } 294 295 void 296 esp_write_reg(sc, reg, v) 297 struct ncr53c9x_softc *sc; 298 int reg; 299 u_char v; 300 { 301 struct esp_softc *esc = (struct esp_softc *)sc; 302 303 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg * 4, v); 304 } 305 306 int 307 esp_dma_isintr(sc) 308 struct ncr53c9x_softc *sc; 309 { 310 struct esp_softc *esc = (struct esp_softc *)sc; 311 312 return (DMA_ISINTR(esc->sc_dma)); 313 } 314 315 void 316 esp_dma_reset(sc) 317 struct ncr53c9x_softc *sc; 318 { 319 struct esp_softc *esc = (struct esp_softc *)sc; 320 321 DMA_RESET(esc->sc_dma); 322 } 323 324 int 325 esp_dma_intr(sc) 326 struct ncr53c9x_softc *sc; 327 { 328 struct esp_softc *esc = (struct esp_softc *)sc; 329 330 return (DMA_INTR(esc->sc_dma)); 331 } 332 333 int 334 esp_dma_setup(sc, addr, len, datain, dmasize) 335 struct ncr53c9x_softc *sc; 336 caddr_t *addr; 337 size_t *len; 338 int datain; 339 size_t *dmasize; 340 { 341 struct esp_softc *esc = (struct esp_softc *)sc; 342 343 return (DMA_SETUP(esc->sc_dma, addr, len, datain, dmasize)); 344 } 345 346 void 347 esp_dma_go(sc) 348 struct ncr53c9x_softc *sc; 349 { 350 struct esp_softc *esc = (struct esp_softc *)sc; 351 352 DMA_GO(esc->sc_dma); 353 } 354 355 void 356 esp_dma_stop(sc) 357 struct ncr53c9x_softc *sc; 358 { 359 struct esp_softc *esc = (struct esp_softc *)sc; 360 u_int32_t csr; 361 362 csr = L64854_GCSR(esc->sc_dma); 363 csr &= ~D_EN_DMA; 364 L64854_SCSR(esc->sc_dma, csr); 365 } 366 367 int 368 esp_dma_isactive(sc) 369 struct ncr53c9x_softc *sc; 370 { 371 struct esp_softc *esc = (struct esp_softc *)sc; 372 373 return (DMA_ISACTIVE(esc->sc_dma)); 374 } 375
Indexes created Tue Sep 30 11:09:46 GMT 2025